1 /* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _sdma1_4_0_SH_MASK_HEADER 22 #define _sdma1_4_0_SH_MASK_HEADER 23 24 25 // addressBlock: sdma1_sdma1dec 26 //SDMA1_UCODE_ADDR 27 #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 28 #define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29 //SDMA1_UCODE_DATA 30 #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 31 #define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32 //SDMA1_VM_CNTL 33 #define SDMA1_VM_CNTL__CMD__SHIFT 0x0 34 #define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL 35 //SDMA1_VM_CTX_LO 36 #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 37 #define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38 //SDMA1_VM_CTX_HI 39 #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 40 #define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41 //SDMA1_ACTIVE_FCN_ID 42 #define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43 #define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44 #define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45 #define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46 #define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47 #define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48 //SDMA1_VM_CTX_CNTL 49 #define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 50 #define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 51 #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52 #define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53 //SDMA1_VIRT_RESET_REQ 54 #define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 55 #define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f 56 #define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57 #define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L 58 //SDMA1_VF_ENABLE 59 #define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 60 #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 61 //SDMA1_CONTEXT_REG_TYPE0 62 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 63 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 64 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 65 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 66 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 67 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 68 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 69 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 70 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 71 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 72 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa 73 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb 74 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc 75 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd 76 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe 77 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf 78 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 79 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 80 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 81 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 82 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L 83 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L 84 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L 85 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L 86 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L 87 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L 88 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L 89 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 90 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 91 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 92 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L 93 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L 94 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L 95 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L 96 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L 97 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L 98 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L 99 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L 100 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L 101 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L 102 //SDMA1_CONTEXT_REG_TYPE1 103 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 104 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 105 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa 106 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb 107 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc 108 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd 109 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 110 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf 111 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 112 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 113 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 114 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 115 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 116 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 117 #define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 118 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L 119 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L 120 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L 121 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L 122 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L 123 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L 124 #define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 125 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L 126 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L 127 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L 128 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 129 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 130 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L 131 #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 132 #define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 133 //SDMA1_CONTEXT_REG_TYPE2 134 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 135 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 136 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 137 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 138 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 139 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 140 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 141 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 142 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 143 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 144 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 145 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L 146 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L 147 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L 148 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L 149 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L 150 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L 151 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L 152 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L 153 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L 154 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L 155 #define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 156 //SDMA1_CONTEXT_REG_TYPE3 157 #define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 158 #define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 159 //SDMA1_PUB_REG_TYPE0 160 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 161 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 162 #define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 163 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 164 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 165 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 166 #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 167 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 168 #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 169 #define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 170 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb 171 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc 172 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd 173 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe 174 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf 175 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 176 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 177 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 178 #define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 179 #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 180 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 181 #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a 182 #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b 183 #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c 184 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d 185 #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e 186 #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f 187 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L 188 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L 189 #define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 190 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L 191 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L 192 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L 193 #define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L 194 #define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L 195 #define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L 196 #define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 197 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L 198 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L 199 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L 200 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L 201 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L 202 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L 203 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L 204 #define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L 205 #define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L 206 #define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 207 #define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 208 #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L 209 #define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L 210 #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L 211 #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L 212 #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L 213 #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L 214 //SDMA1_PUB_REG_TYPE1 215 #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 216 #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 217 #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 218 #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 219 #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 220 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 221 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 222 #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 223 #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 224 #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 225 #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa 226 #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb 227 #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc 228 #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd 229 #define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 230 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 231 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 232 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 233 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 234 #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 235 #define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 236 #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 237 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 238 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 239 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 240 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 241 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a 242 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b 243 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c 244 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d 245 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e 246 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f 247 #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L 248 #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 249 #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L 250 #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L 251 #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L 252 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L 253 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L 254 #define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L 255 #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L 256 #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L 257 #define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L 258 #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L 259 #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L 260 #define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L 261 #define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 262 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 263 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 264 #define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 265 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L 266 #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L 267 #define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L 268 #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L 269 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L 270 #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L 271 #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L 272 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L 273 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L 274 #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L 275 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L 276 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L 277 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L 278 #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L 279 //SDMA1_PUB_REG_TYPE2 280 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 281 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 282 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 283 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 284 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 285 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 286 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 287 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 288 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 289 #define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 290 #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa 291 #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb 292 #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc 293 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd 294 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe 295 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf 296 #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 297 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 298 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 299 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 300 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 301 #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 302 #define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE__SHIFT 0x16 303 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 304 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 305 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 306 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 307 #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b 308 #define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL__SHIFT 0x1c 309 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 310 #define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e 311 #define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 312 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L 313 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L 314 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L 315 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L 316 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L 317 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L 318 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L 319 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L 320 #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L 321 #define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L 322 #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L 323 #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L 324 #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L 325 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L 326 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L 327 #define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L 328 #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L 329 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L 330 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L 331 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L 332 #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L 333 #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L 334 #define SDMA1_PUB_REG_TYPE2__SDMA1_UNBREAKABLE_MASK 0x00400000L 335 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L 336 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L 337 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L 338 #define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 339 #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L 340 #define SDMA1_PUB_REG_TYPE2__SDMA1_MMHUB_TRUSTLVL_MASK 0x10000000L 341 #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 342 #define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L 343 #define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 344 //SDMA1_PUB_REG_TYPE3 345 #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 346 #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 347 #define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 348 #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L 349 #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 350 #define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 351 //SDMA1_MMHUB_CNTL 352 #define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 353 #define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 354 //SDMA1_CONTEXT_GROUP_BOUNDARY 355 #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 356 #define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 357 //SDMA1_POWER_CNTL 358 #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 359 #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 360 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 361 #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 362 #define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 363 #define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 364 #define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 365 #define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 366 #define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 367 #define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 368 //SDMA1_CLK_CTRL 369 #define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 370 #define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 371 #define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc 372 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 373 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 374 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 375 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 376 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 377 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 378 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 379 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 380 #define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 381 #define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 382 #define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L 383 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 384 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 385 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 386 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 387 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 388 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 389 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 390 #define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 391 //SDMA1_CNTL 392 #define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 393 #define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 394 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 395 #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 396 #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 397 #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 398 #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 399 #define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 400 #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 401 #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 402 #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 403 #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L 404 #define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 405 #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 406 #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 407 #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 408 #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 409 #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 410 #define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 411 #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 412 #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 413 #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 414 //SDMA1_CHICKEN_BITS 415 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 416 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 417 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 418 #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 419 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 420 #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 421 #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 422 #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 423 #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 424 #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 425 #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 426 #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 427 #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 428 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 429 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 430 #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 431 #define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 432 #define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 433 #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 434 #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 435 #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 436 #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 437 #define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 438 #define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 439 #define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 440 #define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 441 //SDMA1_GB_ADDR_CONFIG 442 #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 443 #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 444 #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 445 #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 446 #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 447 #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 448 #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 449 #define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 450 #define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 451 #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 452 //SDMA1_GB_ADDR_CONFIG_READ 453 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 454 #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 455 #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 456 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 457 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 458 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 459 #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 460 #define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 461 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 462 #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 463 //SDMA1_RB_RPTR_FETCH_HI 464 #define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 465 #define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 466 //SDMA1_SEM_WAIT_FAIL_TIMER_CNTL 467 #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 468 #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 469 //SDMA1_RB_RPTR_FETCH 470 #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 471 #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 472 //SDMA1_IB_OFFSET_FETCH 473 #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 474 #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 475 //SDMA1_PROGRAM 476 #define SDMA1_PROGRAM__STREAM__SHIFT 0x0 477 #define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL 478 //SDMA1_STATUS_REG 479 #define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 480 #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 481 #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 482 #define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 483 #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 484 #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 485 #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 486 #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 487 #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 488 #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 489 #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa 490 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 491 #define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc 492 #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 493 #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe 494 #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 495 #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 496 #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 497 #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 498 #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 499 #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 500 #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 501 #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 502 #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 503 #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a 504 #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 505 #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 506 #define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e 507 #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 508 #define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L 509 #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L 510 #define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L 511 #define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L 512 #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 513 #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 514 #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 515 #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 516 #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 517 #define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L 518 #define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L 519 #define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 520 #define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L 521 #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 522 #define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 523 #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 524 #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 525 #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 526 #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 527 #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 528 #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 529 #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 530 #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 531 #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 532 #define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L 533 #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 534 #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 535 #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L 536 #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 537 //SDMA1_STATUS1_REG 538 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 539 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 540 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 541 #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 542 #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 543 #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 544 #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 545 #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 546 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 547 #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 548 #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 549 #define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf 550 #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 551 #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 552 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 553 #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 554 #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 555 #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 556 #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 557 #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 558 #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 559 #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 560 #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 561 #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 562 #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 563 #define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L 564 #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 565 #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 566 //SDMA1_RD_BURST_CNTL 567 #define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 568 #define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 569 //SDMA1_HBM_PAGE_CONFIG 570 #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 571 #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L 572 //SDMA1_UCODE_CHECKSUM 573 #define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 574 #define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 575 //SDMA1_F32_CNTL 576 #define SDMA1_F32_CNTL__HALT__SHIFT 0x0 577 #define SDMA1_F32_CNTL__STEP__SHIFT 0x1 578 #define SDMA1_F32_CNTL__HALT_MASK 0x00000001L 579 #define SDMA1_F32_CNTL__STEP_MASK 0x00000002L 580 //SDMA1_FREEZE 581 #define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 582 #define SDMA1_FREEZE__FREEZE__SHIFT 0x4 583 #define SDMA1_FREEZE__FROZEN__SHIFT 0x5 584 #define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 585 #define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L 586 #define SDMA1_FREEZE__FREEZE_MASK 0x00000010L 587 #define SDMA1_FREEZE__FROZEN_MASK 0x00000020L 588 #define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L 589 //SDMA1_PHASE0_QUANTUM 590 #define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 591 #define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 592 #define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 593 #define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 594 #define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 595 #define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 596 //SDMA1_PHASE1_QUANTUM 597 #define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 598 #define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 599 #define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 600 #define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 601 #define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 602 #define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 603 //SDMA1_EDC_CONFIG 604 #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 605 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 606 #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 607 #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 608 //SDMA1_BA_THRESHOLD 609 #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 610 #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 611 #define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 612 #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 613 //SDMA1_ID 614 #define SDMA1_ID__DEVICE_ID__SHIFT 0x0 615 #define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL 616 //SDMA1_VERSION 617 #define SDMA1_VERSION__MINVER__SHIFT 0x0 618 #define SDMA1_VERSION__MAJVER__SHIFT 0x8 619 #define SDMA1_VERSION__REV__SHIFT 0x10 620 #define SDMA1_VERSION__MINVER_MASK 0x0000007FL 621 #define SDMA1_VERSION__MAJVER_MASK 0x00007F00L 622 #define SDMA1_VERSION__REV_MASK 0x003F0000L 623 //SDMA1_EDC_COUNTER 624 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 625 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 626 #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 627 #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 628 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 629 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 630 #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 631 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 632 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 633 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 634 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 635 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 636 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 637 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 638 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 639 #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf 640 #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 641 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L 642 #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L 643 #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 644 #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 645 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 646 #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 647 #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 648 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 649 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 650 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 651 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 652 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 653 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 654 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 655 #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 656 #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L 657 #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L 658 //SDMA1_EDC_COUNTER_CLEAR 659 #define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 660 #define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 661 //SDMA1_STATUS2_REG 662 #define SDMA1_STATUS2_REG__ID__SHIFT 0x0 663 #define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 664 #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 665 #define SDMA1_STATUS2_REG__ID_MASK 0x00000003L 666 #define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 667 #define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 668 //SDMA1_ATOMIC_CNTL 669 #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 670 #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 671 #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 672 #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 673 //SDMA1_ATOMIC_PREOP_LO 674 #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 675 #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 676 //SDMA1_ATOMIC_PREOP_HI 677 #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 678 #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 679 //SDMA1_UTCL1_CNTL 680 #define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 681 #define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 682 #define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 683 #define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 684 #define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 685 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 686 #define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 687 #define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 688 #define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 689 #define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 690 #define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 691 #define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 692 //SDMA1_UTCL1_WATERMK 693 #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 694 #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 695 #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 696 #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a 697 #define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL 698 #define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L 699 #define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L 700 #define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L 701 //SDMA1_UTCL1_RD_STATUS 702 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 703 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 704 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 705 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 706 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 707 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 708 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 709 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 710 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 711 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 712 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 713 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 714 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 715 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 716 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 717 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 718 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 719 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 720 #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 721 #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 722 #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 723 #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 724 #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 725 #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 726 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 727 #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 728 #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 729 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 730 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 731 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 732 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 733 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 734 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 735 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 736 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 737 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 738 #define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 739 #define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 740 #define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 741 #define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 742 #define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 743 #define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 744 #define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 745 #define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 746 #define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 747 #define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 748 #define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 749 #define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 750 #define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 751 #define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 752 #define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 753 #define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 754 #define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 755 #define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 756 //SDMA1_UTCL1_WR_STATUS 757 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 758 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 759 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 760 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 761 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 762 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 763 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 764 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 765 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 766 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 767 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 768 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 769 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 770 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 771 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 772 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 773 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 774 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 775 #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 776 #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 777 #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 778 #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 779 #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 780 #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 781 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 782 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 783 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 784 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 785 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 786 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 787 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 788 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 789 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 790 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 791 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 792 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 793 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 794 #define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 795 #define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 796 #define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 797 #define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 798 #define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 799 #define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 800 #define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 801 #define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 802 #define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 803 #define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 804 #define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 805 #define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 806 #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 807 #define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 808 #define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 809 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 810 #define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 811 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 812 #define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 813 //SDMA1_UTCL1_INV0 814 #define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 815 #define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 816 #define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 817 #define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 818 #define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 819 #define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 820 #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 821 #define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 822 #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 823 #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 824 #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 825 #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 826 #define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 827 #define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 828 #define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 829 #define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 830 #define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 831 #define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 832 #define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 833 #define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 834 #define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 835 #define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 836 #define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 837 #define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 838 #define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 839 #define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 840 #define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 841 #define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 842 //SDMA1_UTCL1_INV1 843 #define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 844 #define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 845 //SDMA1_UTCL1_INV2 846 #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 847 #define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 848 //SDMA1_UTCL1_RD_XNACK0 849 #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 850 #define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 851 //SDMA1_UTCL1_RD_XNACK1 852 #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 853 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 854 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 855 #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 856 #define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 857 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 858 #define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 859 #define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 860 //SDMA1_UTCL1_WR_XNACK0 861 #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 862 #define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 863 //SDMA1_UTCL1_WR_XNACK1 864 #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 865 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 866 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 867 #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 868 #define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 869 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 870 #define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 871 #define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 872 //SDMA1_UTCL1_TIMEOUT 873 #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 874 #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 875 #define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 876 #define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 877 //SDMA1_UTCL1_PAGE 878 #define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 879 #define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 880 #define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 881 #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 882 #define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 883 #define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 884 #define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 885 #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 886 //SDMA1_POWER_CNTL_IDLE 887 #define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 888 #define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 889 #define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 890 #define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 891 #define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 892 #define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 893 //SDMA1_RELAX_ORDERING_LUT 894 #define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 895 #define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 896 #define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 897 #define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 898 #define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 899 #define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 900 #define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 901 #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 902 #define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 903 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 904 #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 905 #define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 906 #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 907 #define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 908 #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 909 #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 910 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 911 #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 912 #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 913 #define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 914 #define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 915 #define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 916 #define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 917 #define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 918 #define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 919 #define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 920 #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 921 #define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 922 #define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 923 #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 924 #define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 925 #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 926 #define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 927 #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 928 #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 929 #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 930 #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 931 #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 932 //SDMA1_CHICKEN_BITS_2 933 #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 934 #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 935 //SDMA1_STATUS3_REG 936 #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 937 #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 938 #define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 939 #define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 940 #define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 941 #define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 942 //SDMA1_PHYSICAL_ADDR_LO 943 #define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 944 #define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 945 #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 946 #define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 947 #define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 948 #define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 949 #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 950 #define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 951 //SDMA1_PHYSICAL_ADDR_HI 952 #define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 953 #define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 954 //SDMA1_PHASE2_QUANTUM 955 #define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 956 #define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 957 #define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e 958 #define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL 959 #define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L 960 #define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L 961 //SDMA1_ERROR_LOG 962 #define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 963 #define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 964 #define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 965 #define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L 966 //SDMA1_PUB_DUMMY_REG0 967 #define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 968 #define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 969 //SDMA1_PUB_DUMMY_REG1 970 #define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 971 #define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 972 //SDMA1_PUB_DUMMY_REG2 973 #define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 974 #define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 975 //SDMA1_PUB_DUMMY_REG3 976 #define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 977 #define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 978 //SDMA1_F32_COUNTER 979 #define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 980 #define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 981 //SDMA1_UNBREAKABLE 982 #define SDMA1_UNBREAKABLE__VALUE__SHIFT 0x0 983 #define SDMA1_UNBREAKABLE__VALUE_MASK 0x00000001L 984 //SDMA1_PERFMON_CNTL 985 #define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 986 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 987 #define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 988 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 989 #define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 990 #define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 991 #define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 992 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 993 #define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 994 #define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 995 #define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 996 #define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 997 //SDMA1_PERFCOUNTER0_RESULT 998 #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 999 #define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1000 //SDMA1_PERFCOUNTER1_RESULT 1001 #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1002 #define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1003 //SDMA1_PERFCOUNTER_TAG_DELAY_RANGE 1004 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1005 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1006 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1007 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1008 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1009 #define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1010 //SDMA1_CRD_CNTL 1011 #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1012 #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1013 #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1014 #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1015 //SDMA1_MMHUB_TRUSTLVL 1016 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 1017 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 1018 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 1019 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 1020 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc 1021 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf 1022 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 1023 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 1024 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L 1025 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L 1026 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L 1027 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L 1028 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L 1029 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L 1030 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L 1031 #define SDMA1_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L 1032 //SDMA1_GPU_IOV_VIOLATION_LOG 1033 #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1034 #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1035 #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1036 #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1037 #define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1038 #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1039 #define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1040 #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1041 #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1042 #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1043 #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1044 #define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1045 #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1046 #define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1047 //SDMA1_ULV_CNTL 1048 #define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1049 #define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1050 #define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1051 #define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1052 #define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1053 #define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1054 #define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1055 #define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1056 //SDMA1_EA_DBIT_ADDR_DATA 1057 #define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1058 #define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1059 //SDMA1_EA_DBIT_ADDR_INDEX 1060 #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1061 #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1062 //SDMA1_GFX_RB_CNTL 1063 #define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1064 #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1065 #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1066 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1067 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1068 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1069 #define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1070 #define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1071 #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1072 #define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1073 #define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1074 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1075 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1076 #define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1077 #define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1078 #define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1079 //SDMA1_GFX_RB_BASE 1080 #define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 1081 #define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1082 //SDMA1_GFX_RB_BASE_HI 1083 #define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1084 #define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1085 //SDMA1_GFX_RB_RPTR 1086 #define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1087 #define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1088 //SDMA1_GFX_RB_RPTR_HI 1089 #define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1090 #define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1091 //SDMA1_GFX_RB_WPTR 1092 #define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1093 #define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1094 //SDMA1_GFX_RB_WPTR_HI 1095 #define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1096 #define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1097 //SDMA1_GFX_RB_WPTR_POLL_CNTL 1098 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1099 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1100 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1101 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1102 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1103 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1104 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1105 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1106 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1107 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1108 //SDMA1_GFX_RB_RPTR_ADDR_HI 1109 #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1110 #define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1111 //SDMA1_GFX_RB_RPTR_ADDR_LO 1112 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1113 #define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1114 //SDMA1_GFX_IB_CNTL 1115 #define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1116 #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1117 #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1118 #define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1119 #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1120 #define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1121 #define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1122 #define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1123 //SDMA1_GFX_IB_RPTR 1124 #define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1125 #define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1126 //SDMA1_GFX_IB_OFFSET 1127 #define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1128 #define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1129 //SDMA1_GFX_IB_BASE_LO 1130 #define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1131 #define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1132 //SDMA1_GFX_IB_BASE_HI 1133 #define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1134 #define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1135 //SDMA1_GFX_IB_SIZE 1136 #define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 1137 #define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1138 //SDMA1_GFX_SKIP_CNTL 1139 #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1140 #define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1141 //SDMA1_GFX_CONTEXT_STATUS 1142 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1143 #define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1144 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1145 #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1146 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1147 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1148 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1149 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1150 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1151 #define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1152 #define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1153 #define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1154 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1155 #define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1156 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1157 #define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1158 //SDMA1_GFX_DOORBELL 1159 #define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1160 #define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1161 #define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1162 #define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1163 //SDMA1_GFX_CONTEXT_CNTL 1164 #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1165 #define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1166 //SDMA1_GFX_STATUS 1167 #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1168 #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1169 #define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1170 #define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1171 //SDMA1_GFX_DOORBELL_LOG 1172 #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1173 #define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1174 #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1175 #define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1176 //SDMA1_GFX_WATERMARK 1177 #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1178 #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1179 #define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1180 #define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1181 //SDMA1_GFX_DOORBELL_OFFSET 1182 #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1183 #define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1184 //SDMA1_GFX_CSA_ADDR_LO 1185 #define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1186 #define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1187 //SDMA1_GFX_CSA_ADDR_HI 1188 #define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1189 #define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1190 //SDMA1_GFX_IB_SUB_REMAIN 1191 #define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1192 #define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1193 //SDMA1_GFX_PREEMPT 1194 #define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1195 #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1196 //SDMA1_GFX_DUMMY_REG 1197 #define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1198 #define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1199 //SDMA1_GFX_RB_WPTR_POLL_ADDR_HI 1200 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1201 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1202 //SDMA1_GFX_RB_WPTR_POLL_ADDR_LO 1203 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1204 #define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1205 //SDMA1_GFX_RB_AQL_CNTL 1206 #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1207 #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1208 #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1209 #define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1210 #define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1211 #define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1212 //SDMA1_GFX_MINOR_PTR_UPDATE 1213 #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1214 #define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1215 //SDMA1_GFX_MIDCMD_DATA0 1216 #define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1217 #define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1218 //SDMA1_GFX_MIDCMD_DATA1 1219 #define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1220 #define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1221 //SDMA1_GFX_MIDCMD_DATA2 1222 #define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1223 #define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1224 //SDMA1_GFX_MIDCMD_DATA3 1225 #define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1226 #define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1227 //SDMA1_GFX_MIDCMD_DATA4 1228 #define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1229 #define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1230 //SDMA1_GFX_MIDCMD_DATA5 1231 #define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1232 #define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1233 //SDMA1_GFX_MIDCMD_DATA6 1234 #define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1235 #define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1236 //SDMA1_GFX_MIDCMD_DATA7 1237 #define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1238 #define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1239 //SDMA1_GFX_MIDCMD_DATA8 1240 #define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1241 #define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1242 //SDMA1_GFX_MIDCMD_CNTL 1243 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1244 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1245 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1246 #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1247 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1248 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1249 #define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1250 #define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1251 //SDMA1_PAGE_RB_CNTL 1252 #define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 1253 #define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 1254 #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1255 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1256 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1257 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1258 #define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 1259 #define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 1260 #define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1261 #define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1262 #define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1263 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1264 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1265 #define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1266 #define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L 1267 #define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L 1268 //SDMA1_PAGE_RB_BASE 1269 #define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 1270 #define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1271 //SDMA1_PAGE_RB_BASE_HI 1272 #define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 1273 #define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1274 //SDMA1_PAGE_RB_RPTR 1275 #define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 1276 #define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1277 //SDMA1_PAGE_RB_RPTR_HI 1278 #define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 1279 #define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1280 //SDMA1_PAGE_RB_WPTR 1281 #define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 1282 #define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1283 //SDMA1_PAGE_RB_WPTR_HI 1284 #define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 1285 #define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1286 //SDMA1_PAGE_RB_WPTR_POLL_CNTL 1287 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1288 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1289 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1290 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1291 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1292 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1293 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1294 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1295 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1296 #define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1297 //SDMA1_PAGE_RB_RPTR_ADDR_HI 1298 #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1299 #define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1300 //SDMA1_PAGE_RB_RPTR_ADDR_LO 1301 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1302 #define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1303 //SDMA1_PAGE_IB_CNTL 1304 #define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 1305 #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1306 #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1307 #define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 1308 #define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1309 #define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1310 #define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1311 #define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1312 //SDMA1_PAGE_IB_RPTR 1313 #define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 1314 #define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1315 //SDMA1_PAGE_IB_OFFSET 1316 #define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 1317 #define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1318 //SDMA1_PAGE_IB_BASE_LO 1319 #define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 1320 #define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1321 //SDMA1_PAGE_IB_BASE_HI 1322 #define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 1323 #define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1324 //SDMA1_PAGE_IB_SIZE 1325 #define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 1326 #define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL 1327 //SDMA1_PAGE_SKIP_CNTL 1328 #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1329 #define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1330 //SDMA1_PAGE_CONTEXT_STATUS 1331 #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1332 #define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 1333 #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1334 #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1335 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1336 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1337 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1338 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1339 #define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1340 #define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1341 #define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1342 #define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1343 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1344 #define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1345 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1346 #define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1347 //SDMA1_PAGE_DOORBELL 1348 #define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c 1349 #define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e 1350 #define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L 1351 #define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L 1352 //SDMA1_PAGE_STATUS 1353 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1354 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1355 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1356 #define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1357 //SDMA1_PAGE_DOORBELL_LOG 1358 #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1359 #define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 1360 #define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1361 #define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1362 //SDMA1_PAGE_WATERMARK 1363 #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1364 #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1365 #define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1366 #define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1367 //SDMA1_PAGE_DOORBELL_OFFSET 1368 #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1369 #define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1370 //SDMA1_PAGE_CSA_ADDR_LO 1371 #define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 1372 #define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1373 //SDMA1_PAGE_CSA_ADDR_HI 1374 #define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 1375 #define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1376 //SDMA1_PAGE_IB_SUB_REMAIN 1377 #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1378 #define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1379 //SDMA1_PAGE_PREEMPT 1380 #define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 1381 #define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1382 //SDMA1_PAGE_DUMMY_REG 1383 #define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 1384 #define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1385 //SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 1386 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1387 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1388 //SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 1389 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1390 #define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1391 //SDMA1_PAGE_RB_AQL_CNTL 1392 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1393 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1394 #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1395 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1396 #define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1397 #define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1398 //SDMA1_PAGE_MINOR_PTR_UPDATE 1399 #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1400 #define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1401 //SDMA1_PAGE_MIDCMD_DATA0 1402 #define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 1403 #define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1404 //SDMA1_PAGE_MIDCMD_DATA1 1405 #define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 1406 #define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1407 //SDMA1_PAGE_MIDCMD_DATA2 1408 #define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 1409 #define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1410 //SDMA1_PAGE_MIDCMD_DATA3 1411 #define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 1412 #define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1413 //SDMA1_PAGE_MIDCMD_DATA4 1414 #define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 1415 #define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1416 //SDMA1_PAGE_MIDCMD_DATA5 1417 #define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 1418 #define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1419 //SDMA1_PAGE_MIDCMD_DATA6 1420 #define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 1421 #define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1422 //SDMA1_PAGE_MIDCMD_DATA7 1423 #define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 1424 #define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1425 //SDMA1_PAGE_MIDCMD_DATA8 1426 #define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 1427 #define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1428 //SDMA1_PAGE_MIDCMD_CNTL 1429 #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1430 #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1431 #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1432 #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1433 #define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1434 #define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1435 #define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1436 #define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1437 //SDMA1_RLC0_RB_CNTL 1438 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1439 #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1440 #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1441 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1442 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1443 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1444 #define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1445 #define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1446 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1447 #define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1448 #define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1449 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1450 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1451 #define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1452 #define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1453 #define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1454 //SDMA1_RLC0_RB_BASE 1455 #define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 1456 #define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1457 //SDMA1_RLC0_RB_BASE_HI 1458 #define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1459 #define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1460 //SDMA1_RLC0_RB_RPTR 1461 #define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1462 #define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1463 //SDMA1_RLC0_RB_RPTR_HI 1464 #define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1465 #define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1466 //SDMA1_RLC0_RB_WPTR 1467 #define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1468 #define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1469 //SDMA1_RLC0_RB_WPTR_HI 1470 #define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1471 #define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1472 //SDMA1_RLC0_RB_WPTR_POLL_CNTL 1473 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1474 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1475 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1476 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1477 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1478 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1479 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1480 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1481 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1482 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1483 //SDMA1_RLC0_RB_RPTR_ADDR_HI 1484 #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1485 #define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1486 //SDMA1_RLC0_RB_RPTR_ADDR_LO 1487 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1488 #define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1489 //SDMA1_RLC0_IB_CNTL 1490 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1491 #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1492 #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1493 #define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1494 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1495 #define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1496 #define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1497 #define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1498 //SDMA1_RLC0_IB_RPTR 1499 #define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1500 #define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1501 //SDMA1_RLC0_IB_OFFSET 1502 #define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1503 #define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1504 //SDMA1_RLC0_IB_BASE_LO 1505 #define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1506 #define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1507 //SDMA1_RLC0_IB_BASE_HI 1508 #define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1509 #define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1510 //SDMA1_RLC0_IB_SIZE 1511 #define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1512 #define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1513 //SDMA1_RLC0_SKIP_CNTL 1514 #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1515 #define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1516 //SDMA1_RLC0_CONTEXT_STATUS 1517 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1518 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1519 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1520 #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1521 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1522 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1523 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1524 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1525 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1526 #define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1527 #define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1528 #define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1529 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1530 #define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1531 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1532 #define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1533 //SDMA1_RLC0_DOORBELL 1534 #define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1535 #define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1536 #define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1537 #define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1538 //SDMA1_RLC0_STATUS 1539 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1540 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1541 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1542 #define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1543 //SDMA1_RLC0_DOORBELL_LOG 1544 #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1545 #define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1546 #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1547 #define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1548 //SDMA1_RLC0_WATERMARK 1549 #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1550 #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1551 #define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1552 #define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1553 //SDMA1_RLC0_DOORBELL_OFFSET 1554 #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1555 #define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1556 //SDMA1_RLC0_CSA_ADDR_LO 1557 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1558 #define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1559 //SDMA1_RLC0_CSA_ADDR_HI 1560 #define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1561 #define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1562 //SDMA1_RLC0_IB_SUB_REMAIN 1563 #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1564 #define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1565 //SDMA1_RLC0_PREEMPT 1566 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1567 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1568 //SDMA1_RLC0_DUMMY_REG 1569 #define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1570 #define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1571 //SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 1572 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1573 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1574 //SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 1575 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1576 #define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1577 //SDMA1_RLC0_RB_AQL_CNTL 1578 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1579 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1580 #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1581 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1582 #define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1583 #define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1584 //SDMA1_RLC0_MINOR_PTR_UPDATE 1585 #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1586 #define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1587 //SDMA1_RLC0_MIDCMD_DATA0 1588 #define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1589 #define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1590 //SDMA1_RLC0_MIDCMD_DATA1 1591 #define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1592 #define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1593 //SDMA1_RLC0_MIDCMD_DATA2 1594 #define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1595 #define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1596 //SDMA1_RLC0_MIDCMD_DATA3 1597 #define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1598 #define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1599 //SDMA1_RLC0_MIDCMD_DATA4 1600 #define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1601 #define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1602 //SDMA1_RLC0_MIDCMD_DATA5 1603 #define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1604 #define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1605 //SDMA1_RLC0_MIDCMD_DATA6 1606 #define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1607 #define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1608 //SDMA1_RLC0_MIDCMD_DATA7 1609 #define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1610 #define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1611 //SDMA1_RLC0_MIDCMD_DATA8 1612 #define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1613 #define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1614 //SDMA1_RLC0_MIDCMD_CNTL 1615 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1616 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1617 #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1618 #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1619 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1620 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1621 #define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1622 #define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1623 //SDMA1_RLC1_RB_CNTL 1624 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1625 #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1626 #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1627 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1628 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1629 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1630 #define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1631 #define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1632 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1633 #define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1634 #define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1635 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1636 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1637 #define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1638 #define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1639 #define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1640 //SDMA1_RLC1_RB_BASE 1641 #define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 1642 #define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1643 //SDMA1_RLC1_RB_BASE_HI 1644 #define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1645 #define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1646 //SDMA1_RLC1_RB_RPTR 1647 #define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1648 #define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1649 //SDMA1_RLC1_RB_RPTR_HI 1650 #define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1651 #define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1652 //SDMA1_RLC1_RB_WPTR 1653 #define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1654 #define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1655 //SDMA1_RLC1_RB_WPTR_HI 1656 #define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1657 #define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1658 //SDMA1_RLC1_RB_WPTR_POLL_CNTL 1659 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1660 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1661 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1662 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1663 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1664 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1665 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1666 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1667 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1668 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1669 //SDMA1_RLC1_RB_RPTR_ADDR_HI 1670 #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1671 #define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1672 //SDMA1_RLC1_RB_RPTR_ADDR_LO 1673 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1674 #define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1675 //SDMA1_RLC1_IB_CNTL 1676 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1677 #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1678 #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1679 #define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1680 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1681 #define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1682 #define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1683 #define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1684 //SDMA1_RLC1_IB_RPTR 1685 #define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1686 #define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1687 //SDMA1_RLC1_IB_OFFSET 1688 #define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1689 #define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1690 //SDMA1_RLC1_IB_BASE_LO 1691 #define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1692 #define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1693 //SDMA1_RLC1_IB_BASE_HI 1694 #define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1695 #define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1696 //SDMA1_RLC1_IB_SIZE 1697 #define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1698 #define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1699 //SDMA1_RLC1_SKIP_CNTL 1700 #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1701 #define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1702 //SDMA1_RLC1_CONTEXT_STATUS 1703 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1704 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1705 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1706 #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1707 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1708 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1709 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1710 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1711 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1712 #define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1713 #define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1714 #define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1715 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1716 #define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1717 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1718 #define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1719 //SDMA1_RLC1_DOORBELL 1720 #define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1721 #define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1722 #define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1723 #define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1724 //SDMA1_RLC1_STATUS 1725 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1726 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1727 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1728 #define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1729 //SDMA1_RLC1_DOORBELL_LOG 1730 #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1731 #define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1732 #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1733 #define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1734 //SDMA1_RLC1_WATERMARK 1735 #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1736 #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1737 #define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1738 #define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1739 //SDMA1_RLC1_DOORBELL_OFFSET 1740 #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1741 #define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1742 //SDMA1_RLC1_CSA_ADDR_LO 1743 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1744 #define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1745 //SDMA1_RLC1_CSA_ADDR_HI 1746 #define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1747 #define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1748 //SDMA1_RLC1_IB_SUB_REMAIN 1749 #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1750 #define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1751 //SDMA1_RLC1_PREEMPT 1752 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1753 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1754 //SDMA1_RLC1_DUMMY_REG 1755 #define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1756 #define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1757 //SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 1758 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1759 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1760 //SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 1761 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1762 #define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1763 //SDMA1_RLC1_RB_AQL_CNTL 1764 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1765 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1766 #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1767 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1768 #define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1769 #define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1770 //SDMA1_RLC1_MINOR_PTR_UPDATE 1771 #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1772 #define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1773 //SDMA1_RLC1_MIDCMD_DATA0 1774 #define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1775 #define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1776 //SDMA1_RLC1_MIDCMD_DATA1 1777 #define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1778 #define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1779 //SDMA1_RLC1_MIDCMD_DATA2 1780 #define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1781 #define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1782 //SDMA1_RLC1_MIDCMD_DATA3 1783 #define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1784 #define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1785 //SDMA1_RLC1_MIDCMD_DATA4 1786 #define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1787 #define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1788 //SDMA1_RLC1_MIDCMD_DATA5 1789 #define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1790 #define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1791 //SDMA1_RLC1_MIDCMD_DATA6 1792 #define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1793 #define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1794 //SDMA1_RLC1_MIDCMD_DATA7 1795 #define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1796 #define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1797 //SDMA1_RLC1_MIDCMD_DATA8 1798 #define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1799 #define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1800 //SDMA1_RLC1_MIDCMD_CNTL 1801 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1802 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1803 #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1804 #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1805 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1806 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1807 #define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1808 #define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1809 1810 #endif 1811