| /linux-6.1.9/include/dt-bindings/clock/ |
| D | rk3036-cru.h | 24 #define SCLK_UART1 78 macro
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| D | exynos7-clk.h | 96 #define SCLK_UART1 4 macro
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| D | s5pv210.h | 196 #define SCLK_UART1 174 macro
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| D | rk3188-cru-common.h | 21 #define SCLK_UART1 65 macro
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| D | rk3128-cru.h | 26 #define SCLK_UART1 78 macro
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| D | rk3228-cru.h | 25 #define SCLK_UART1 78 macro
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| D | rv1108-cru.h | 23 #define SCLK_UART1 73 macro
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| D | rk3288-cru.h | 33 #define SCLK_UART1 78 macro
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| D | rk3308-cru.h | 22 #define SCLK_UART1 18 macro
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| D | rk3328-cru.h | 28 #define SCLK_UART1 39 macro
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| D | rk3368-cru.h | 31 #define SCLK_UART1 78 macro
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| D | px30-cru.h | 26 #define SCLK_UART1 24 macro
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| D | rockchip,rv1126-cru.h | 25 #define SCLK_UART1 11 macro
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| D | rk3399-cru.h | 39 #define SCLK_UART1 82 macro
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| D | rk3568-cru.h | 350 #define SCLK_UART1 287 macro
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| /linux-6.1.9/Documentation/devicetree/bindings/clock/ |
| D | rockchip,rk3568-cru.yaml | 16 (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module)
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| /linux-6.1.9/drivers/clk/rockchip/ |
| D | clk-rk3036.c | 154 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3128.c | 190 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3228.c | 204 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3188.c | 264 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3328.c | 257 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| D | clk-rv1108.c | 172 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| /linux-6.1.9/drivers/clk/samsung/ |
| D | clk-s5pv210.c | 598 GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13,
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| /linux-6.1.9/arch/arm/boot/dts/ |
| D | rk3xxx.dtsi | 121 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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| D | s5pv210.dtsi | 332 <&clocks SCLK_UART1>;
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