| /linux-6.1.9/include/dt-bindings/clock/ |
| D | samsung,s3c64xx-clock.h | 102 #define SCLK_SPI0 90 macro
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| D | exynos7-clk.h | 109 #define SCLK_SPI0 17 macro
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| D | s5pv210.h | 193 #define SCLK_SPI0 171 macro
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| D | rk3188-cru-common.h | 25 #define SCLK_SPI0 69 macro
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| D | rk3128-cru.h | 20 #define SCLK_SPI0 65 macro
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| D | rk3228-cru.h | 18 #define SCLK_SPI0 65 macro
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| D | rv1108-cru.h | 17 #define SCLK_SPI0 65 macro
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| D | rk3288-cru.h | 20 #define SCLK_SPI0 65 macro
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| D | rk3308-cru.h | 31 #define SCLK_SPI0 27 macro
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| D | rk3368-cru.h | 21 #define SCLK_SPI0 65 macro
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| D | px30-cru.h | 38 #define SCLK_SPI0 36 macro
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| D | rk3399-cru.h | 28 #define SCLK_SPI0 71 macro
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| /linux-6.1.9/Documentation/devicetree/bindings/spi/ |
| D | spi-rockchip.yaml | 106 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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| /linux-6.1.9/drivers/clk/samsung/ |
| D | clk-s3c64xx.c | 256 GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20),
357 ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi_busclk2"),
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| D | clk-s5pv210.c | 594 GATE(SCLK_SPI0, "sclk_spi0", "dout_spi0", CLK_SRC_MASK0, 16,
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| D | clk-exynos7.c | 784 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
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| /linux-6.1.9/drivers/clk/rockchip/ |
| D | clk-rk3128.c | 404 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0,
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| D | clk-rk3228.c | 474 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
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| D | clk-rk3188.c | 391 COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
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| D | clk-rk3368.c | 535 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
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| D | clk-rk3288.c | 516 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
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| D | clk-px30.c | 744 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
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| D | clk-rk3308.c | 403 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_dpll_vpll0_xin24m_p, 0,
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| /linux-6.1.9/arch/arm/boot/dts/ |
| D | rk3xxx.dtsi | 453 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
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| D | s5pv210.dtsi | 158 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
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