Searched refs:SCLK_I2S1 (Results 1 – 21 of 21) sorted by relevance
| /linux-6.1.9/include/dt-bindings/clock/ |
| D | s3c2443.h | 33 #define SCLK_I2S1 19 macro
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| D | exynos7-clk.h | 117 #define SCLK_I2S1 25 macro
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| D | rk3188-cru-common.h | 32 #define SCLK_I2S1 76 macro
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| D | rk3128-cru.h | 29 #define SCLK_I2S1 81 macro
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| D | rk3228-cru.h | 28 #define SCLK_I2S1 81 macro
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| D | rv1108-cru.h | 26 #define SCLK_I2S1 76 macro
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| D | rk3328-cru.h | 31 #define SCLK_I2S1 42 macro
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| D | px30-cru.h | 22 #define SCLK_I2S1 20 macro
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| /linux-6.1.9/Documentation/devicetree/bindings/sound/ |
| D | rockchip,rk3328-codec.yaml | 65 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
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| /linux-6.1.9/drivers/clk/samsung/ |
| D | clk-s3c2443.c | 294 GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0),
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| D | clk-exynos7.c | 794 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
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| /linux-6.1.9/drivers/clk/rockchip/ |
| D | clk-rk3128.c | 374 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
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| D | clk-rk3228.c | 434 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
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| D | clk-rk3188.c | 551 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3328.c | 387 GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
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| D | clk-rv1108.c | 521 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
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| D | clk-px30.c | 638 GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
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| /linux-6.1.9/arch/arm/boot/dts/ |
| D | rk3066a.dtsi | 176 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
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| D | rk322x.dtsi | 140 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
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| /linux-6.1.9/arch/arm64/boot/dts/rockchip/ |
| D | rk3328.dtsi | 227 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
755 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
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| D | px30.dtsi | 394 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
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