1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #ifndef __RTW_FW_H_
6 #define __RTW_FW_H_
7
8 #define H2C_PKT_SIZE 32
9 #define H2C_PKT_HDR_SIZE 8
10
11 /* FW bin information */
12 #define FW_HDR_SIZE 64
13 #define FW_HDR_CHKSUM_SIZE 8
14
15 #define FW_NLO_INFO_CHECK_SIZE 4
16
17 #define FIFO_PAGE_SIZE_SHIFT 12
18 #define FIFO_PAGE_SIZE 4096
19 #define FIFO_DUMP_ADDR 0x8000
20
21 #define DLFW_PAGE_SIZE_SHIFT_LEGACY 12
22 #define DLFW_PAGE_SIZE_LEGACY 0x1000
23 #define DLFW_BLK_SIZE_SHIFT_LEGACY 2
24 #define DLFW_BLK_SIZE_LEGACY 4
25 #define FW_START_ADDR_LEGACY 0x1000
26
27 #define BCN_LOSS_CNT 10
28 #define BCN_FILTER_NOTIFY_SIGNAL_CHANGE 0
29 #define BCN_FILTER_CONNECTION_LOSS 1
30 #define BCN_FILTER_CONNECTED 2
31 #define BCN_FILTER_NOTIFY_BEACON_LOSS 3
32
33 #define SCAN_NOTIFY_TIMEOUT msecs_to_jiffies(10)
34
35 #define RTW_CHANNEL_TIME 45
36 #define RTW_OFF_CHAN_TIME 100
37 #define RTW_PASS_CHAN_TIME 105
38 #define RTW_DFS_CHAN_TIME 20
39 #define RTW_CH_INFO_SIZE 4
40 #define RTW_EX_CH_INFO_SIZE 3
41 #define RTW_EX_CH_INFO_HDR_SIZE 2
42 #define RTW_SCAN_WIDTH 0
43 #define RTW_PRI_CH_IDX 1
44 #define RTW_OLD_PROBE_PG_CNT 2
45 #define RTW_PROBE_PG_CNT 4
46
47 enum rtw_c2h_cmd_id {
48 C2H_CCX_TX_RPT = 0x03,
49 C2H_BT_INFO = 0x09,
50 C2H_BT_MP_INFO = 0x0b,
51 C2H_BT_HID_INFO = 0x45,
52 C2H_RA_RPT = 0x0c,
53 C2H_HW_FEATURE_REPORT = 0x19,
54 C2H_WLAN_INFO = 0x27,
55 C2H_WLAN_RFON = 0x32,
56 C2H_BCN_FILTER_NOTIFY = 0x36,
57 C2H_ADAPTIVITY = 0x37,
58 C2H_SCAN_RESULT = 0x38,
59 C2H_HW_FEATURE_DUMP = 0xfd,
60 C2H_HALMAC = 0xff,
61 };
62
63 enum rtw_c2h_cmd_id_ext {
64 C2H_SCAN_STATUS_RPT = 0x3,
65 C2H_CCX_RPT = 0x0f,
66 C2H_CHAN_SWITCH = 0x22,
67 };
68
69 struct rtw_c2h_cmd {
70 u8 id;
71 u8 seq;
72 u8 payload[];
73 } __packed;
74
75 struct rtw_c2h_adaptivity {
76 u8 density;
77 u8 igi;
78 u8 l2h_th_init;
79 u8 l2h;
80 u8 h2l;
81 u8 option;
82 } __packed;
83
84 enum rtw_rsvd_packet_type {
85 RSVD_BEACON,
86 RSVD_DUMMY,
87 RSVD_PS_POLL,
88 RSVD_PROBE_RESP,
89 RSVD_NULL,
90 RSVD_QOS_NULL,
91 RSVD_LPS_PG_DPK,
92 RSVD_LPS_PG_INFO,
93 RSVD_PROBE_REQ,
94 RSVD_NLO_INFO,
95 RSVD_CH_INFO,
96 };
97
98 enum rtw_fw_rf_type {
99 FW_RF_1T2R = 0,
100 FW_RF_2T4R = 1,
101 FW_RF_2T2R = 2,
102 FW_RF_2T3R = 3,
103 FW_RF_1T1R = 4,
104 FW_RF_2T2R_GREEN = 5,
105 FW_RF_3T3R = 6,
106 FW_RF_3T4R = 7,
107 FW_RF_4T4R = 8,
108 FW_RF_MAX_TYPE = 0xF,
109 };
110
111 enum rtw_fw_feature {
112 FW_FEATURE_SIG = BIT(0),
113 FW_FEATURE_LPS_C2H = BIT(1),
114 FW_FEATURE_LCLK = BIT(2),
115 FW_FEATURE_PG = BIT(3),
116 FW_FEATURE_TX_WAKE = BIT(4),
117 FW_FEATURE_BCN_FILTER = BIT(5),
118 FW_FEATURE_NOTIFY_SCAN = BIT(6),
119 FW_FEATURE_ADAPTIVITY = BIT(7),
120 FW_FEATURE_SCAN_OFFLOAD = BIT(8),
121 FW_FEATURE_MAX = BIT(31),
122 };
123
124 enum rtw_fw_feature_ext {
125 FW_FEATURE_EXT_OLD_PAGE_NUM = BIT(0),
126 };
127
128 enum rtw_beacon_filter_offload_mode {
129 BCN_FILTER_OFFLOAD_MODE_0 = 0,
130 BCN_FILTER_OFFLOAD_MODE_1,
131 BCN_FILTER_OFFLOAD_MODE_2,
132 BCN_FILTER_OFFLOAD_MODE_3,
133
134 BCN_FILTER_OFFLOAD_MODE_DEFAULT = BCN_FILTER_OFFLOAD_MODE_0,
135 };
136
137 struct rtw_coex_info_req {
138 u8 seq;
139 u8 op_code;
140 u8 para1;
141 u8 para2;
142 u8 para3;
143 };
144
145 struct rtw_iqk_para {
146 u8 clear;
147 u8 segment_iqk;
148 };
149
150 struct rtw_lps_pg_dpk_hdr {
151 u16 dpk_path_ok;
152 u8 dpk_txagc[2];
153 u16 dpk_gs[2];
154 u32 coef[2][20];
155 u8 dpk_ch;
156 } __packed;
157
158 struct rtw_lps_pg_info_hdr {
159 u8 macid;
160 u8 mbssid;
161 u8 pattern_count;
162 u8 mu_tab_group_id;
163 u8 sec_cam_count;
164 u8 tx_bu_page_count;
165 u16 rsvd;
166 u8 sec_cam[MAX_PG_CAM_BACKUP_NUM];
167 } __packed;
168
169 struct rtw_rsvd_page {
170 /* associated with each vif */
171 struct list_head vif_list;
172 struct rtw_vif *rtwvif;
173
174 /* associated when build rsvd page */
175 struct list_head build_list;
176
177 struct sk_buff *skb;
178 enum rtw_rsvd_packet_type type;
179 u8 page;
180 u16 tim_offset;
181 bool add_txdesc;
182 struct cfg80211_ssid *ssid;
183 u16 probe_req_size;
184 };
185
186 enum rtw_keep_alive_pkt_type {
187 KEEP_ALIVE_NULL_PKT = 0,
188 KEEP_ALIVE_ARP_RSP = 1,
189 };
190
191 struct rtw_nlo_info_hdr {
192 u8 nlo_count;
193 u8 hidden_ap_count;
194 u8 rsvd1[2];
195 u8 pattern_check[FW_NLO_INFO_CHECK_SIZE];
196 u8 rsvd2[8];
197 u8 ssid_len[16];
198 u8 chiper[16];
199 u8 rsvd3[16];
200 u8 location[8];
201 } __packed;
202
203 enum rtw_packet_type {
204 RTW_PACKET_PROBE_REQ = 0x00,
205
206 RTW_PACKET_UNDEFINE = 0x7FFFFFFF,
207 };
208
209 struct rtw_fw_wow_keep_alive_para {
210 bool adopt;
211 u8 pkt_type;
212 u8 period; /* unit: sec */
213 };
214
215 struct rtw_fw_wow_disconnect_para {
216 bool adopt;
217 u8 period; /* unit: sec */
218 u8 retry_count;
219 };
220
221 enum rtw_channel_type {
222 RTW_CHANNEL_PASSIVE,
223 RTW_CHANNEL_ACTIVE,
224 RTW_CHANNEL_RADAR,
225 };
226
227 enum rtw_scan_extra_id {
228 RTW_SCAN_EXTRA_ID_DFS,
229 };
230
231 enum rtw_scan_extra_info {
232 RTW_SCAN_EXTRA_ACTION_SCAN,
233 };
234
235 enum rtw_scan_report_code {
236 RTW_SCAN_REPORT_SUCCESS = 0x00,
237 RTW_SCAN_REPORT_ERR_PHYDM = 0x01,
238 RTW_SCAN_REPORT_ERR_ID = 0x02,
239 RTW_SCAN_REPORT_ERR_TX = 0x03,
240 RTW_SCAN_REPORT_CANCELED = 0x10,
241 RTW_SCAN_REPORT_CANCELED_EXT = 0x11,
242 RTW_SCAN_REPORT_FW_DISABLED = 0xF0,
243 };
244
245 enum rtw_scan_notify_id {
246 RTW_SCAN_NOTIFY_ID_PRESWITCH = 0x00,
247 RTW_SCAN_NOTIFY_ID_POSTSWITCH = 0x01,
248 RTW_SCAN_NOTIFY_ID_PROBE_PRETX = 0x02,
249 RTW_SCAN_NOTIFY_ID_PROBE_ISSUETX = 0x03,
250 RTW_SCAN_NOTIFY_ID_NULL0_PRETX = 0x04,
251 RTW_SCAN_NOTIFY_ID_NULL0_ISSUETX = 0x05,
252 RTW_SCAN_NOTIFY_ID_NULL0_POSTTX = 0x06,
253 RTW_SCAN_NOTIFY_ID_NULL1_PRETX = 0x07,
254 RTW_SCAN_NOTIFY_ID_NULL1_ISSUETX = 0x08,
255 RTW_SCAN_NOTIFY_ID_NULL1_POSTTX = 0x09,
256 RTW_SCAN_NOTIFY_ID_DWELLEXT = 0x0A,
257 };
258
259 enum rtw_scan_notify_status {
260 RTW_SCAN_NOTIFY_STATUS_SUCCESS = 0x00,
261 RTW_SCAN_NOTIFY_STATUS_FAILURE = 0x01,
262 RTW_SCAN_NOTIFY_STATUS_RESOURCE = 0x02,
263 RTW_SCAN_NOTIFY_STATUS_TIMEOUT = 0x03,
264 };
265
266 struct rtw_ch_switch_option {
267 u8 periodic_option;
268 u32 tsf_high;
269 u32 tsf_low;
270 u8 dest_ch_en;
271 u8 absolute_time_en;
272 u8 dest_ch;
273 u8 normal_period;
274 u8 normal_period_sel;
275 u8 normal_cycle;
276 u8 slow_period;
277 u8 slow_period_sel;
278 u8 nlo_en;
279 bool switch_en;
280 bool back_op_en;
281 };
282
283 struct rtw_fw_hdr {
284 __le16 signature;
285 u8 category;
286 u8 function;
287 __le16 version; /* 0x04 */
288 u8 subversion;
289 u8 subindex;
290 __le32 rsvd; /* 0x08 */
291 __le32 feature; /* 0x0C */
292 u8 month; /* 0x10 */
293 u8 day;
294 u8 hour;
295 u8 min;
296 __le16 year; /* 0x14 */
297 __le16 rsvd3;
298 u8 mem_usage; /* 0x18 */
299 u8 rsvd4[3];
300 __le16 h2c_fmt_ver; /* 0x1C */
301 __le16 rsvd5;
302 __le32 dmem_addr; /* 0x20 */
303 __le32 dmem_size;
304 __le32 rsvd6;
305 __le32 rsvd7;
306 __le32 imem_size; /* 0x30 */
307 __le32 emem_size;
308 __le32 emem_addr;
309 __le32 imem_addr;
310 } __packed;
311
312 struct rtw_fw_hdr_legacy {
313 __le16 signature;
314 u8 category;
315 u8 function;
316 __le16 version; /* 0x04 */
317 u8 subversion1;
318 u8 subversion2;
319 u8 month; /* 0x08 */
320 u8 day;
321 u8 hour;
322 u8 minute;
323 __le16 size;
324 __le16 rsvd2;
325 __le32 idx; /* 0x10 */
326 __le32 rsvd3;
327 __le32 rsvd4; /* 0x18 */
328 __le32 rsvd5;
329 } __packed;
330
331 #define RTW_FW_VER_CODE(ver, sub_ver, idx) \
332 (((ver) << 16) | ((sub_ver) << 8) | (idx))
333 #define RTW_FW_SUIT_VER_CODE(s) \
334 RTW_FW_VER_CODE((s).version, (s).sub_version, (s).sub_index)
335
336 /* C2H */
337 #define GET_CCX_REPORT_SEQNUM_V0(c2h_payload) (c2h_payload[6] & 0xfc)
338 #define GET_CCX_REPORT_STATUS_V0(c2h_payload) (c2h_payload[0] & 0xc0)
339 #define GET_CCX_REPORT_SEQNUM_V1(c2h_payload) (c2h_payload[8] & 0xfc)
340 #define GET_CCX_REPORT_STATUS_V1(c2h_payload) (c2h_payload[9] & 0xc0)
341
342 #define GET_SCAN_REPORT_RETURN_CODE(c2h_payload) (c2h_payload[2] & 0xff)
343
344 #define GET_CHAN_SWITCH_CENTRAL_CH(c2h_payload) (c2h_payload[2])
345 #define GET_CHAN_SWITCH_ID(c2h_payload) (c2h_payload[3])
346 #define GET_CHAN_SWITCH_STATUS(c2h_payload) (c2h_payload[4])
347 #define GET_RA_REPORT_RATE(c2h_payload) (c2h_payload[0] & 0x7f)
348 #define GET_RA_REPORT_SGI(c2h_payload) ((c2h_payload[0] & 0x80) >> 7)
349 #define GET_RA_REPORT_BW(c2h_payload) (c2h_payload[6])
350 #define GET_RA_REPORT_MACID(c2h_payload) (c2h_payload[1])
351
352 #define GET_BCN_FILTER_NOTIFY_TYPE(c2h_payload) (c2h_payload[1] & 0xf)
353 #define GET_BCN_FILTER_NOTIFY_EVENT(c2h_payload) (c2h_payload[1] & 0x10)
354 #define GET_BCN_FILTER_NOTIFY_RSSI(c2h_payload) (c2h_payload[2] - 100)
355
356 /* PKT H2C */
357 #define H2C_PKT_CMD_ID 0xFF
358 #define H2C_PKT_CATEGORY 0x01
359
360 #define H2C_PKT_GENERAL_INFO 0x0D
361 #define H2C_PKT_PHYDM_INFO 0x11
362 #define H2C_PKT_IQK 0x0E
363
364 #define H2C_PKT_CH_SWITCH 0x02
365 #define H2C_PKT_UPDATE_PKT 0x0C
366 #define H2C_PKT_SCAN_OFFLOAD 0x19
367
368 #define H2C_PKT_CH_SWITCH_LEN 0x20
369 #define H2C_PKT_UPDATE_PKT_LEN 0x4
370
371 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \
372 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
373 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \
374 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
375 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \
376 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
377 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \
378 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
379
rtw_h2c_pkt_set_header(u8 * h2c_pkt,u8 sub_id)380 static inline void rtw_h2c_pkt_set_header(u8 *h2c_pkt, u8 sub_id)
381 {
382 SET_PKT_H2C_CATEGORY(h2c_pkt, H2C_PKT_CATEGORY);
383 SET_PKT_H2C_CMD_ID(h2c_pkt, H2C_PKT_CMD_ID);
384 SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, sub_id);
385 }
386
387 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \
388 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
389 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \
390 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
391
392 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \
393 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(7, 0))
394 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \
395 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
396 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \
397 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
398 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \
399 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
400 #define PHYDM_INFO_SET_TX_ANT_STATUS(h2c_pkt, value) \
401 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
402 #define IQK_SET_CLEAR(h2c_pkt, value) \
403 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
404 #define IQK_SET_SEGMENT_IQK(h2c_pkt, value) \
405 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
406
407 #define CHSW_INFO_SET_CH(pkt, value) \
408 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(7, 0))
409 #define CHSW_INFO_SET_PRI_CH_IDX(pkt, value) \
410 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(11, 8))
411 #define CHSW_INFO_SET_BW(pkt, value) \
412 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(15, 12))
413 #define CHSW_INFO_SET_TIMEOUT(pkt, value) \
414 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(23, 16))
415 #define CHSW_INFO_SET_ACTION_ID(pkt, value) \
416 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, GENMASK(30, 24))
417 #define CHSW_INFO_SET_EXTRA_INFO(pkt, value) \
418 le32p_replace_bits((__le32 *)(pkt) + 0x00, value, BIT(31))
419
420 #define CH_INFO_SET_CH(pkt, value) \
421 u8p_replace_bits((u8 *)(pkt) + 0x00, value, GENMASK(7, 0))
422 #define CH_INFO_SET_PRI_CH_IDX(pkt, value) \
423 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(3, 0))
424 #define CH_INFO_SET_BW(pkt, value) \
425 u8p_replace_bits((u8 *)(pkt) + 0x01, value, GENMASK(7, 4))
426 #define CH_INFO_SET_TIMEOUT(pkt, value) \
427 u8p_replace_bits((u8 *)(pkt) + 0x02, value, GENMASK(7, 0))
428 #define CH_INFO_SET_ACTION_ID(pkt, value) \
429 u8p_replace_bits((u8 *)(pkt) + 0x03, value, GENMASK(6, 0))
430 #define CH_INFO_SET_EXTRA_INFO(pkt, value) \
431 u8p_replace_bits((u8 *)(pkt) + 0x03, value, BIT(7))
432
433 #define EXTRA_CH_INFO_SET_ID(pkt, value) \
434 u8p_replace_bits((u8 *)(pkt) + 0x04, value, GENMASK(6, 0))
435 #define EXTRA_CH_INFO_SET_INFO(pkt, value) \
436 u8p_replace_bits((u8 *)(pkt) + 0x04, value, BIT(7))
437 #define EXTRA_CH_INFO_SET_SIZE(pkt, value) \
438 u8p_replace_bits((u8 *)(pkt) + 0x05, value, GENMASK(7, 0))
439 #define EXTRA_CH_INFO_SET_DFS_EXT_TIME(pkt, value) \
440 u8p_replace_bits((u8 *)(pkt) + 0x06, value, GENMASK(7, 0))
441
442 #define UPDATE_PKT_SET_SIZE(h2c_pkt, value) \
443 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 0))
444 #define UPDATE_PKT_SET_PKT_ID(h2c_pkt, value) \
445 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
446 #define UPDATE_PKT_SET_LOCATION(h2c_pkt, value) \
447 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 24))
448
449 #define CH_SWITCH_SET_START(h2c_pkt, value) \
450 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
451 #define CH_SWITCH_SET_DEST_CH_EN(h2c_pkt, value) \
452 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
453 #define CH_SWITCH_SET_ABSOLUTE_TIME(h2c_pkt, value) \
454 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2))
455 #define CH_SWITCH_SET_PERIODIC_OPT(h2c_pkt, value) \
456 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(4, 3))
457 #define CH_SWITCH_SET_SCAN_MODE(h2c_pkt, value) \
458 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(5))
459 #define CH_SWITCH_SET_BACK_OP_EN(h2c_pkt, value) \
460 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(6))
461 #define CH_SWITCH_SET_INFO_LOC(h2c_pkt, value) \
462 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
463 #define CH_SWITCH_SET_CH_NUM(h2c_pkt, value) \
464 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(23, 16))
465 #define CH_SWITCH_SET_PRI_CH_IDX(h2c_pkt, value) \
466 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(27, 24))
467 #define CH_SWITCH_SET_DEST_BW(h2c_pkt, value) \
468 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 28))
469 #define CH_SWITCH_SET_DEST_CH(h2c_pkt, value) \
470 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))
471 #define CH_SWITCH_SET_NORMAL_PERIOD(h2c_pkt, value) \
472 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(13, 8))
473 #define CH_SWITCH_SET_NORMAL_PERIOD_SEL(h2c_pkt, value) \
474 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 14))
475 #define CH_SWITCH_SET_SLOW_PERIOD(h2c_pkt, value) \
476 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(21, 16))
477 #define CH_SWITCH_SET_SLOW_PERIOD_SEL(h2c_pkt, value) \
478 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 22))
479 #define CH_SWITCH_SET_NORMAL_CYCLE(h2c_pkt, value) \
480 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(31, 24))
481 #define CH_SWITCH_SET_TSF_HIGH(h2c_pkt, value) \
482 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 0))
483 #define CH_SWITCH_SET_TSF_LOW(h2c_pkt, value) \
484 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(31, 0))
485 #define CH_SWITCH_SET_INFO_SIZE(h2c_pkt, value) \
486 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x06, value, GENMASK(15, 0))
487
488 #define SCAN_OFFLOAD_SET_START(h2c_pkt, value) \
489 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(0))
490 #define SCAN_OFFLOAD_SET_BACK_OP_EN(h2c_pkt, value) \
491 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(1))
492 #define SCAN_OFFLOAD_SET_RANDOM_SEQ_EN(h2c_pkt, value) \
493 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(2))
494 #define SCAN_OFFLOAD_SET_NO_CCK_EN(h2c_pkt, value) \
495 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(3))
496 #define SCAN_OFFLOAD_SET_VERBOSE(h2c_pkt, value) \
497 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, BIT(4))
498 #define SCAN_OFFLOAD_SET_CH_NUM(h2c_pkt, value) \
499 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(15, 8))
500 #define SCAN_OFFLOAD_SET_CH_INFO_SIZE(h2c_pkt, value) \
501 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x02, value, GENMASK(31, 16))
502 #define SCAN_OFFLOAD_SET_CH_INFO_LOC(h2c_pkt, value) \
503 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(7, 0))
504 #define SCAN_OFFLOAD_SET_OP_CH(h2c_pkt, value) \
505 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(15, 8))
506 #define SCAN_OFFLOAD_SET_OP_PRI_CH_IDX(h2c_pkt, value) \
507 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(19, 16))
508 #define SCAN_OFFLOAD_SET_OP_BW(h2c_pkt, value) \
509 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(23, 20))
510 #define SCAN_OFFLOAD_SET_OP_PORT_ID(h2c_pkt, value) \
511 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x03, value, GENMASK(26, 24))
512 #define SCAN_OFFLOAD_SET_OP_DWELL_TIME(h2c_pkt, value) \
513 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(15, 0))
514 #define SCAN_OFFLOAD_SET_OP_GAP_TIME(h2c_pkt, value) \
515 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x04, value, GENMASK(31, 16))
516 #define SCAN_OFFLOAD_SET_MODE(h2c_pkt, value) \
517 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(3, 0))
518 #define SCAN_OFFLOAD_SET_SSID_NUM(h2c_pkt, value) \
519 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(7, 4))
520 #define SCAN_OFFLOAD_SET_PKT_LOC(h2c_pkt, value) \
521 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x05, value, GENMASK(15, 8))
522
523 /* Command H2C */
524 #define H2C_CMD_RSVD_PAGE 0x0
525 #define H2C_CMD_MEDIA_STATUS_RPT 0x01
526 #define H2C_CMD_SET_PWR_MODE 0x20
527 #define H2C_CMD_LPS_PG_INFO 0x2b
528 #define H2C_CMD_RA_INFO 0x40
529 #define H2C_CMD_RSSI_MONITOR 0x42
530 #define H2C_CMD_BCN_FILTER_OFFLOAD_P0 0x56
531 #define H2C_CMD_BCN_FILTER_OFFLOAD_P1 0x57
532 #define H2C_CMD_WL_PHY_INFO 0x58
533 #define H2C_CMD_SCAN 0x59
534 #define H2C_CMD_ADAPTIVITY 0x5A
535
536 #define H2C_CMD_COEX_TDMA_TYPE 0x60
537 #define H2C_CMD_QUERY_BT_INFO 0x61
538 #define H2C_CMD_FORCE_BT_TX_POWER 0x62
539 #define H2C_CMD_IGNORE_WLAN_ACTION 0x63
540 #define H2C_CMD_WL_CH_INFO 0x66
541 #define H2C_CMD_QUERY_BT_MP_INFO 0x67
542 #define H2C_CMD_BT_WIFI_CONTROL 0x69
543 #define H2C_CMD_WIFI_CALIBRATION 0x6d
544 #define H2C_CMD_QUERY_BT_HID_INFO 0x73
545
546 #define H2C_CMD_KEEP_ALIVE 0x03
547 #define H2C_CMD_DISCONNECT_DECISION 0x04
548 #define H2C_CMD_WOWLAN 0x80
549 #define H2C_CMD_REMOTE_WAKE_CTRL 0x81
550 #define H2C_CMD_AOAC_GLOBAL_INFO 0x82
551 #define H2C_CMD_NLO_INFO 0x8C
552
553 #define SET_H2C_CMD_ID_CLASS(h2c_pkt, value) \
554 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(7, 0))
555
556 #define MEDIA_STATUS_RPT_SET_OP_MODE(h2c_pkt, value) \
557 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
558 #define MEDIA_STATUS_RPT_SET_MACID(h2c_pkt, value) \
559 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
560
561 #define SET_WL_PHY_INFO_TX_TP(h2c_pkt, value) \
562 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(17, 8))
563 #define SET_WL_PHY_INFO_RX_TP(h2c_pkt, value) \
564 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(27, 18))
565 #define SET_WL_PHY_INFO_TX_RATE_DESC(h2c_pkt, value) \
566 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
567 #define SET_WL_PHY_INFO_RX_RATE_DESC(h2c_pkt, value) \
568 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
569 #define SET_WL_PHY_INFO_RX_EVM(h2c_pkt, value) \
570 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
571 #define SET_BCN_FILTER_OFFLOAD_P1_MACID(h2c_pkt, value) \
572 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
573 #define SET_BCN_FILTER_OFFLOAD_P1_ENABLE(h2c_pkt, value) \
574 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(16))
575 #define SET_BCN_FILTER_OFFLOAD_P1_HYST(h2c_pkt, value) \
576 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 17))
577 #define SET_BCN_FILTER_OFFLOAD_P1_OFFLOAD_MODE(h2c_pkt, value) \
578 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 21))
579 #define SET_BCN_FILTER_OFFLOAD_P1_THRESHOLD(h2c_pkt, value) \
580 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
581 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_LOSS_CNT(h2c_pkt, value) \
582 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(3, 0))
583 #define SET_BCN_FILTER_OFFLOAD_P1_BCN_INTERVAL(h2c_pkt, value) \
584 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(13, 4))
585
586 #define SET_SCAN_START(h2c_pkt, value) \
587 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
588
589 #define SET_ADAPTIVITY_MODE(h2c_pkt, value) \
590 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(11, 8))
591 #define SET_ADAPTIVITY_OPTION(h2c_pkt, value) \
592 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
593 #define SET_ADAPTIVITY_IGI(h2c_pkt, value) \
594 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
595 #define SET_ADAPTIVITY_L2H(h2c_pkt, value) \
596 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
597 #define SET_ADAPTIVITY_DENSITY(h2c_pkt, value) \
598 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
599
600 #define SET_PWR_MODE_SET_MODE(h2c_pkt, value) \
601 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(14, 8))
602 #define SET_PWR_MODE_SET_RLBM(h2c_pkt, value) \
603 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(19, 16))
604 #define SET_PWR_MODE_SET_SMART_PS(h2c_pkt, value) \
605 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 20))
606 #define SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c_pkt, value) \
607 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
608 #define SET_PWR_MODE_SET_PORT_ID(h2c_pkt, value) \
609 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 5))
610 #define SET_PWR_MODE_SET_PWR_STATE(h2c_pkt, value) \
611 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
612 #define LPS_PG_INFO_LOC(h2c_pkt, value) \
613 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
614 #define LPS_PG_DPK_LOC(h2c_pkt, value) \
615 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
616 #define LPS_PG_SEC_CAM_EN(h2c_pkt, value) \
617 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
618 #define LPS_PG_PATTERN_CAM_EN(h2c_pkt, value) \
619 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
620 #define SET_RSSI_INFO_MACID(h2c_pkt, value) \
621 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
622 #define SET_RSSI_INFO_RSSI(h2c_pkt, value) \
623 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
624 #define SET_RSSI_INFO_STBC(h2c_pkt, value) \
625 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, BIT(1))
626 #define SET_RA_INFO_MACID(h2c_pkt, value) \
627 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
628 #define SET_RA_INFO_RATE_ID(h2c_pkt, value) \
629 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(20, 16))
630 #define SET_RA_INFO_INIT_RA_LVL(h2c_pkt, value) \
631 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(22, 21))
632 #define SET_RA_INFO_SGI_EN(h2c_pkt, value) \
633 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(23))
634 #define SET_RA_INFO_BW_MODE(h2c_pkt, value) \
635 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(25, 24))
636 #define SET_RA_INFO_LDPC(h2c_pkt, value) \
637 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(26))
638 #define SET_RA_INFO_NO_UPDATE(h2c_pkt, value) \
639 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(27))
640 #define SET_RA_INFO_VHT_EN(h2c_pkt, value) \
641 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(29, 28))
642 #define SET_RA_INFO_DIS_PT(h2c_pkt, value) \
643 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(30))
644 #define SET_RA_INFO_RA_MASK0(h2c_pkt, value) \
645 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
646 #define SET_RA_INFO_RA_MASK1(h2c_pkt, value) \
647 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
648 #define SET_RA_INFO_RA_MASK2(h2c_pkt, value) \
649 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
650 #define SET_RA_INFO_RA_MASK3(h2c_pkt, value) \
651 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 24))
652 #define SET_QUERY_BT_INFO(h2c_pkt, value) \
653 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
654 #define SET_WL_CH_INFO_LINK(h2c_pkt, value) \
655 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
656 #define SET_WL_CH_INFO_CHNL(h2c_pkt, value) \
657 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
658 #define SET_WL_CH_INFO_BW(h2c_pkt, value) \
659 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
660 #define SET_BT_MP_INFO_SEQ(h2c_pkt, value) \
661 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 12))
662 #define SET_BT_MP_INFO_OP_CODE(h2c_pkt, value) \
663 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
664 #define SET_BT_MP_INFO_PARA1(h2c_pkt, value) \
665 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
666 #define SET_BT_MP_INFO_PARA2(h2c_pkt, value) \
667 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
668 #define SET_BT_MP_INFO_PARA3(h2c_pkt, value) \
669 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
670 #define SET_BT_TX_POWER_INDEX(h2c_pkt, value) \
671 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
672 #define SET_IGNORE_WLAN_ACTION_EN(h2c_pkt, value) \
673 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
674 #define SET_COEX_TDMA_TYPE_PARA1(h2c_pkt, value) \
675 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
676 #define SET_COEX_TDMA_TYPE_PARA2(h2c_pkt, value) \
677 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
678 #define SET_COEX_TDMA_TYPE_PARA3(h2c_pkt, value) \
679 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
680 #define SET_COEX_TDMA_TYPE_PARA4(h2c_pkt, value) \
681 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
682 #define SET_COEX_TDMA_TYPE_PARA5(h2c_pkt, value) \
683 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
684 #define SET_BT_WIFI_CONTROL_OP_CODE(h2c_pkt, value) \
685 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
686 #define SET_BT_WIFI_CONTROL_DATA1(h2c_pkt, value) \
687 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
688 #define SET_BT_WIFI_CONTROL_DATA2(h2c_pkt, value) \
689 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
690 #define SET_BT_WIFI_CONTROL_DATA3(h2c_pkt, value) \
691 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(7, 0))
692 #define SET_BT_WIFI_CONTROL_DATA4(h2c_pkt, value) \
693 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 8))
694 #define SET_BT_WIFI_CONTROL_DATA5(h2c_pkt, value) \
695 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(23, 16))
696
697 #define SET_COEX_QUERY_HID_INFO_SUBID(h2c_pkt, value) \
698 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
699 #define SET_COEX_QUERY_HID_INFO_DATA1(h2c_pkt, value) \
700 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
701
702 #define SET_KEEP_ALIVE_ENABLE(h2c_pkt, value) \
703 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
704 #define SET_KEEP_ALIVE_ADOPT(h2c_pkt, value) \
705 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
706 #define SET_KEEP_ALIVE_PKT_TYPE(h2c_pkt, value) \
707 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
708 #define SET_KEEP_ALIVE_CHECK_PERIOD(h2c_pkt, value) \
709 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
710
711 #define SET_DISCONNECT_DECISION_ENABLE(h2c_pkt, value) \
712 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
713 #define SET_DISCONNECT_DECISION_ADOPT(h2c_pkt, value) \
714 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
715 #define SET_DISCONNECT_DECISION_CHECK_PERIOD(h2c_pkt, value) \
716 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
717 #define SET_DISCONNECT_DECISION_TRY_PKT_NUM(h2c_pkt, value) \
718 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 24))
719
720 #define SET_WOWLAN_FUNC_ENABLE(h2c_pkt, value) \
721 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
722 #define SET_WOWLAN_PATTERN_MATCH_ENABLE(h2c_pkt, value) \
723 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
724 #define SET_WOWLAN_MAGIC_PKT_ENABLE(h2c_pkt, value) \
725 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
726 #define SET_WOWLAN_UNICAST_PKT_ENABLE(h2c_pkt, value) \
727 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(11))
728 #define SET_WOWLAN_REKEY_WAKEUP_ENABLE(h2c_pkt, value) \
729 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(14))
730 #define SET_WOWLAN_DEAUTH_WAKEUP_ENABLE(h2c_pkt, value) \
731 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(15))
732
733 #define SET_REMOTE_WAKECTRL_ENABLE(h2c_pkt, value) \
734 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
735 #define SET_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(h2c_pkt, value) \
736 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(12))
737
738 #define SET_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(h2c_pkt, value) \
739 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
740 #define SET_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(h2c_pkt, value) \
741 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
742
743 #define SET_NLO_FUN_EN(h2c_pkt, value) \
744 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
745 #define SET_NLO_PS_32K(h2c_pkt, value) \
746 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(9))
747 #define SET_NLO_IGNORE_SECURITY(h2c_pkt, value) \
748 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(10))
749 #define SET_NLO_LOC_NLO_INFO(h2c_pkt, value) \
750 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(23, 16))
751
752 #define GET_FW_DUMP_LEN(_header) \
753 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(15, 0))
754 #define GET_FW_DUMP_SEQ(_header) \
755 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(22, 16))
756 #define GET_FW_DUMP_MORE(_header) \
757 le32_get_bits(*((__le32 *)(_header) + 0x00), BIT(23))
758 #define GET_FW_DUMP_VERSION(_header) \
759 le32_get_bits(*((__le32 *)(_header) + 0x00), GENMASK(31, 24))
760 #define GET_FW_DUMP_TLV_TYPE(_header) \
761 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(15, 0))
762 #define GET_FW_DUMP_TLV_LEN(_header) \
763 le32_get_bits(*((__le32 *)(_header) + 0x01), GENMASK(31, 16))
764 #define GET_FW_DUMP_TLV_VAL(_header) \
765 le32_get_bits(*((__le32 *)(_header) + 0x02), GENMASK(31, 0))
766
767 #define RFK_SET_INFORM_START(h2c_pkt, value) \
768 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, BIT(8))
get_c2h_from_skb(struct sk_buff * skb)769 static inline struct rtw_c2h_cmd *get_c2h_from_skb(struct sk_buff *skb)
770 {
771 u32 pkt_offset;
772
773 pkt_offset = *((u32 *)skb->cb);
774 return (struct rtw_c2h_cmd *)(skb->data + pkt_offset);
775 }
776
rtw_fw_feature_check(struct rtw_fw_state * fw,enum rtw_fw_feature feature)777 static inline bool rtw_fw_feature_check(struct rtw_fw_state *fw,
778 enum rtw_fw_feature feature)
779 {
780 return !!(fw->feature & feature);
781 }
782
rtw_fw_feature_ext_check(struct rtw_fw_state * fw,enum rtw_fw_feature_ext feature)783 static inline bool rtw_fw_feature_ext_check(struct rtw_fw_state *fw,
784 enum rtw_fw_feature_ext feature)
785 {
786 return !!(fw->feature_ext & feature);
787 }
788
789 void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset,
790 struct sk_buff *skb);
791 void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb);
792 void rtw_fw_send_general_info(struct rtw_dev *rtwdev);
793 void rtw_fw_send_phydm_info(struct rtw_dev *rtwdev);
794
795 void rtw_fw_do_iqk(struct rtw_dev *rtwdev, struct rtw_iqk_para *para);
796 void rtw_fw_inform_rfk_status(struct rtw_dev *rtwdev, bool start);
797 void rtw_fw_set_pwr_mode(struct rtw_dev *rtwdev);
798 void rtw_fw_set_pg_info(struct rtw_dev *rtwdev);
799 void rtw_fw_query_bt_info(struct rtw_dev *rtwdev);
800 void rtw_fw_wl_ch_info(struct rtw_dev *rtwdev, u8 link, u8 ch, u8 bw);
801 void rtw_fw_query_bt_mp_info(struct rtw_dev *rtwdev,
802 struct rtw_coex_info_req *req);
803 void rtw_fw_force_bt_tx_power(struct rtw_dev *rtwdev, u8 bt_pwr_dec_lvl);
804 void rtw_fw_bt_ignore_wlan_action(struct rtw_dev *rtwdev, bool enable);
805 void rtw_fw_coex_tdma_type(struct rtw_dev *rtwdev,
806 u8 para1, u8 para2, u8 para3, u8 para4, u8 para5);
807 void rtw_fw_coex_query_hid_info(struct rtw_dev *rtwdev, u8 sub_id, u8 data);
808
809 void rtw_fw_bt_wifi_control(struct rtw_dev *rtwdev, u8 op_code, u8 *data);
810 void rtw_fw_send_rssi_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
811 void rtw_fw_send_ra_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si,
812 bool reset_ra_mask);
813 void rtw_fw_media_status_report(struct rtw_dev *rtwdev, u8 mac_id, bool conn);
814 void rtw_fw_update_wl_phy_info(struct rtw_dev *rtwdev);
815 void rtw_fw_beacon_filter_config(struct rtw_dev *rtwdev, bool connect,
816 struct ieee80211_vif *vif);
817 int rtw_fw_write_data_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
818 u8 *buf, u32 size);
819 void rtw_remove_rsvd_page(struct rtw_dev *rtwdev,
820 struct rtw_vif *rtwvif);
821 void rtw_add_rsvd_page_bcn(struct rtw_dev *rtwdev,
822 struct rtw_vif *rtwvif);
823 void rtw_add_rsvd_page_pno(struct rtw_dev *rtwdev,
824 struct rtw_vif *rtwvif);
825 void rtw_add_rsvd_page_sta(struct rtw_dev *rtwdev,
826 struct rtw_vif *rtwvif);
827 int rtw_fw_download_rsvd_page(struct rtw_dev *rtwdev);
828 void rtw_fw_update_beacon_work(struct work_struct *work);
829 void rtw_send_rsvd_page_h2c(struct rtw_dev *rtwdev);
830 int rtw_dump_drv_rsvd_page(struct rtw_dev *rtwdev,
831 u32 offset, u32 size, u32 *buf);
832 void rtw_fw_set_remote_wake_ctrl_cmd(struct rtw_dev *rtwdev, bool enable);
833 void rtw_fw_set_wowlan_ctrl_cmd(struct rtw_dev *rtwdev, bool enable);
834 void rtw_fw_set_keep_alive_cmd(struct rtw_dev *rtwdev, bool enable);
835 void rtw_fw_set_disconnect_decision_cmd(struct rtw_dev *rtwdev, bool enable);
836 void rtw_fw_set_aoac_global_info_cmd(struct rtw_dev *rtwdev,
837 u8 pairwise_key_enc,
838 u8 group_key_enc);
839
840 void rtw_fw_set_nlo_info(struct rtw_dev *rtwdev, bool enable);
841 void rtw_fw_update_pkt_probe_req(struct rtw_dev *rtwdev,
842 struct cfg80211_ssid *ssid);
843 void rtw_fw_channel_switch(struct rtw_dev *rtwdev, bool enable);
844 void rtw_fw_h2c_cmd_dbg(struct rtw_dev *rtwdev, u8 *h2c);
845 void rtw_fw_c2h_cmd_isr(struct rtw_dev *rtwdev);
846 int rtw_fw_dump_fifo(struct rtw_dev *rtwdev, u8 fifo_sel, u32 addr, u32 size,
847 u32 *buffer);
848 void rtw_fw_scan_notify(struct rtw_dev *rtwdev, bool start);
849 void rtw_fw_adaptivity(struct rtw_dev *rtwdev);
850 void rtw_store_op_chan(struct rtw_dev *rtwdev, bool backup);
851 void rtw_clear_op_chan(struct rtw_dev *rtwdev);
852 void rtw_hw_scan_start(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
853 struct ieee80211_scan_request *req);
854 void rtw_hw_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
855 bool aborted);
856 int rtw_hw_scan_offload(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
857 bool enable);
858 void rtw_hw_scan_status_report(struct rtw_dev *rtwdev, struct sk_buff *skb);
859 void rtw_hw_scan_chan_switch(struct rtw_dev *rtwdev, struct sk_buff *skb);
860 void rtw_hw_scan_abort(struct rtw_dev *rtwdev, struct ieee80211_vif *vif);
861 #endif
862