Searched refs:Reset (Results 1 – 25 of 378) sorted by relevance
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| /linux-6.1.9/drivers/reset/ |
| D | Kconfig | 6 bool "Reset Controller Support"
9 Generic Reset Controller support.
19 tristate "Altera Arria10 System Resource Reset"
26 bool "AR71xx Reset Driver" if COMPILE_TEST
33 bool "AXS10x Reset Driver" if COMPILE_TEST
39 bool "BCM6345 Reset Controller"
46 tristate "Berlin Reset Driver"
70 bool "Synopsys HSDK Reset Driver"
77 tristate "i.MX7/8 Reset Driver"
86 bool "Intel Reset Controller Driver"
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| /linux-6.1.9/Documentation/devicetree/bindings/reset/ |
| D | amlogic,meson-reset.yaml | 8 title: Amlogic Meson SoC Reset Controller
16 - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
17 - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
18 - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
19 - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs
20 - amlogic,meson-s4-reset # Reset Controller on S4 and compatible SoCs
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| D | nxp,lpc1850-rgu.txt | 1 NXP LPC1850 Reset Generation Unit (RGU)
18 Reset Peripheral
64 Reset provider example:
73 Reset consumer example:
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| D | microchip,rst.yaml | 7 title: Microchip Sparx5 Switch Reset Controller
16 - One Time Switch Core Reset (Soft Reset)
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| D | zynq-reset.txt | 1 Xilinx Zynq Reset Manager
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
24 Reset outputs:
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| D | ti-syscon-reset.txt | 1 TI SysCon Reset Controller
12 A SysCon Reset Controller node defines a device that uses a syscon node
16 SysCon Reset Controller Node
49 SysCon Reset Consumer Nodes
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| D | renesas,rst.yaml | 7 title: Renesas R-Car and RZ/G Reset Controller
14 The R-Car and RZ/G Reset Controllers provide reset control, and implement the
18 - Reset control of peripheral devices (on R-Car Gen1),
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| D | reset.txt | 1 = Reset Signal Device Tree Bindings =
4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
32 = Reset providers =
45 = Reset consumers =
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| D | intel,rcu-gw.yaml | 7 title: System Reset Controller on Intel Gateway SoCs
19 description: Reset controller registers.
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| D | st,stm32-rcc.txt | 1 STMicroelectronics STM32 Peripheral Reset Controller
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| D | st,stm32mp1-rcc.txt | 1 STMicroelectronics STM32MP1 Peripheral Reset Controller
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| /linux-6.1.9/Documentation/hwmon/ |
| D | ltc3815.rst | 44 in1_reset_history Reset input voltage history.
50 in2_reset_history Reset output voltage history.
55 temp1_reset_history Reset temperature history.
60 curr1_reset_history Reset input current history.
66 curr2_reset_history Reset output current history.
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| /linux-6.1.9/Documentation/devicetree/bindings/watchdog/ |
| D | aspeed-wdt.txt | 16 Reset behavior - Whenever a timeout occurs the watchdog can be programmed
26 Reset types:
28 - cpu: Reset CPU on watchdog timeout
30 - soc: Reset 'System on Chip' on watchdog timeout
32 - system: Reset system on watchdog timeout
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| D | realtek,otto-wdt.yaml | 56 - description: Reset the entire chip
59 Reset the CPU and IPsec engine, but leave other peripherals untouched
62 Reset the execution pointer, but don't actually reset any hardware
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| /linux-6.1.9/Documentation/driver-api/ |
| D | reset.rst | 4 Reset controller API
10 Reset controllers are central units that control the reset signals to multiple
29 Reset line
34 Reset control
44 Reset controller
49 Reset consumer
146 Reset control arrays
155 Reset controller driver interface
178 Reset consumer API
181 Reset consumers can control a reset line using an opaque reset control handle,
[all …]
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| /linux-6.1.9/drivers/reset/hisilicon/ |
| D | Kconfig | 3 tristate "Hi3660 Reset Driver"
10 tristate "Hi6220 Reset Driver"
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| /linux-6.1.9/drivers/acpi/arm64/ |
| D | Kconfig | 13 bool "Arm Generic Diagnostic Dump and Reset Device Interface"
16 Arm Generic Diagnostic Dump and Reset Device Interface (AGDI) is
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| /linux-6.1.9/drivers/platform/mips/ |
| D | Kconfig | 34 bool "Loongson-2K1000 Reset Controller"
37 Loongson-2K1000 Reset Controller driver.
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| /linux-6.1.9/Documentation/driver-api/mmc/ |
| D | mmc-tools.rst | 26 - Permanently enable the eMMC H/W Reset feature.
27 - Permanently disable the eMMC H/W Reset feature.
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| /linux-6.1.9/Documentation/devicetree/bindings/display/ |
| D | allwinner,sun4i-a10-tcon.yaml | 86 - description: TCON Reset Line
89 - description: TCON Reset Line
90 - description: TCON LVDS Reset Line
93 - description: TCON Reset Line
94 - description: TCON eDP Reset Line
97 - description: TCON Reset Line
98 - description: TCON eDP Reset Line
99 - description: TCON LVDS Reset Line
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| /linux-6.1.9/Documentation/devicetree/bindings/mfd/ |
| D | altera-a10sr.txt | 20 a10sr_rst Reset Controller
30 Arria10 Peripheral PHY Reset
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| /linux-6.1.9/init/ |
| D | initramfs.c | 227 Reset enumerator
366 next_state = Reset; in do_name()
437 next_state = Reset; in do_symlink()
449 [Reset] = do_reset,
478 state = Reset; in flush_buffer()
538 if (state != Reset) in unpack_to_rootfs()
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| /linux-6.1.9/Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx93-src.yaml | 7 title: NXP i.MX93 System Reset Controller
13 The System Reset Controller (SRC) is responsible for the generation of
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| /linux-6.1.9/Documentation/devicetree/bindings/clock/ |
| D | renesas,cpg-mssr.yaml | 7 title: Renesas Clock Pulse Generator / Module Standby and Software Reset
14 and MSSR (Module Standby and Software Reset) blocks are intimately connected,
22 2. Reset Control, to perform a software reset of individual SoC devices.
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| D | nvidia,tegra20-car.yaml | 7 title: NVIDIA Tegra Clock and Reset Controller
14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
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