1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_REG_H__ 6 #define __RTW89_REG_H__ 7 8 #define R_AX_SYS_WL_EFUSE_CTRL 0x000A 9 #define B_AX_AUTOLOAD_SUS BIT(5) 10 11 #define R_AX_SYS_ISO_CTRL 0x0000 12 #define B_AX_PWC_EV2EF_MASK GENMASK(15, 14) 13 #define B_AX_PWC_EV2EF_B15 BIT(15) 14 #define B_AX_PWC_EV2EF_B14 BIT(14) 15 #define B_AX_ISO_EB2CORE BIT(8) 16 17 #define R_AX_SYS_FUNC_EN 0x0002 18 #define B_AX_FEN_BB_GLB_RSTN BIT(1) 19 #define B_AX_FEN_BBRSTB BIT(0) 20 21 #define R_AX_SYS_PW_CTRL 0x0004 22 #define B_AX_XTAL_OFF_A_DIE BIT(22) 23 #define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18) 24 #define B_AX_RDY_SYSPWR BIT(17) 25 #define B_AX_EN_WLON BIT(16) 26 #define B_AX_APDM_HPDN BIT(15) 27 #define B_AX_PSUS_OFF_CAPC_EN BIT(14) 28 #define B_AX_AFSM_PCIE_SUS_EN BIT(12) 29 #define B_AX_AFSM_WLSUS_EN BIT(11) 30 #define B_AX_APFM_SWLPS BIT(10) 31 #define B_AX_APFM_OFFMAC BIT(9) 32 #define B_AX_APFN_ONMAC BIT(8) 33 34 #define R_AX_SYS_CLK_CTRL 0x0008 35 #define B_AX_CPU_CLK_EN BIT(14) 36 37 #define R_AX_SYS_ADIE_PAD_PWR_CTRL 0x0018 38 #define B_AX_SYM_PADPDN_WL_PTA_1P3 BIT(6) 39 #define B_AX_SYM_PADPDN_WL_RFC_1P3 BIT(5) 40 41 #define R_AX_RSV_CTRL 0x001C 42 #define B_AX_R_DIS_PRST BIT(6) 43 #define B_AX_WLOCK_1C_BIT6 BIT(5) 44 45 #define R_AX_EFUSE_CTRL_1 0x0038 46 #define B_AX_EF_PGPD_MASK GENMASK(30, 28) 47 #define B_AX_EF_RDT BIT(27) 48 #define B_AX_EF_VDDQST_MASK GENMASK(26, 24) 49 #define B_AX_EF_PGTS_MASK GENMASK(23, 20) 50 #define B_AX_EF_PD_DIS BIT(11) 51 #define B_AX_EF_POR BIT(10) 52 #define B_AX_EF_CELL_SEL_MASK GENMASK(9, 8) 53 54 #define R_AX_EFUSE_CTRL 0x0030 55 #define B_AX_EF_MODE_SEL_MASK GENMASK(31, 30) 56 #define B_AX_EF_RDY BIT(29) 57 #define B_AX_EF_COMP_RESULT BIT(28) 58 #define B_AX_EF_ADDR_MASK GENMASK(26, 16) 59 #define B_AX_EF_DATA_MASK GENMASK(15, 0) 60 61 #define R_AX_EFUSE_CTRL_1_V1 0x0038 62 #define B_AX_EF_ENT BIT(31) 63 #define B_AX_EF_BURST BIT(19) 64 #define B_AX_EF_TEST_SEL_MASK GENMASK(18, 16) 65 #define B_AX_EF_TROW_EN BIT(15) 66 #define B_AX_EF_ERR_FLAG BIT(14) 67 #define B_AX_EF_DSB_EN BIT(11) 68 #define B_AX_PCIE_CALIB_EN_V1 BIT(12) 69 #define B_AX_WDT_WAKE_PCIE_EN BIT(10) 70 #define B_AX_WDT_WAKE_USB_EN BIT(9) 71 72 #define R_AX_GPIO_MUXCFG 0x0040 73 #define B_AX_BOOT_MODE BIT(19) 74 #define B_AX_WL_EECS_EXT_32K_SEL BIT(18) 75 #define B_AX_WL_SEC_BONDING_OPT_STS BIT(17) 76 #define B_AX_SECSIC_SEL BIT(16) 77 #define B_AX_ENHTP BIT(14) 78 #define B_AX_BT_AOD_GPIO3 BIT(13) 79 #define B_AX_ENSIC BIT(12) 80 #define B_AX_SIC_SWRST BIT(11) 81 #define B_AX_PO_WIFI_PTA_PINS BIT(10) 82 #define B_AX_PO_BT_PTA_PINS BIT(9) 83 #define B_AX_ENUARTTX BIT(8) 84 #define B_AX_BTMODE_MASK GENMASK(7, 6) 85 #define MAC_AX_BT_MODE_0_3 0 86 #define MAC_AX_BT_MODE_2 2 87 #define MAC_AX_RTK_MODE 0 88 #define MAC_AX_CSR_MODE 1 89 #define B_AX_ENBT BIT(5) 90 #define B_AX_EROM_EN BIT(4) 91 #define B_AX_ENUARTRX BIT(2) 92 #define B_AX_GPIOSEL_MASK GENMASK(1, 0) 93 94 #define R_AX_DBG_CTRL 0x0058 95 #define B_AX_DBG_SEL1_4BIT GENMASK(31, 30) 96 #define B_AX_DBG_SEL1_16BIT BIT(27) 97 #define B_AX_DBG_SEL1 GENMASK(23, 16) 98 #define B_AX_DBG_SEL0_4BIT GENMASK(15, 14) 99 #define B_AX_DBG_SEL0_16BIT BIT(11) 100 #define B_AX_DBG_SEL0 GENMASK(7, 0) 101 102 #define R_AX_SYS_SDIO_CTRL 0x0070 103 #define B_AX_PCIE_DIS_L2_CTRL_LDO_HCI BIT(15) 104 #define B_AX_PCIE_DIS_WLSUS_AFT_PDN BIT(14) 105 #define B_AX_PCIE_FORCE_PWR_NGAT BIT(13) 106 #define B_AX_PCIE_CALIB_EN_V1 BIT(12) 107 #define B_AX_PCIE_AUXCLK_GATE BIT(11) 108 #define B_AX_LTE_MUX_CTRL_PATH BIT(26) 109 110 #define R_AX_HCI_OPT_CTRL 0x0074 111 #define BIT_WAKE_CTRL BIT(5) 112 113 #define R_AX_HCI_BG_CTRL 0x0078 114 #define B_AX_IBX_EN_VALUE BIT(15) 115 #define B_AX_IB_EN_VALUE BIT(14) 116 #define B_AX_FORCED_IB_EN BIT(4) 117 #define B_AX_EN_REGBG BIT(3) 118 #define B_AX_R_AX_BG_LPF BIT(2) 119 #define B_AX_R_AX_BG GENMASK(1, 0) 120 121 #define R_AX_PLATFORM_ENABLE 0x0088 122 #define B_AX_AXIDMA_EN BIT(3) 123 #define B_AX_WCPU_EN BIT(1) 124 #define B_AX_PLATFORM_EN BIT(0) 125 126 #define R_AX_WLLPS_CTRL 0x0090 127 #define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1) 128 129 #define R_AX_SCOREBOARD 0x00AC 130 #define B_AX_TOGGLE BIT(31) 131 #define B_MAC_AX_SB_FW_MASK GENMASK(30, 24) 132 #define B_MAC_AX_SB_DRV_MASK GENMASK(23, 0) 133 #define B_MAC_AX_BTGS1_NOTIFY BIT(0) 134 #define MAC_AX_NOTIFY_TP_MAJOR 0x81 135 #define MAC_AX_NOTIFY_PWR_MAJOR 0x80 136 137 #define R_AX_DBG_PORT_SEL 0x00C0 138 #define B_AX_DEBUG_ST_MASK GENMASK(31, 0) 139 140 #define R_AX_PMC_DBG_CTRL2 0x00CC 141 #define B_AX_SYSON_DIS_PMCR_AX_WRMSK BIT(2) 142 143 #define R_AX_PCIE_MIO_INTF 0x00E4 144 #define B_AX_PCIE_MIO_ADDR_PAGE_V1_MASK GENMASK(20, 16) 145 #define B_AX_PCIE_MIO_BYIOREG BIT(13) 146 #define B_AX_PCIE_MIO_RE BIT(12) 147 #define B_AX_PCIE_MIO_WE_MASK GENMASK(11, 8) 148 #define MIO_WRITE_BYTE_ALL 0xF 149 #define B_AX_PCIE_MIO_ADDR_MASK GENMASK(7, 0) 150 #define MIO_ADDR_PAGE_MASK GENMASK(12, 8) 151 152 #define R_AX_PCIE_MIO_INTD 0x00E8 153 #define B_AX_PCIE_MIO_DATA_MASK GENMASK(31, 0) 154 155 #define R_AX_SYS_CFG1 0x00F0 156 #define B_AX_CHIP_VER_MASK GENMASK(15, 12) 157 158 #define R_AX_SYS_STATUS1 0x00F4 159 #define B_AX_SEL_0XC0_MASK GENMASK(17, 16) 160 #define B_AX_PAD_HCI_SEL_V2_MASK GENMASK(5, 3) 161 #define MAC_AX_HCI_SEL_SDIO_UART 0 162 #define MAC_AX_HCI_SEL_MULTI_USB 1 163 #define MAC_AX_HCI_SEL_PCIE_UART 2 164 #define MAC_AX_HCI_SEL_PCIE_USB 3 165 #define MAC_AX_HCI_SEL_MULTI_SDIO 4 166 167 #define R_AX_HALT_H2C_CTRL 0x0160 168 #define R_AX_HALT_H2C 0x0168 169 #define B_AX_HALT_H2C_TRIGGER BIT(0) 170 #define R_AX_HALT_C2H_CTRL 0x0164 171 #define R_AX_HALT_C2H 0x016C 172 173 #define R_AX_WCPU_FW_CTRL 0x01E0 174 #define B_AX_WCPU_FWDL_STS_MASK GENMASK(7, 5) 175 #define B_AX_FWDL_PATH_RDY BIT(2) 176 #define B_AX_H2C_PATH_RDY BIT(1) 177 #define B_AX_WCPU_FWDL_EN BIT(0) 178 179 #define R_AX_RPWM 0x01E4 180 #define R_AX_PCIE_HRPWM 0x10C0 181 #define PS_RPWM_TOGGLE BIT(15) 182 #define PS_RPWM_ACK BIT(14) 183 #define PS_RPWM_SEQ_NUM GENMASK(13, 12) 184 #define PS_RPWM_NOTIFY_WAKE BIT(8) 185 #define PS_RPWM_STATE 0x7 186 #define RPWM_SEQ_NUM_MAX 3 187 #define PS_CPWM_SEQ_NUM GENMASK(13, 12) 188 #define PS_CPWM_RSP_SEQ_NUM GENMASK(9, 8) 189 #define PS_CPWM_STATE GENMASK(2, 0) 190 #define CPWM_SEQ_NUM_MAX 3 191 192 #define R_AX_BOOT_REASON 0x01E6 193 #define B_AX_BOOT_REASON_MASK GENMASK(2, 0) 194 195 #define R_AX_LDM 0x01E8 196 #define B_AX_EN_32K BIT(31) 197 198 #define R_AX_UDM0 0x01F0 199 #define R_AX_UDM1 0x01F4 200 #define R_AX_UDM2 0x01F8 201 #define R_AX_UDM3 0x01FC 202 203 #define R_AX_SPS_DIG_ON_CTRL0 0x0200 204 #define B_AX_VREFPFM_L_MASK GENMASK(25, 22) 205 #define B_AX_REG_ZCDC_H_MASK GENMASK(18, 17) 206 #define B_AX_OCP_L1_MASK GENMASK(15, 13) 207 #define B_AX_VOL_L1_MASK GENMASK(3, 0) 208 209 #define R_AX_LDO_AON_CTRL0 0x0218 210 #define B_AX_PD_REGU_L BIT(16) 211 212 #define R_AX_WLAN_XTAL_SI_CTRL 0x0270 213 #define B_AX_WL_XTAL_SI_CMD_POLL BIT(31) 214 #define B_AX_BT_XTAL_SI_ERR_FLAG BIT(30) 215 #define B_AX_WL_XTAL_GNT BIT(29) 216 #define B_AX_BT_XTAL_GNT BIT(28) 217 #define B_AX_WL_XTAL_SI_MODE_MASK GENMASK(25, 24) 218 #define XTAL_SI_NORMAL_WRITE 0x00 219 #define XTAL_SI_NORMAL_READ 0x01 220 #define B_AX_WL_XTAL_SI_BITMASK_MASK GENMASK(23, 16) 221 #define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8) 222 #define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0) 223 224 #define R_AX_XTAL_ON_CTRL0 0x0280 225 #define B_AX_XTAL_SC_LPS BIT(31) 226 #define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17) 227 #define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10) 228 #define B_AX_XTAL_SC_MASK GENMASK(6, 0) 229 230 #define R_AX_GPIO0_7_FUNC_SEL 0x02D0 231 232 #define R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN 0x02E4 233 #define B_AX_LED1_PULL_LOW_EN BIT(18) 234 #define B_AX_EESK_PULL_LOW_EN BIT(17) 235 #define B_AX_EECS_PULL_LOW_EN BIT(16) 236 237 #define R_AX_WLRF_CTRL 0x02F0 238 #define B_AX_AFC_AFEDIG BIT(17) 239 #define B_AX_WLRF1_CTRL_7 BIT(15) 240 #define B_AX_WLRF1_CTRL_1 BIT(9) 241 #define B_AX_WLRF_CTRL_7 BIT(7) 242 #define B_AX_WLRF_CTRL_1 BIT(1) 243 244 #define R_AX_IC_PWR_STATE 0x03F0 245 #define B_AX_WHOLE_SYS_PWR_STE_MASK GENMASK(25, 16) 246 #define B_AX_WLMAC_PWR_STE_MASK GENMASK(9, 8) 247 #define B_AX_UART_HCISYS_PWR_STE_MASK GENMASK(7, 6) 248 #define B_AX_SDIO_HCISYS_PWR_STE_MASK GENMASK(5, 4) 249 #define B_AX_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2) 250 #define B_AX_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0) 251 252 #define R_AX_AFE_OFF_CTRL1 0x0444 253 #define B_AX_S1_LDO_VSEL_F_MASK GENMASK(25, 24) 254 #define B_AX_S1_LDO2PWRCUT_F BIT(23) 255 #define B_AX_S0_LDO_VSEL_F_MASK GENMASK(22, 21) 256 257 #define R_AX_FILTER_MODEL_ADDR 0x0C04 258 259 #define R_AX_HAXI_INIT_CFG1 0x1000 260 #define B_AX_WD_ITVL_IDLE_V1_MASK GENMASK(31, 28) 261 #define B_AX_WD_ITVL_ACT_V1_MASK GENMASK(27, 24) 262 #define B_AX_DMA_MODE_MASK GENMASK(19, 18) 263 #define DMA_MOD_PCIE_1B 0x0 264 #define DMA_MOD_PCIE_4B 0x1 265 #define DMA_MOD_USB 0x2 266 #define DMA_MOD_SDIO 0x3 267 #define B_AX_STOP_AXI_MST BIT(17) 268 #define B_AX_HAXI_RST_KEEP_REG BIT(16) 269 #define B_AX_RXHCI_EN_V1 BIT(15) 270 #define B_AX_RXBD_MODE_V1 BIT(14) 271 #define B_AX_HAXI_MAX_RXDMA_MASK GENMASK(9, 8) 272 #define B_AX_TXHCI_EN_V1 BIT(7) 273 #define B_AX_FLUSH_AXI_MST BIT(4) 274 #define B_AX_RST_BDRAM BIT(3) 275 #define B_AX_HAXI_MAX_TXDMA_MASK GENMASK(1, 0) 276 277 #define R_AX_HAXI_DMA_STOP1 0x1010 278 #define B_AX_STOP_WPDMA BIT(19) 279 #define B_AX_STOP_CH12 BIT(18) 280 #define B_AX_STOP_CH9 BIT(17) 281 #define B_AX_STOP_CH8 BIT(16) 282 #define B_AX_STOP_ACH7 BIT(15) 283 #define B_AX_STOP_ACH6 BIT(14) 284 #define B_AX_STOP_ACH5 BIT(13) 285 #define B_AX_STOP_ACH4 BIT(12) 286 #define B_AX_STOP_ACH3 BIT(11) 287 #define B_AX_STOP_ACH2 BIT(10) 288 #define B_AX_STOP_ACH1 BIT(9) 289 #define B_AX_STOP_ACH0 BIT(8) 290 291 #define R_AX_HAXI_DMA_BUSY1 0x101C 292 #define B_AX_HAXIIO_BUSY BIT(20) 293 #define B_AX_WPDMA_BUSY BIT(19) 294 #define B_AX_CH12_BUSY BIT(18) 295 #define B_AX_CH9_BUSY BIT(17) 296 #define B_AX_CH8_BUSY BIT(16) 297 #define B_AX_ACH7_BUSY BIT(15) 298 #define B_AX_ACH6_BUSY BIT(14) 299 #define B_AX_ACH5_BUSY BIT(13) 300 #define B_AX_ACH4_BUSY BIT(12) 301 #define B_AX_ACH3_BUSY BIT(11) 302 #define B_AX_ACH2_BUSY BIT(10) 303 #define B_AX_ACH1_BUSY BIT(9) 304 #define B_AX_ACH0_BUSY BIT(8) 305 306 #define R_AX_PCIE_DBG_CTRL 0x11C0 307 #define B_AX_DBG_DUMMY_MASK GENMASK(23, 16) 308 #define B_AX_DBG_SEL_MASK GENMASK(15, 13) 309 #define B_AX_PCIE_DBG_SEL BIT(12) 310 #define B_AX_MRD_TIMEOUT_EN BIT(10) 311 #define B_AX_ASFF_FULL_NO_STK BIT(1) 312 #define B_AX_EN_STUCK_DBG BIT(0) 313 314 #define R_AX_HAXI_DMA_STOP2 0x11C0 315 #define B_AX_STOP_CH11 BIT(1) 316 #define B_AX_STOP_CH10 BIT(0) 317 318 #define R_AX_HAXI_DMA_BUSY2 0x11C8 319 #define B_AX_CH11_BUSY BIT(1) 320 #define B_AX_CH10_BUSY BIT(0) 321 322 #define R_AX_HAXI_DMA_BUSY3 0x1208 323 #define B_AX_RPQ_BUSY BIT(1) 324 #define B_AX_RXQ_BUSY BIT(0) 325 326 #define R_AX_LTR_DEC_CTRL 0x1600 327 #define B_AX_LTR_IDX_DRV_VLD BIT(16) 328 #define B_AX_LTR_CURR_IDX_DRV_MASK GENMASK(15, 14) 329 #define B_AX_LTR_IDX_FW_VLD BIT(13) 330 #define B_AX_LTR_CURR_IDX_FW_MASK GENMASK(12, 11) 331 #define B_AX_LTR_IDX_HW_VLD BIT(10) 332 #define B_AX_LTR_CURR_IDX_HW_MASK GENMASK(9, 8) 333 #define B_AX_LTR_REQ_DRV BIT(7) 334 #define B_AX_LTR_IDX_DRV_MASK GENMASK(6, 5) 335 #define PCIE_LTR_IDX_IDLE 3 336 #define B_AX_LTR_DRV_DEC_EN BIT(4) 337 #define B_AX_LTR_FW_DEC_EN BIT(3) 338 #define B_AX_LTR_HW_DEC_EN BIT(2) 339 #define B_AX_LTR_SPACE_IDX_V1_MASK GENMASK(1, 0) 340 #define LTR_EN_BITS (B_AX_LTR_HW_DEC_EN | B_AX_LTR_FW_DEC_EN | B_AX_LTR_DRV_DEC_EN) 341 342 #define R_AX_LTR_LATENCY_IDX0 0x1604 343 #define R_AX_LTR_LATENCY_IDX1 0x1608 344 #define R_AX_LTR_LATENCY_IDX2 0x160C 345 #define R_AX_LTR_LATENCY_IDX3 0x1610 346 347 #define R_AX_HCI_FC_CTRL_V1 0x1700 348 #define R_AX_CH_PAGE_CTRL_V1 0x1704 349 350 #define R_AX_ACH0_PAGE_CTRL_V1 0x1710 351 #define R_AX_ACH1_PAGE_CTRL_V1 0x1714 352 #define R_AX_ACH2_PAGE_CTRL_V1 0x1718 353 #define R_AX_ACH3_PAGE_CTRL_V1 0x171C 354 #define R_AX_ACH4_PAGE_CTRL_V1 0x1720 355 #define R_AX_ACH5_PAGE_CTRL_V1 0x1724 356 #define R_AX_ACH6_PAGE_CTRL_V1 0x1728 357 #define R_AX_ACH7_PAGE_CTRL_V1 0x172C 358 #define R_AX_CH8_PAGE_CTRL_V1 0x1730 359 #define R_AX_CH9_PAGE_CTRL_V1 0x1734 360 #define R_AX_CH10_PAGE_CTRL_V1 0x1738 361 #define R_AX_CH11_PAGE_CTRL_V1 0x173C 362 363 #define R_AX_ACH0_PAGE_INFO_V1 0x1750 364 #define R_AX_ACH1_PAGE_INFO_V1 0x1754 365 #define R_AX_ACH2_PAGE_INFO_V1 0x1758 366 #define R_AX_ACH3_PAGE_INFO_V1 0x175C 367 #define R_AX_ACH4_PAGE_INFO_V1 0x1760 368 #define R_AX_ACH5_PAGE_INFO_V1 0x1764 369 #define R_AX_ACH6_PAGE_INFO_V1 0x1768 370 #define R_AX_ACH7_PAGE_INFO_V1 0x176C 371 #define R_AX_CH8_PAGE_INFO_V1 0x1770 372 #define R_AX_CH9_PAGE_INFO_V1 0x1774 373 #define R_AX_CH10_PAGE_INFO_V1 0x1778 374 #define R_AX_CH11_PAGE_INFO_V1 0x177C 375 #define R_AX_CH12_PAGE_INFO_V1 0x1780 376 377 #define R_AX_PUB_PAGE_INFO3_V1 0x178C 378 #define R_AX_PUB_PAGE_CTRL1_V1 0x1790 379 #define R_AX_PUB_PAGE_CTRL2_V1 0x1794 380 #define R_AX_PUB_PAGE_INFO1_V1 0x1798 381 #define R_AX_PUB_PAGE_INFO2_V1 0x179C 382 #define R_AX_WP_PAGE_CTRL1_V1 0x17A0 383 #define R_AX_WP_PAGE_CTRL2_V1 0x17A4 384 #define R_AX_WP_PAGE_INFO1_V1 0x17A8 385 386 #define R_AX_H2CREG_DATA0_V1 0x7140 387 #define R_AX_H2CREG_DATA1_V1 0x7144 388 #define R_AX_H2CREG_DATA2_V1 0x7148 389 #define R_AX_H2CREG_DATA3_V1 0x714C 390 #define R_AX_C2HREG_DATA0_V1 0x7150 391 #define R_AX_C2HREG_DATA1_V1 0x7154 392 #define R_AX_C2HREG_DATA2_V1 0x7158 393 #define R_AX_C2HREG_DATA3_V1 0x715C 394 #define R_AX_H2CREG_CTRL_V1 0x7160 395 #define R_AX_C2HREG_CTRL_V1 0x7164 396 397 #define R_AX_HCI_FUNC_EN_V1 0x7880 398 399 #define R_AX_PHYREG_SET 0x8040 400 #define PHYREG_SET_ALL_CYCLE 0x8 401 #define PHYREG_SET_XYN_CYCLE 0xE 402 403 #define R_AX_HD0IMR 0x8110 404 #define B_AX_WDT_PTFM_INT_EN BIT(5) 405 #define B_AX_CPWM_INT_EN BIT(2) 406 #define B_AX_GT3_INT_EN BIT(1) 407 #define B_AX_C2H_INT_EN BIT(0) 408 #define R_AX_HD0ISR 0x8114 409 #define B_AX_C2H_INT BIT(0) 410 411 #define R_AX_H2CREG_DATA0 0x8140 412 #define R_AX_H2CREG_DATA1 0x8144 413 #define R_AX_H2CREG_DATA2 0x8148 414 #define R_AX_H2CREG_DATA3 0x814C 415 #define R_AX_C2HREG_DATA0 0x8150 416 #define R_AX_C2HREG_DATA1 0x8154 417 #define R_AX_C2HREG_DATA2 0x8158 418 #define R_AX_C2HREG_DATA3 0x815C 419 #define R_AX_H2CREG_CTRL 0x8160 420 #define B_AX_H2CREG_TRIGGER BIT(0) 421 #define R_AX_C2HREG_CTRL 0x8164 422 #define B_AX_C2HREG_TRIGGER BIT(0) 423 #define R_AX_CPWM 0x8170 424 425 #define R_AX_HCI_FUNC_EN 0x8380 426 #define B_AX_HCI_RXDMA_EN BIT(1) 427 #define B_AX_HCI_TXDMA_EN BIT(0) 428 429 #define R_AX_BOOT_DBG 0x83F0 430 431 #define R_AX_DMAC_FUNC_EN 0x8400 432 #define B_AX_DMAC_CRPRT BIT(31) 433 #define B_AX_MAC_FUNC_EN BIT(30) 434 #define B_AX_DMAC_FUNC_EN BIT(29) 435 #define B_AX_MPDU_PROC_EN BIT(28) 436 #define B_AX_WD_RLS_EN BIT(27) 437 #define B_AX_DLE_WDE_EN BIT(26) 438 #define B_AX_TXPKT_CTRL_EN BIT(25) 439 #define B_AX_STA_SCH_EN BIT(24) 440 #define B_AX_DLE_PLE_EN BIT(23) 441 #define B_AX_PKT_BUF_EN BIT(22) 442 #define B_AX_DMAC_TBL_EN BIT(21) 443 #define B_AX_PKT_IN_EN BIT(20) 444 #define B_AX_DLE_CPUIO_EN BIT(19) 445 #define B_AX_DISPATCHER_EN BIT(18) 446 #define B_AX_BBRPT_EN BIT(17) 447 #define B_AX_MAC_SEC_EN BIT(16) 448 #define B_AX_MAC_UN_EN BIT(15) 449 #define B_AX_H_AXIDMA_EN BIT(14) 450 451 #define R_AX_DMAC_CLK_EN 0x8404 452 #define B_AX_WD_RLS_CLK_EN BIT(27) 453 #define B_AX_DLE_WDE_CLK_EN BIT(26) 454 #define B_AX_TXPKT_CTRL_CLK_EN BIT(25) 455 #define B_AX_STA_SCH_CLK_EN BIT(24) 456 #define B_AX_DLE_PLE_CLK_EN BIT(23) 457 #define B_AX_PKT_IN_CLK_EN BIT(20) 458 #define B_AX_DLE_CPUIO_CLK_EN BIT(19) 459 #define B_AX_DISPATCHER_CLK_EN BIT(18) 460 #define B_AX_BBRPT_CLK_EN BIT(17) 461 #define B_AX_MAC_SEC_CLK_EN BIT(16) 462 463 #define PCI_LTR_IDLE_TIMER_1US 0 464 #define PCI_LTR_IDLE_TIMER_10US 1 465 #define PCI_LTR_IDLE_TIMER_100US 2 466 #define PCI_LTR_IDLE_TIMER_200US 3 467 #define PCI_LTR_IDLE_TIMER_400US 4 468 #define PCI_LTR_IDLE_TIMER_800US 5 469 #define PCI_LTR_IDLE_TIMER_1_6MS 6 470 #define PCI_LTR_IDLE_TIMER_3_2MS 7 471 #define PCI_LTR_IDLE_TIMER_R_ERR 0xFD 472 #define PCI_LTR_IDLE_TIMER_DEF 0xFE 473 #define PCI_LTR_IDLE_TIMER_IGNORE 0xFF 474 475 #define PCI_LTR_SPC_10US 0 476 #define PCI_LTR_SPC_100US 1 477 #define PCI_LTR_SPC_500US 2 478 #define PCI_LTR_SPC_1MS 3 479 #define PCI_LTR_SPC_R_ERR 0xFD 480 #define PCI_LTR_SPC_DEF 0xFE 481 #define PCI_LTR_SPC_IGNORE 0xFF 482 483 #define R_AX_LTR_CTRL_0 0x8410 484 #define B_AX_LTR_SPACE_IDX_MASK GENMASK(13, 12) 485 #define B_AX_LTR_IDLE_TIMER_IDX_MASK GENMASK(10, 8) 486 #define B_AX_LTR_WD_NOEMP_CHK BIT(6) 487 #define B_AX_APP_LTR_ACT BIT(5) 488 #define B_AX_APP_LTR_IDLE BIT(4) 489 #define B_AX_LTR_EN BIT(1) 490 #define B_AX_LTR_WD_NOEMP_CHK_V1 BIT(1) 491 #define B_AX_LTR_HW_EN BIT(0) 492 493 #define R_AX_LTR_CTRL_1 0x8414 494 #define B_AX_LTR_RX1_TH_MASK GENMASK(27, 16) 495 #define B_AX_LTR_RX0_TH_MASK GENMASK(11, 0) 496 497 #define R_AX_LTR_IDLE_LATENCY 0x8418 498 499 #define R_AX_LTR_ACTIVE_LATENCY 0x841C 500 501 #define R_AX_SER_DBG_INFO 0x8424 502 #define B_AX_L0_TO_L1_EVENT_MASK GENMASK(31, 28) 503 504 #define R_AX_DLE_EMPTY0 0x8430 505 #define B_AX_PLE_EMPTY_QTA_DMAC_CPUIO BIT(26) 506 #define B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX BIT(25) 507 #define B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU BIT(24) 508 #define B_AX_PLE_EMPTY_QTA_DMAC_H2C BIT(23) 509 #define B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL BIT(22) 510 #define B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL BIT(21) 511 #define B_AX_WDE_EMPTY_QTA_DMAC_CPUIO BIT(20) 512 #define B_AX_WDE_EMPTY_QTA_DMAC_PKTIN BIT(19) 513 #define B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU BIT(18) 514 #define B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU BIT(17) 515 #define B_AX_WDE_EMPTY_QTA_DMAC_HIF BIT(16) 516 #define B_AX_WDE_EMPTY_QUE_DMAC_PKTIN BIT(10) 517 #define B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX BIT(9) 518 #define B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX BIT(8) 519 #define B_AX_WDE_EMPTY_QUE_OTHERS BIT(7) 520 #define B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 BIT(4) 521 #define B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 BIT(3) 522 #define B_AX_WDE_EMPTY_QUE_CMAC1_MBH BIT(2) 523 #define B_AX_WDE_EMPTY_QUE_CMAC0_MBH BIT(1) 524 #define B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC BIT(0) 525 526 #define R_AX_DMAC_ERR_IMR 0x8520 527 #define B_AX_DLE_CPUIO_ERR_INT_EN BIT(10) 528 #define B_AX_APB_BRIDGE_ERR_INT_EN BIT(9) 529 #define B_AX_DISPATCH_ERR_INT_EN BIT(8) 530 #define B_AX_PKTIN_ERR_INT_EN BIT(7) 531 #define B_AX_PLE_DLE_ERR_INT_EN BIT(6) 532 #define B_AX_TXPKTCTRL_ERR_INT_EN BIT(5) 533 #define B_AX_WDE_DLE_ERR_INT_EN BIT(4) 534 #define B_AX_STA_SCHEDULER_ERR_INT_EN BIT(3) 535 #define B_AX_MPDU_ERR_INT_EN BIT(2) 536 #define B_AX_WSEC_ERR_INT_EN BIT(1) 537 #define B_AX_WDRLS_ERR_INT_EN BIT(0) 538 #define DMAC_ERR_IMR_EN GENMASK(31, 0) 539 #define DMAC_ERR_IMR_DIS 0 540 541 #define R_AX_DMAC_ERR_ISR 0x8524 542 #define B_AX_DLE_CPUIO_ERR_FLAG BIT(10) 543 #define B_AX_APB_BRIDGE_ERR_FLAG BIT(9) 544 #define B_AX_DISPATCH_ERR_FLAG BIT(8) 545 #define B_AX_PKTIN_ERR_FLAG BIT(7) 546 #define B_AX_PLE_DLE_ERR_FLAG BIT(6) 547 #define B_AX_TXPKTCTRL_ERR_FLAG BIT(5) 548 #define B_AX_WDE_DLE_ERR_FLAG BIT(4) 549 #define B_AX_STA_SCHEDULER_ERR_FLAG BIT(3) 550 #define B_AX_MPDU_ERR_FLAG BIT(2) 551 #define B_AX_WSEC_ERR_FLAG BIT(1) 552 #define B_AX_WDRLS_ERR_FLAG BIT(0) 553 554 #define R_AX_DISPATCHER_GLOBAL_SETTING_0 0x8800 555 #define B_AX_PL_PAGE_128B_SEL BIT(9) 556 #define B_AX_WD_PAGE_64B_SEL BIT(8) 557 #define R_AX_OTHER_DISPATCHER_ERR_ISR 0x8804 558 #define R_AX_HOST_DISPATCHER_ERR_ISR 0x8808 559 #define R_AX_CPU_DISPATCHER_ERR_ISR 0x880C 560 #define R_AX_TX_ADDRESS_INFO_MODE_SETTING 0x8810 561 #define B_AX_HOST_ADDR_INFO_8B_SEL BIT(0) 562 563 #define R_AX_HOST_DISPATCHER_ERR_IMR 0x8850 564 #define B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN BIT(31) 565 #define B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN BIT(30) 566 #define B_AX_HDT_CHKSUM_FSM_ERR_INT_EN BIT(29) 567 #define B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN BIT(28) 568 #define B_AX_HDT_DMA_PROCESS_ERR_INT_EN BIT(27) 569 #define B_AX_HDT_TOTAL_LEN_ERR_INT_EN BIT(26) 570 #define B_AX_HDT_SHIFT_EN_ERR_INT_EN BIT(25) 571 #define B_AX_HDT_RXAGG_CFG_ERR_INT_EN BIT(24) 572 #define B_AX_HDT_OUTPUT_ERR_INT_EN BIT(21) 573 #define B_AX_HDT_RES_ERR_INT_EN BIT(20) 574 #define B_AX_HDT_BURST_NUM_ERR_INT_EN BIT(19) 575 #define B_AX_HDT_NULLPKT_ERR_INT_EN BIT(18) 576 #define B_AX_HDT_FLOW_CTRL_ERR_INT_EN BIT(17) 577 #define B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN BIT(16) 578 #define B_AX_HDT_PLD_CMD_OVERLOW_INT_EN BIT(15) 579 #define B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN BIT(14) 580 #define B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN BIT(13) 581 #define B_AX_HDT_TCP_CHK_ERR_INT_EN BIT(12) 582 #define B_AX_HDT_TXPKTSIZE_ERR_INT_EN BIT(11) 583 #define B_AX_HDT_PRE_COST_ERR_INT_EN BIT(10) 584 #define B_AX_HDT_WD_CHK_ERR_INT_EN BIT(9) 585 #define B_AX_HDT_CHANNEL_DMA_ERR_INT_EN BIT(8) 586 #define B_AX_HDT_OFFSET_UNMATCH_INT_EN BIT(7) 587 #define B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN BIT(6) 588 #define B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN BIT(5) 589 #define B_AX_HDT_PERMU_UNDERFLOW_INT_EN BIT(4) 590 #define B_AX_HDT_PERMU_OVERFLOW_INT_EN BIT(3) 591 #define B_AX_HDT_PKT_FAIL_DBG_INT_EN BIT(2) 592 #define B_AX_HDT_CHANNEL_ID_ERR_INT_EN BIT(1) 593 #define B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN BIT(0) 594 #define B_AX_HOST_DISP_IMR_CLR (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \ 595 B_AX_HDT_CHANNEL_ID_ERR_INT_EN | \ 596 B_AX_HDT_PKT_FAIL_DBG_INT_EN | \ 597 B_AX_HDT_PERMU_OVERFLOW_INT_EN | \ 598 B_AX_HDT_PERMU_UNDERFLOW_INT_EN | \ 599 B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \ 600 B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \ 601 B_AX_HDT_OFFSET_UNMATCH_INT_EN | \ 602 B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \ 603 B_AX_HDT_WD_CHK_ERR_INT_EN | \ 604 B_AX_HDT_PRE_COST_ERR_INT_EN | \ 605 B_AX_HDT_TXPKTSIZE_ERR_INT_EN | \ 606 B_AX_HDT_TCP_CHK_ERR_INT_EN | \ 607 B_AX_HDT_TX_WRITE_OVERFLOW_INT_EN | \ 608 B_AX_HDT_TX_WRITE_UNDERFLOW_INT_EN | \ 609 B_AX_HDT_PLD_CMD_OVERLOW_INT_EN | \ 610 B_AX_HDT_PLD_CMD_UNDERFLOW_INT_EN | \ 611 B_AX_HDT_FLOW_CTRL_ERR_INT_EN | \ 612 B_AX_HDT_NULLPKT_ERR_INT_EN | \ 613 B_AX_HDT_BURST_NUM_ERR_INT_EN | \ 614 B_AX_HDT_RXAGG_CFG_ERR_INT_EN | \ 615 B_AX_HDT_SHIFT_EN_ERR_INT_EN | \ 616 B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \ 617 B_AX_HDT_DMA_PROCESS_ERR_INT_EN | \ 618 B_AX_HDT_SHIFT_DMA_CFG_ERR_INT_EN | \ 619 B_AX_HDT_CHKSUM_FSM_ERR_INT_EN | \ 620 B_AX_HDT_RX_WRITE_OVERFLOW_INT_EN | \ 621 B_AX_HDT_RX_WRITE_UNDERFLOW_INT_EN) 622 #define B_AX_HOST_DISP_IMR_SET (B_AX_HDT_CHANNEL_DIFF_ERR_INT_EN | \ 623 B_AX_HDT_PAYLOAD_OVERFLOW_INT_EN | \ 624 B_AX_HDT_PAYLOAD_UNDERFLOW_INT_EN | \ 625 B_AX_HDT_CHANNEL_DMA_ERR_INT_EN | \ 626 B_AX_HDT_TOTAL_LEN_ERR_INT_EN | \ 627 B_AX_HDT_DMA_PROCESS_ERR_INT_EN) 628 629 #define B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN BIT(31) 630 #define B_AX_HR_WRFF_OVERFLOW_ERR_INT_EN BIT(30) 631 #define B_AX_HR_CHKSUM_FSM_ERR_INT_EN BIT(29) 632 #define B_AX_HR_SHIFT_DMA_CFG_ERR_INT_EN BIT(28) 633 #define B_AX_HR_DMA_PROCESS_ERR_INT_EN BIT(27) 634 #define B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(26) 635 #define B_AX_HR_SHIFT_EN_ERR_INT_EN BIT(25) 636 #define B_AX_HR_AGG_CFG_ERR_INT_EN BIT(24) 637 #define B_AX_HR_DMA_RD_CNT_DEQ_ERR_INT_EN BIT(23) 638 #define B_AX_HR_PLD_LEN_ZERO_ERR_INT_EN BIT(22) 639 #define B_AX_HT_ILL_CH_ERR_INT_EN BIT(20) 640 #define B_AX_HT_ADDR_INFO_LEN_ERR_INT_EN BIT(18) 641 #define B_AX_HT_WD_LEN_OVER_ERR_INT_EN BIT(17) 642 #define B_AX_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(16) 643 #define B_AX_HT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(15) 644 #define B_AX_HT_WRFF_UNDERFLOW_ERR_INT_EN BIT(14) 645 #define B_AX_HT_WRFF_OVERFLOW_ERR_INT_EN BIT(13) 646 #define B_AX_HT_CHKSUM_FSM_ERR_INT_EN BIT(12) 647 #define B_AX_HT_TXPKTSIZE_ERR_INT_EN BIT(11) 648 #define B_AX_HT_PRE_SUB_ERR_INT_EN BIT(10) 649 #define B_AX_HT_WD_CHKSUM_ERR_INT_EN BIT(9) 650 #define B_AX_HT_CHANNEL_DMA_ERR_INT_EN BIT(8) 651 #define B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN BIT(7) 652 #define B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN BIT(6) 653 #define B_AX_HT_PAYLOAD_OVER_ERR_INT_EN BIT(5) 654 #define B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4) 655 #define B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3) 656 #define B_AX_HT_PKT_FAIL_ERR_INT_EN BIT(2) 657 #define B_AX_HT_CH_ID_ERR_INT_EN BIT(1) 658 #define B_AX_HT_EP_CH_DIFF_ERR_INT_EN BIT(0) 659 #define B_AX_HOST_DISP_IMR_CLR_V1 (B_AX_HT_EP_CH_DIFF_ERR_INT_EN | \ 660 B_AX_HT_CH_ID_ERR_INT_EN | \ 661 B_AX_HT_PKT_FAIL_ERR_INT_EN | \ 662 B_AX_HT_PERMU_FF_OVERFLOW_ERR_INT_EN | \ 663 B_AX_HT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \ 664 B_AX_HT_PAYLOAD_OVER_ERR_INT_EN | \ 665 B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN | \ 666 B_AX_HT_OFFSET_UNMATCH_ERR_INT_EN | \ 667 B_AX_HT_CHANNEL_DMA_ERR_INT_EN | \ 668 B_AX_HT_WD_CHKSUM_ERR_INT_EN | \ 669 B_AX_HT_PRE_SUB_ERR_INT_EN | \ 670 B_AX_HT_TXPKTSIZE_ERR_INT_EN | \ 671 B_AX_HT_CHKSUM_FSM_ERR_INT_EN | \ 672 B_AX_HT_WRFF_OVERFLOW_ERR_INT_EN | \ 673 B_AX_HT_WRFF_UNDERFLOW_ERR_INT_EN | \ 674 B_AX_HT_PLD_CMD_OVERFLOW_ERR_INT_EN | \ 675 B_AX_HT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \ 676 B_AX_HT_WD_LEN_OVER_ERR_INT_EN | \ 677 B_AX_HT_ADDR_INFO_LEN_ERR_INT_EN | \ 678 B_AX_HT_ILL_CH_ERR_INT_EN | \ 679 B_AX_HR_PLD_LEN_ZERO_ERR_INT_EN | \ 680 B_AX_HR_DMA_RD_CNT_DEQ_ERR_INT_EN | \ 681 B_AX_HR_AGG_CFG_ERR_INT_EN | \ 682 B_AX_HR_SHIFT_EN_ERR_INT_EN | \ 683 B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \ 684 B_AX_HR_DMA_PROCESS_ERR_INT_EN | \ 685 B_AX_HR_SHIFT_DMA_CFG_ERR_INT_EN | \ 686 B_AX_HR_CHKSUM_FSM_ERR_INT_EN | \ 687 B_AX_HR_WRFF_OVERFLOW_ERR_INT_EN | \ 688 B_AX_HR_WRFF_UNDERFLOW_ERR_INT_EN) 689 #define B_AX_HOST_DISP_IMR_SET_V1 (B_AX_HT_PAYLOAD_OVER_ERR_INT_EN | \ 690 B_AX_HT_PAYLOAD_UNDER_ERR_INT_EN | \ 691 B_AX_HT_ILL_CH_ERR_INT_EN | \ 692 B_AX_HR_TOTAL_LEN_UNDER_ERR_INT_EN | \ 693 B_AX_HR_DMA_PROCESS_ERR_INT_EN) 694 695 #define R_AX_CPU_DISPATCHER_ERR_IMR 0x8854 696 #define B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN BIT(31) 697 #define B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN BIT(30) 698 #define B_AX_CPU_CHKSUM_FSM_ERR_INT_EN BIT(29) 699 #define B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN BIT(28) 700 #define B_AX_CPU_DMA_PROCESS_ERR_INT_EN BIT(27) 701 #define B_AX_CPU_TOTAL_LEN_ERR_INT_EN BIT(26) 702 #define B_AX_CPU_SHIFT_EN_ERR_INT_EN BIT(25) 703 #define B_AX_CPU_RXAGG_CFG_ERR_INT_EN BIT(24) 704 #define B_AX_CPU_OUTPUT_ERR_INT_EN BIT(20) 705 #define B_AX_CPU_RESP_ERR_INT_EN BIT(19) 706 #define B_AX_CPU_BURST_NUM_ERR_INT_EN BIT(18) 707 #define B_AX_CPU_NULLPKT_ERR_INT_EN BIT(17) 708 #define B_AX_CPU_FLOW_CTRL_ERR_INT_EN BIT(16) 709 #define B_AX_CPU_F2P_SEQ_ERR_INT_EN BIT(15) 710 #define B_AX_CPU_F2P_QSEL_ERR_INT_EN BIT(14) 711 #define B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN BIT(13) 712 #define B_AX_CPU_PLD_CMD_OVERLOW_INT_EN BIT(12) 713 #define B_AX_CPU_PRE_COST_ERR_INT_EN BIT(11) 714 #define B_AX_CPU_WD_CHK_ERR_INT_EN BIT(10) 715 #define B_AX_CPU_CHANNEL_DMA_ERR_INT_EN BIT(9) 716 #define B_AX_CPU_OFFSET_UNMATCH_INT_EN BIT(8) 717 #define B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7) 718 #define B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN BIT(6) 719 #define B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN BIT(5) 720 #define B_AX_CPU_PERMU_UNDERFLOW_INT_EN BIT(4) 721 #define B_AX_CPU_PERMU_OVERFLOW_INT_EN BIT(3) 722 #define B_AX_CPU_CHANNEL_ID_ERR_INT_EN BIT(2) 723 #define B_AX_CPU_PKT_FAIL_DBG_INT_EN BIT(1) 724 #define B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN BIT(0) 725 #define B_AX_CPU_DISP_IMR_CLR (B_AX_CPU_CHANNEL_DIFF_ERR_INT_EN | \ 726 B_AX_CPU_PKT_FAIL_DBG_INT_EN | \ 727 B_AX_CPU_CHANNEL_ID_ERR_INT_EN | \ 728 B_AX_CPU_PERMU_OVERFLOW_INT_EN | \ 729 B_AX_CPU_PERMU_UNDERFLOW_INT_EN | \ 730 B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | \ 731 B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | \ 732 B_AX_CPU_PAYLOAD_CHKSUM_ERR_INT_EN | \ 733 B_AX_CPU_OFFSET_UNMATCH_INT_EN | \ 734 B_AX_CPU_CHANNEL_DMA_ERR_INT_EN | \ 735 B_AX_CPU_WD_CHK_ERR_INT_EN | \ 736 B_AX_CPU_PRE_COST_ERR_INT_EN | \ 737 B_AX_CPU_PLD_CMD_OVERLOW_INT_EN | \ 738 B_AX_CPU_PLD_CMD_UNDERFLOW_INT_EN | \ 739 B_AX_CPU_F2P_QSEL_ERR_INT_EN | \ 740 B_AX_CPU_F2P_SEQ_ERR_INT_EN | \ 741 B_AX_CPU_FLOW_CTRL_ERR_INT_EN | \ 742 B_AX_CPU_NULLPKT_ERR_INT_EN | \ 743 B_AX_CPU_BURST_NUM_ERR_INT_EN | \ 744 B_AX_CPU_RXAGG_CFG_ERR_INT_EN | \ 745 B_AX_CPU_SHIFT_EN_ERR_INT_EN | \ 746 B_AX_CPU_TOTAL_LEN_ERR_INT_EN | \ 747 B_AX_CPU_DMA_PROCESS_ERR_INT_EN | \ 748 B_AX_CPU_SHIFT_DMA_CFG_ERR_INT_EN | \ 749 B_AX_CPU_CHKSUM_FSM_ERR_INT_EN | \ 750 B_AX_CPU_RX_WRITE_OVERFLOW_INT_EN | \ 751 B_AX_CPU_RX_WRITE_UNDERFLOW_INT_EN) 752 #define B_AX_CPU_DISP_IMR_SET (B_AX_CPU_PKT_FAIL_DBG_INT_EN | \ 753 B_AX_CPU_PAYLOAD_OVERFLOW_INT_EN | \ 754 B_AX_CPU_PAYLOAD_UNDERFLOW_INT_EN | \ 755 B_AX_CPU_TOTAL_LEN_ERR_INT_EN) 756 757 #define B_AX_CR_PLD_LEN_ERR_INT_EN BIT(30) 758 #define B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN BIT(29) 759 #define B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN BIT(28) 760 #define B_AX_CR_SHIFT_DMA_CFG_ERR_INT_EN BIT(27) 761 #define B_AX_CR_DMA_PROCESS_ERR_INT_EN BIT(26) 762 #define B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN BIT(25) 763 #define B_AX_CR_SHIFT_EN_ERR_INT_EN BIT(24) 764 #define B_AX_REUSE_FIFO_B_UNDER_ERR_INT_EN BIT(22) 765 #define B_AX_REUSE_FIFO_B_OVER_ERR_INT_EN BIT(21) 766 #define B_AX_REUSE_FIFO_A_UNDER_ERR_INT_EN BIT(20) 767 #define B_AX_REUSE_FIFO_A_OVER_ERR_INT_EN BIT(19) 768 #define B_AX_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN BIT(17) 769 #define B_AX_CT_WD_LEN_OVER_ERR_INT_EN BIT(16) 770 #define B_AX_CT_F2P_SEQ_ERR_INT_EN BIT(15) 771 #define B_AX_CT_F2P_QSEL_ERR_INT_EN BIT(14) 772 #define B_AX_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN BIT(13) 773 #define B_AX_CT_PLD_CMD_OVERFLOW_ERR_INT_EN BIT(12) 774 #define B_AX_CT_PRE_SUB_ERR_INT_EN BIT(11) 775 #define B_AX_CT_WD_CHKSUM_ERR_INT_EN BIT(10) 776 #define B_AX_CT_CHANNEL_DMA_ERR_INT_EN BIT(9) 777 #define B_AX_CT_OFFSET_UNMATCH_ERR_INT_EN BIT(8) 778 #define B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN BIT(7) 779 #define B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN BIT(6) 780 #define B_AX_CT_PAYLOAD_OVER_ERR_INT_EN BIT(5) 781 #define B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN BIT(4) 782 #define B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN BIT(3) 783 #define B_AX_CT_CH_ID_ERR_INT_EN BIT(2) 784 #define B_AX_CT_EP_CH_DIFF_ERR_INT_EN BIT(0) 785 #define B_AX_CPU_DISP_IMR_CLR_V1 (B_AX_CT_EP_CH_DIFF_ERR_INT_EN | \ 786 B_AX_CT_CH_ID_ERR_INT_EN | \ 787 B_AX_CT_PERMU_FF_OVERFLOW_ERR_INT_EN | \ 788 B_AX_CT_PERMU_FF_UNDERFLOW_ERR_INT_EN | \ 789 B_AX_CT_PAYLOAD_OVER_ERR_INT_EN | \ 790 B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN | \ 791 B_AX_CT_PAYLOAD_CHKSUM_ERR_INT_EN | \ 792 B_AX_CT_OFFSET_UNMATCH_ERR_INT_EN | \ 793 B_AX_CT_CHANNEL_DMA_ERR_INT_EN | \ 794 B_AX_CT_WD_CHKSUM_ERR_INT_EN | \ 795 B_AX_CT_PRE_SUB_ERR_INT_EN | \ 796 B_AX_CT_PLD_CMD_OVERFLOW_ERR_INT_EN | \ 797 B_AX_CT_PLD_CMD_UNDERFLOW_ERR_INT_EN | \ 798 B_AX_CT_F2P_QSEL_ERR_INT_EN | \ 799 B_AX_CT_F2P_SEQ_ERR_INT_EN | \ 800 B_AX_CT_WD_LEN_OVER_ERR_INT_EN | \ 801 B_AX_CT_ADDR_INFO_LEN_MISS_ERR_INT_EN | \ 802 B_AX_REUSE_FIFO_A_OVER_ERR_INT_EN | \ 803 B_AX_REUSE_FIFO_A_UNDER_ERR_INT_EN | \ 804 B_AX_REUSE_FIFO_B_OVER_ERR_INT_EN | \ 805 B_AX_REUSE_FIFO_B_UNDER_ERR_INT_EN | \ 806 B_AX_CR_SHIFT_EN_ERR_INT_EN | \ 807 B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN | \ 808 B_AX_CR_DMA_PROCESS_ERR_INT_EN | \ 809 B_AX_CR_SHIFT_DMA_CFG_ERR_INT_EN | \ 810 B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN | \ 811 B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN | \ 812 B_AX_CR_PLD_LEN_ERR_INT_EN) 813 #define B_AX_CPU_DISP_IMR_SET_V1 (B_AX_CT_PAYLOAD_OVER_ERR_INT_EN | \ 814 B_AX_CT_PAYLOAD_UNDER_ERR_INT_EN | \ 815 B_AX_CR_TOTAL_LEN_UNDER_ERR_INT_EN | \ 816 B_AX_CR_DMA_PROCESS_ERR_INT_EN | \ 817 B_AX_CR_WRFF_OVERFLOW_ERR_INT_EN | \ 818 B_AX_CR_WRFF_UNDERFLOW_ERR_INT_EN) 819 820 #define R_AX_OTHER_DISPATCHER_ERR_IMR 0x8858 821 #define B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN BIT(29) 822 #define B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN BIT(28) 823 #define B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN BIT(27) 824 #define B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN BIT(26) 825 #define B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN BIT(25) 826 #define B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN BIT(24) 827 #define B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(17) 828 #define B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN BIT(16) 829 #define B_AX_PLE_OUTPUT_ERR_INT_EN BIT(12) 830 #define B_AX_PLE_RESP_ERR_INT_EN BIT(11) 831 #define B_AX_PLE_BURST_NUM_ERR_INT_EN BIT(10) 832 #define B_AX_PLE_NULL_PKT_ERR_INT_EN BIT(9) 833 #define B_AX_PLE_FLOW_CTRL_ERR_INT_EN BIT(8) 834 #define B_AX_WDE_OUTPUT_ERR_INT_EN BIT(4) 835 #define B_AX_WDE_RESP_ERR_INT_EN BIT(3) 836 #define B_AX_WDE_BURST_NUM_ERR_INT_EN BIT(2) 837 #define B_AX_WDE_NULL_PKT_ERR_INT_EN BIT(1) 838 #define B_AX_WDE_FLOW_CTRL_ERR_INT_EN BIT(0) 839 #define B_AX_OTHER_DISP_IMR_CLR (B_AX_OTHER_STF_WROQT_UNDERFLOW_INT_EN | \ 840 B_AX_OTHER_STF_WROQT_OVERFLOW_INT_EN | \ 841 B_AX_OTHER_STF_WRFF_UNDERFLOW_INT_EN | \ 842 B_AX_OTHER_STF_WRFF_OVERFLOW_INT_EN | \ 843 B_AX_OTHER_STF_CMD_UNDERFLOW_INT_EN | \ 844 B_AX_OTHER_STF_CMD_OVERFLOW_INT_EN | \ 845 B_AX_HOST_ADDR_INFO_LEN_ZERO_ERR_INT_EN | \ 846 B_AX_CPU_ADDR_INFO_LEN_ZERO_ERR_INT_EN | \ 847 B_AX_PLE_OUTPUT_ERR_INT_EN | \ 848 B_AX_PLE_RESP_ERR_INT_EN | \ 849 B_AX_PLE_BURST_NUM_ERR_INT_EN | \ 850 B_AX_PLE_NULL_PKT_ERR_INT_EN | \ 851 B_AX_PLE_FLOW_CTRL_ERR_INT_EN | \ 852 B_AX_WDE_OUTPUT_ERR_INT_EN | \ 853 B_AX_WDE_RESP_ERR_INT_EN | \ 854 B_AX_WDE_BURST_NUM_ERR_INT_EN | \ 855 B_AX_WDE_NULL_PKT_ERR_INT_EN | \ 856 B_AX_WDE_FLOW_CTRL_ERR_INT_EN) 857 858 #define B_AX_REUSE_SIZE_ERR_INT_EN BIT(31) 859 #define B_AX_REUSE_EN_ERR_INT_EN BIT(30) 860 #define B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN BIT(29) 861 #define B_AX_STF_OQT_OVERFLOW_ERR_INT_EN BIT(28) 862 #define B_AX_STF_WRFF_UNDERFLOW_ERR_INT_EN BIT(27) 863 #define B_AX_STF_WRFF_OVERFLOW_ERR_INT_EN BIT(26) 864 #define B_AX_STF_CMD_UNDERFLOW_ERR_INT_EN BIT(25) 865 #define B_AX_STF_CMD_OVERFLOW_ERR_INT_EN BIT(24) 866 #define B_AX_REUSE_SIZE_ZERO_ERR_INT_EN BIT(23) 867 #define B_AX_REUSE_PKT_CNT_ERR_INT_EN BIT(22) 868 #define B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN BIT(21) 869 #define B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN BIT(20) 870 #define B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN BIT(19) 871 #define B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN BIT(18) 872 #define B_AX_CDT_ADDR_INFO_LEN_ERR_INT_EN BIT(17) 873 #define B_AX_HDT_ADDR_INFO_LEN_ERR_INT_EN BIT(16) 874 #define B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN BIT(15) 875 #define B_AX_CDR_RX_TIMEOUT_ERR_INT_EN BIT(14) 876 #define B_AX_PLE_RESPOSE_ERR_INT_EN BIT(11) 877 #define B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN BIT(7) 878 #define B_AX_HDR_RX_TIMEOUT_ERR_INT_EN BIT(6) 879 #define B_AX_WDE_RESPONSE_ERR_INT_EN BIT(3) 880 #define B_AX_OTHER_DISP_IMR_CLR_V1 (B_AX_CT_EP_CH_DIFF_ERR_INT_EN | \ 881 B_AX_WDE_FLOW_CTRL_ERR_INT_EN | \ 882 B_AX_WDE_NULL_PKT_ERR_INT_EN | \ 883 B_AX_WDE_BURST_NUM_ERR_INT_EN | \ 884 B_AX_WDE_RESPONSE_ERR_INT_EN | \ 885 B_AX_WDE_OUTPUT_ERR_INT_EN | \ 886 B_AX_HDR_RX_TIMEOUT_ERR_INT_EN | \ 887 B_AX_HDR_DMA_TIMEOUT_ERR_INT_EN | \ 888 B_AX_PLE_FLOW_CTRL_ERR_INT_EN | \ 889 B_AX_PLE_NULL_PKT_ERR_INT_EN | \ 890 B_AX_PLE_BURST_NUM_ERR_INT_EN | \ 891 B_AX_PLE_RESPOSE_ERR_INT_EN | \ 892 B_AX_PLE_OUTPUT_ERR_INT_EN | \ 893 B_AX_CDR_RX_TIMEOUT_ERR_INT_EN | \ 894 B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN | \ 895 B_AX_HDT_ADDR_INFO_LEN_ERR_INT_EN | \ 896 B_AX_CDT_ADDR_INFO_LEN_ERR_INT_EN | \ 897 B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN | \ 898 B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN | \ 899 B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN | \ 900 B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN | \ 901 B_AX_REUSE_PKT_CNT_ERR_INT_EN | \ 902 B_AX_REUSE_SIZE_ZERO_ERR_INT_EN | \ 903 B_AX_STF_CMD_OVERFLOW_ERR_INT_EN | \ 904 B_AX_STF_CMD_UNDERFLOW_ERR_INT_EN | \ 905 B_AX_STF_WRFF_OVERFLOW_ERR_INT_EN | \ 906 B_AX_STF_WRFF_UNDERFLOW_ERR_INT_EN | \ 907 B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \ 908 B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN | \ 909 B_AX_REUSE_EN_ERR_INT_EN | \ 910 B_AX_REUSE_SIZE_ERR_INT_EN) 911 #define B_AX_OTHER_DISP_IMR_SET_V1 (B_AX_CDR_RX_TIMEOUT_ERR_INT_EN | \ 912 B_AX_CDR_DMA_TIMEOUT_ERR_INT_EN | \ 913 B_AX_HDT_HCI_TIMEOUT_ERR_INT_EN | \ 914 B_AX_HDT_PTR_TIMEOUT_ERR_INT_EN | \ 915 B_AX_CDT_HCI_TIMEOUT_ERR_INT_EN | \ 916 B_AX_CDT_PTR_TIMEOUT_ERR_INT_EN | \ 917 B_AX_STF_OQT_OVERFLOW_ERR_INT_EN | \ 918 B_AX_STF_OQT_UNDERFLOW_ERR_INT_EN) 919 920 #define R_AX_HCI_FC_CTRL 0x8A00 921 #define B_AX_HCI_FC_CH12_FULL_COND_MASK GENMASK(11, 10) 922 #define B_AX_HCI_FC_WP_CH811_FULL_COND_MASK GENMASK(9, 8) 923 #define B_AX_HCI_FC_WP_CH07_FULL_COND_MASK GENMASK(7, 6) 924 #define B_AX_HCI_FC_WD_FULL_COND_MASK GENMASK(5, 4) 925 #define B_AX_HCI_FC_CH12_EN BIT(3) 926 #define B_AX_HCI_FC_MODE_MASK GENMASK(2, 1) 927 #define B_AX_HCI_FC_EN BIT(0) 928 929 #define R_AX_CH_PAGE_CTRL 0x8A04 930 #define B_AX_PREC_PAGE_CH12_MASK GENMASK(24, 16) 931 #define B_AX_PREC_PAGE_CH011_MASK GENMASK(8, 0) 932 933 #define B_AX_MAX_PG_MASK GENMASK(28, 16) 934 #define B_AX_MIN_PG_MASK GENMASK(12, 0) 935 #define B_AX_GRP BIT(31) 936 #define R_AX_ACH0_PAGE_CTRL 0x8A10 937 #define R_AX_ACH1_PAGE_CTRL 0x8A14 938 #define R_AX_ACH2_PAGE_CTRL 0x8A18 939 #define R_AX_ACH3_PAGE_CTRL 0x8A1C 940 #define R_AX_ACH4_PAGE_CTRL 0x8A20 941 #define R_AX_ACH5_PAGE_CTRL 0x8A24 942 #define R_AX_ACH6_PAGE_CTRL 0x8A28 943 #define R_AX_ACH7_PAGE_CTRL 0x8A2C 944 #define R_AX_CH8_PAGE_CTRL 0x8A30 945 #define R_AX_CH9_PAGE_CTRL 0x8A34 946 #define R_AX_CH10_PAGE_CTRL 0x8A38 947 #define R_AX_CH11_PAGE_CTRL 0x8A3C 948 949 #define B_AX_AVAL_PG_MASK GENMASK(27, 16) 950 #define B_AX_USE_PG_MASK GENMASK(12, 0) 951 #define R_AX_ACH0_PAGE_INFO 0x8A50 952 #define R_AX_ACH1_PAGE_INFO 0x8A54 953 #define R_AX_ACH2_PAGE_INFO 0x8A58 954 #define R_AX_ACH3_PAGE_INFO 0x8A5C 955 #define R_AX_ACH4_PAGE_INFO 0x8A60 956 #define R_AX_ACH5_PAGE_INFO 0x8A64 957 #define R_AX_ACH6_PAGE_INFO 0x8A68 958 #define R_AX_ACH7_PAGE_INFO 0x8A6C 959 #define R_AX_CH8_PAGE_INFO 0x8A70 960 #define R_AX_CH9_PAGE_INFO 0x8A74 961 #define R_AX_CH10_PAGE_INFO 0x8A78 962 #define R_AX_CH11_PAGE_INFO 0x8A7C 963 #define R_AX_CH12_PAGE_INFO 0x8A80 964 965 #define R_AX_PUB_PAGE_INFO3 0x8A8C 966 #define B_AX_G1_AVAL_PG_MASK GENMASK(28, 16) 967 #define B_AX_G0_AVAL_PG_MASK GENMASK(12, 0) 968 969 #define R_AX_PUB_PAGE_CTRL1 0x8A90 970 #define B_AX_PUBPG_G1_MASK GENMASK(28, 16) 971 #define B_AX_PUBPG_G0_MASK GENMASK(12, 0) 972 973 #define R_AX_PUB_PAGE_CTRL2 0x8A94 974 #define B_AX_PUBPG_ALL_MASK GENMASK(12, 0) 975 976 #define R_AX_PUB_PAGE_INFO1 0x8A98 977 #define B_AX_G1_USE_PG_MASK GENMASK(28, 16) 978 #define B_AX_G0_USE_PG_MASK GENMASK(12, 0) 979 980 #define R_AX_PUB_PAGE_INFO2 0x8A9C 981 #define B_AX_PUB_AVAL_PG_MASK GENMASK(12, 0) 982 983 #define R_AX_WP_PAGE_CTRL1 0x8AA0 984 #define B_AX_PREC_PAGE_WP_CH811_MASK GENMASK(24, 16) 985 #define B_AX_PREC_PAGE_WP_CH07_MASK GENMASK(8, 0) 986 987 #define R_AX_WP_PAGE_CTRL2 0x8AA4 988 #define B_AX_WP_THRD_MASK GENMASK(12, 0) 989 990 #define R_AX_WP_PAGE_INFO1 0x8AA8 991 #define B_AX_WP_AVAL_PG_MASK GENMASK(28, 16) 992 993 #define R_AX_WDE_PKTBUF_CFG 0x8C08 994 #define B_AX_WDE_START_BOUND_MASK GENMASK(13, 8) 995 #define B_AX_WDE_PAGE_SEL_MASK GENMASK(1, 0) 996 #define B_AX_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16) 997 998 #define R_AX_WDE_ERRFLAG_MSG 0x8C30 999 #define B_AX_WDE_ERR_FLAG_MSG_MASK GENMASK(31, 0) 1000 1001 #define R_AX_WDE_ERR_FLAG_CFG 0x8C34 1002 1003 #define R_AX_WDE_ERR_IMR 0x8C38 1004 #define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27) 1005 #define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26) 1006 #define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25) 1007 #define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24) 1008 #define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19) 1009 #define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18) 1010 #define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17) 1011 #define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16) 1012 #define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15) 1013 #define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14) 1014 #define B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN BIT(13) 1015 #define B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN BIT(12) 1016 #define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN BIT(7) 1017 #define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN BIT(6) 1018 #define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN BIT(5) 1019 #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4) 1020 #define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN BIT(3) 1021 #define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2) 1022 #define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1) 1023 #define B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN BIT(0) 1024 #define B_AX_WDE_IMR_CLR (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \ 1025 B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \ 1026 B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ 1027 B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \ 1028 B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ 1029 B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \ 1030 B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \ 1031 B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \ 1032 B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \ 1033 B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \ 1034 B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \ 1035 B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1036 B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1037 B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \ 1038 B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \ 1039 B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ 1040 B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \ 1041 B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \ 1042 B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN) 1043 #define B_AX_WDE_IMR_SET (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \ 1044 B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN | \ 1045 B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ 1046 B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN | \ 1047 B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ 1048 B_AX_WDE_GETNPG_STRPG_ERR_INT_EN | \ 1049 B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN | \ 1050 B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN | \ 1051 B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \ 1052 B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \ 1053 B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \ 1054 B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1055 B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1056 B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \ 1057 B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \ 1058 B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ 1059 B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \ 1060 B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \ 1061 B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN) 1062 1063 #define B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN BIT(29) 1064 #define B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN BIT(28) 1065 #define B_AX_WDE_DATCHN_RRDY_ERR_INT_EN BIT(27) 1066 #define B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN BIT(26) 1067 #define B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN BIT(25) 1068 #define B_AX_WDE_DATCHN_ARBT_ERR_INT_EN BIT(24) 1069 #define B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN BIT(19) 1070 #define B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN BIT(18) 1071 #define B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN BIT(17) 1072 #define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16) 1073 #define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15) 1074 #define B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN BIT(14) 1075 #define B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9) 1076 #define B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8) 1077 #define B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7) 1078 #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6) 1079 #define B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5) 1080 #define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4) 1081 #define B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3) 1082 #define B_AX_WDE_BUFREQ_SIZELMT_INT_EN BIT(2) 1083 #define B_AX_WDE_BUFREQ_SIZE0_INT_EN BIT(1) 1084 #define B_AX_WDE_IMR_CLR_V1 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \ 1085 B_AX_WDE_BUFREQ_SIZE0_INT_EN | \ 1086 B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \ 1087 B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \ 1088 B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \ 1089 B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \ 1090 B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \ 1091 B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \ 1092 B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \ 1093 B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \ 1094 B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \ 1095 B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \ 1096 B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \ 1097 B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1098 B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1099 B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \ 1100 B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \ 1101 B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ 1102 B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \ 1103 B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \ 1104 B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \ 1105 B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \ 1106 B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \ 1107 B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN) 1108 #define B_AX_WDE_IMR_SET_V1 (B_AX_WDE_BUFREQ_QTAID_ERR_INT_EN | \ 1109 B_AX_WDE_BUFREQ_SIZE0_INT_EN | \ 1110 B_AX_WDE_BUFREQ_SIZELMT_INT_EN | \ 1111 B_AX_WDE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \ 1112 B_AX_WDE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \ 1113 B_AX_WDE_BUFRTN_SIZE_ERR_INT_EN_V1 | \ 1114 B_AX_WDE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \ 1115 B_AX_WDE_GETNPG_STRPG_ERR_INT_EN_V1 | \ 1116 B_AX_WDE_GETNPG_PGOFST_ERR_INT_EN_V1 | \ 1117 B_AX_WDE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \ 1118 B_AX_WDE_QUE_CMDTYPE_ERR_INT_EN | \ 1119 B_AX_WDE_QUE_DSTQUEID_ERR_INT_EN | \ 1120 B_AX_WDE_QUE_SRCQUEID_ERR_INT_EN | \ 1121 B_AX_WDE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1122 B_AX_WDE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1123 B_AX_WDE_PREPKTLLT_AD_ERR_INT_EN | \ 1124 B_AX_WDE_NXTPKTLL_AD_ERR_INT_EN | \ 1125 B_AX_WDE_QUEMGN_FRZTO_ERR_INT_EN | \ 1126 B_AX_WDE_DATCHN_ARBT_ERR_INT_EN | \ 1127 B_AX_WDE_DATCHN_NULLPG_ERR_INT_EN | \ 1128 B_AX_WDE_DATCHN_FRZTO_ERR_INT_EN | \ 1129 B_AX_WDE_DATCHN_RRDY_ERR_INT_EN | \ 1130 B_AX_WDE_DATCHN_ADRERR_ERR_INT_EN | \ 1131 B_AX_WDE_DATCHN_CAMREQ_ERR_INT_EN) 1132 1133 #define R_AX_WDE_ERR_ISR 0x8C3C 1134 #define B_AX_WDE_DATCHN_RRDY_ERR BIT(27) 1135 #define B_AX_WDE_DATCHN_FRZTO_ERR BIT(26) 1136 #define B_AX_WDE_DATCHN_NULLPG_ERR BIT(25) 1137 #define B_AX_WDE_DATCHN_ARBT_ERR BIT(24) 1138 #define B_AX_WDE_QUEMGN_FRZTO_ERR BIT(19) 1139 #define B_AX_WDE_NXTPKTLL_AD_ERR BIT(18) 1140 #define B_AX_WDE_PREPKTLLT_AD_ERR BIT(17) 1141 #define B_AX_WDE_ENQ_PKTCNT_NVAL_ERR BIT(16) 1142 #define B_AX_WDE_ENQ_PKTCNT_OVRF_ERR BIT(15) 1143 #define B_AX_WDE_QUE_SRCQUEID_ERR BIT(14) 1144 #define B_AX_WDE_QUE_DSTQUEID_ERR BIT(13) 1145 #define B_AX_WDE_QUE_CMDTYPE_ERR BIT(12) 1146 #define B_AX_WDE_BUFMGN_FRZTO_ERR BIT(7) 1147 #define B_AX_WDE_GETNPG_PGOFST_ERR BIT(6) 1148 #define B_AX_WDE_GETNPG_STRPG_ERR BIT(5) 1149 #define B_AX_WDE_BUFREQ_SRCHTAILPG_ERR BIT(4) 1150 #define B_AX_WDE_BUFRTN_SIZE_ERR BIT(3) 1151 #define B_AX_WDE_BUFRTN_INVLD_PKTID_ERR BIT(2) 1152 #define B_AX_WDE_BUFREQ_UNAVAL_ERR BIT(1) 1153 #define B_AX_WDE_BUFREQ_QTAID_ERR BIT(0) 1154 1155 #define B_AX_WDE_MAX_SIZE_MASK GENMASK(27, 16) 1156 #define B_AX_WDE_MIN_SIZE_MASK GENMASK(11, 0) 1157 #define R_AX_WDE_QTA0_CFG 0x8C40 1158 #define R_AX_WDE_QTA1_CFG 0x8C44 1159 #define R_AX_WDE_QTA2_CFG 0x8C48 1160 #define R_AX_WDE_QTA3_CFG 0x8C4C 1161 #define R_AX_WDE_QTA4_CFG 0x8C50 1162 1163 #define B_AX_DLE_PUB_PGNUM GENMASK(12, 0) 1164 #define B_AX_DLE_FREE_HEADPG GENMASK(11, 0) 1165 #define B_AX_DLE_FREE_TAILPG GENMASK(27, 16) 1166 #define B_AX_DLE_USE_PGNUM GENMASK(27, 16) 1167 #define B_AX_DLE_RSV_PGNUM GENMASK(11, 0) 1168 #define B_AX_DLE_QEMPTY_GRP GENMASK(31, 0) 1169 1170 #define R_AX_WDE_INI_STATUS 0x8D00 1171 #define B_AX_WDE_Q_MGN_INI_RDY BIT(1) 1172 #define B_AX_WDE_BUF_MGN_INI_RDY BIT(0) 1173 #define WDE_MGN_INI_RDY (B_AX_WDE_Q_MGN_INI_RDY | B_AX_WDE_BUF_MGN_INI_RDY) 1174 #define R_AX_WDE_DBG_FUN_INTF_CTL 0x8D10 1175 #define B_AX_WDE_DFI_ACTIVE BIT(31) 1176 #define B_AX_WDE_DFI_TRGSEL_MASK GENMASK(19, 16) 1177 #define B_AX_WDE_DFI_ADDR_MASK GENMASK(15, 0) 1178 #define R_AX_WDE_DBG_FUN_INTF_DATA 0x8D14 1179 #define B_AX_WDE_DFI_DATA_MASK GENMASK(31, 0) 1180 1181 #define R_AX_PLE_PKTBUF_CFG 0x9008 1182 #define B_AX_PLE_START_BOUND_MASK GENMASK(13, 8) 1183 #define B_AX_PLE_PAGE_SEL_MASK GENMASK(1, 0) 1184 #define B_AX_PLE_FREE_PAGE_NUM_MASK GENMASK(28, 16) 1185 #define R_AX_PLE_ERR_FLAG_CFG 0x9034 1186 1187 #define R_AX_PLE_ERR_IMR 0x9038 1188 #define B_AX_PLE_DATCHN_RRDY_ERR_INT_EN BIT(27) 1189 #define B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN BIT(26) 1190 #define B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN BIT(25) 1191 #define B_AX_PLE_DATCHN_ARBT_ERR_INT_EN BIT(24) 1192 #define B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN BIT(19) 1193 #define B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN BIT(18) 1194 #define B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN BIT(17) 1195 #define B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN BIT(16) 1196 #define B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN BIT(15) 1197 #define B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN BIT(14) 1198 #define B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN BIT(13) 1199 #define B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN BIT(12) 1200 #define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN BIT(7) 1201 #define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN BIT(6) 1202 #define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN BIT(5) 1203 #define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN BIT(4) 1204 #define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN BIT(3) 1205 #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN BIT(2) 1206 #define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN BIT(1) 1207 #define B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN BIT(0) 1208 #define B_AX_PLE_IMR_CLR (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \ 1209 B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \ 1210 B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ 1211 B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | \ 1212 B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ 1213 B_AX_PLE_GETNPG_STRPG_ERR_INT_EN | \ 1214 B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | \ 1215 B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | \ 1216 B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \ 1217 B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \ 1218 B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \ 1219 B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1220 B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1221 B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \ 1222 B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \ 1223 B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ 1224 B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \ 1225 B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \ 1226 B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN) 1227 #define B_AX_PLE_IMR_SET (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \ 1228 B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN | \ 1229 B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN | \ 1230 B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN | \ 1231 B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN | \ 1232 B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN | \ 1233 B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN | \ 1234 B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \ 1235 B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \ 1236 B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \ 1237 B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1238 B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1239 B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \ 1240 B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \ 1241 B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ 1242 B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \ 1243 B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \ 1244 B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN) 1245 1246 #define B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29) 1247 #define B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28) 1248 #define B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 BIT(9) 1249 #define B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 BIT(8) 1250 #define B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 BIT(7) 1251 #define B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 BIT(6) 1252 #define B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 BIT(5) 1253 #define B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 BIT(4) 1254 #define B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 BIT(3) 1255 #define B_AX_PLE_BUFREQ_SIZELMT_INT_EN BIT(2) 1256 #define B_AX_PLE_BUFREQ_SIZE0_INT_EN BIT(1) 1257 #define B_AX_PLE_IMR_CLR_V1 (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \ 1258 B_AX_PLE_BUFREQ_SIZE0_INT_EN | \ 1259 B_AX_PLE_BUFREQ_SIZELMT_INT_EN | \ 1260 B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \ 1261 B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \ 1262 B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 | \ 1263 B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \ 1264 B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 | \ 1265 B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 | \ 1266 B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \ 1267 B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \ 1268 B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \ 1269 B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \ 1270 B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1271 B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1272 B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \ 1273 B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \ 1274 B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ 1275 B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \ 1276 B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \ 1277 B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN | \ 1278 B_AX_PLE_DATCHN_RRDY_ERR_INT_EN | \ 1279 B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN | \ 1280 B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN) 1281 #define B_AX_PLE_IMR_SET_V1 (B_AX_PLE_BUFREQ_QTAID_ERR_INT_EN | \ 1282 B_AX_PLE_BUFREQ_SIZE0_INT_EN | \ 1283 B_AX_PLE_BUFREQ_SIZELMT_INT_EN | \ 1284 B_AX_PLE_BUFREQ_UNAVAL_ERR_INT_EN_V1 | \ 1285 B_AX_PLE_BUFRTN_INVLD_PKTID_ERR_INT_EN_V1 | \ 1286 B_AX_PLE_BUFRTN_SIZE_ERR_INT_EN_V1 | \ 1287 B_AX_PLE_BUFREQ_SRCHTAILPG_ERR_INT_EN_V1 | \ 1288 B_AX_PLE_GETNPG_STRPG_ERR_INT_EN_V1 | \ 1289 B_AX_PLE_GETNPG_PGOFST_ERR_INT_EN_V1 | \ 1290 B_AX_PLE_BUFMGN_FRZTO_ERR_INT_EN_V1 | \ 1291 B_AX_PLE_QUE_CMDTYPE_ERR_INT_EN | \ 1292 B_AX_PLE_QUE_DSTQUEID_ERR_INT_EN | \ 1293 B_AX_PLE_QUE_SRCQUEID_ERR_INT_EN | \ 1294 B_AX_PLE_ENQ_PKTCNT_OVRF_ERR_INT_EN | \ 1295 B_AX_PLE_ENQ_PKTCNT_NVAL_ERR_INT_EN | \ 1296 B_AX_PLE_PREPKTLLT_AD_ERR_INT_EN | \ 1297 B_AX_PLE_NXTPKTLL_AD_ERR_INT_EN | \ 1298 B_AX_PLE_QUEMGN_FRZTO_ERR_INT_EN | \ 1299 B_AX_PLE_DATCHN_ARBT_ERR_INT_EN | \ 1300 B_AX_PLE_DATCHN_NULLPG_ERR_INT_EN | \ 1301 B_AX_PLE_DATCHN_FRZTO_ERR_INT_EN | \ 1302 B_AX_PLE_DATCHN_RRDY_ERR_INT_EN | \ 1303 B_AX_PLE_DATCHN_ADRERR_ERR_INT_EN | \ 1304 B_AX_PLE_DATCHN_CAMREQ_ERR_INT_EN) 1305 1306 #define R_AX_PLE_ERR_FLAG_ISR 0x903C 1307 #define B_AX_PLE_MAX_SIZE_MASK GENMASK(27, 16) 1308 #define B_AX_PLE_MIN_SIZE_MASK GENMASK(11, 0) 1309 #define R_AX_PLE_QTA0_CFG 0x9040 1310 #define R_AX_PLE_QTA1_CFG 0x9044 1311 #define R_AX_PLE_QTA2_CFG 0x9048 1312 #define R_AX_PLE_QTA3_CFG 0x904C 1313 #define R_AX_PLE_QTA4_CFG 0x9050 1314 #define R_AX_PLE_QTA5_CFG 0x9054 1315 #define R_AX_PLE_QTA6_CFG 0x9058 1316 #define B_AX_PLE_Q6_MAX_SIZE_MASK GENMASK(27, 16) 1317 #define B_AX_PLE_Q6_MIN_SIZE_MASK GENMASK(11, 0) 1318 #define R_AX_PLE_QTA7_CFG 0x905C 1319 #define R_AX_PLE_QTA8_CFG 0x9060 1320 #define R_AX_PLE_QTA9_CFG 0x9064 1321 #define R_AX_PLE_QTA10_CFG 0x9068 1322 #define R_AX_PLE_QTA11_CFG 0x906C 1323 1324 #define R_AX_PLE_INI_STATUS 0x9100 1325 #define B_AX_PLE_Q_MGN_INI_RDY BIT(1) 1326 #define B_AX_PLE_BUF_MGN_INI_RDY BIT(0) 1327 #define PLE_MGN_INI_RDY (B_AX_PLE_Q_MGN_INI_RDY | B_AX_PLE_BUF_MGN_INI_RDY) 1328 #define R_AX_PLE_DBG_FUN_INTF_CTL 0x9110 1329 #define B_AX_PLE_DFI_ACTIVE BIT(31) 1330 #define B_AX_PLE_DFI_TRGSEL_MASK GENMASK(19, 16) 1331 #define B_AX_PLE_DFI_ADDR_MASK GENMASK(15, 0) 1332 #define R_AX_PLE_DBG_FUN_INTF_DATA 0x9114 1333 #define B_AX_PLE_DFI_DATA_MASK GENMASK(31, 0) 1334 1335 #define R_AX_WDRLS_CFG 0x9408 1336 #define B_AX_RLSRPT_BUFREQ_TO_MASK GENMASK(15, 8) 1337 #define B_AX_WDRLS_MODE_MASK GENMASK(1, 0) 1338 1339 #define R_AX_RLSRPT0_CFG0 0x9410 1340 #define B_AX_RLSRPT0_FLTR_MAP_MASK GENMASK(27, 24) 1341 #define B_AX_RLSRPT0_PKTTYPE_MASK GENMASK(19, 16) 1342 #define B_AX_RLSRPT0_PID_MASK GENMASK(10, 8) 1343 #define B_AX_RLSRPT0_QID_MASK GENMASK(5, 0) 1344 1345 #define R_AX_RLSRPT0_CFG1 0x9414 1346 #define B_AX_RLSRPT0_TO_MASK GENMASK(23, 16) 1347 #define B_AX_RLSRPT0_AGGNUM_MASK GENMASK(7, 0) 1348 1349 #define R_AX_WDRLS_ERR_IMR 0x9430 1350 #define B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN BIT(13) 1351 #define B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN BIT(12) 1352 #define B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN BIT(9) 1353 #define B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN BIT(8) 1354 #define B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN BIT(5) 1355 #define B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN BIT(4) 1356 #define B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN BIT(2) 1357 #define B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN BIT(1) 1358 #define B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN BIT(0) 1359 #define B_AX_WDRLS_IMR_EN_CLR (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \ 1360 B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \ 1361 B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \ 1362 B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | \ 1363 B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \ 1364 B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \ 1365 B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \ 1366 B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \ 1367 B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN) 1368 #define B_AX_WDRLS_IMR_SET (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \ 1369 B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \ 1370 B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \ 1371 B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \ 1372 B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \ 1373 B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \ 1374 B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \ 1375 B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN) 1376 #define B_AX_WDRLS_IMR_SET_V1 (B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN | \ 1377 B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN | \ 1378 B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN | \ 1379 B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN | \ 1380 B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN | \ 1381 B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN | \ 1382 B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN | \ 1383 B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN | \ 1384 B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN) 1385 1386 #define R_AX_WDRLS_ERR_ISR 0x9434 1387 1388 #define R_AX_BBRPT_COM_ERR_IMR 0x9608 1389 #define B_AX_BBRPT_COM_HANG_EN BIT(1) 1390 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0) 1391 1392 #define R_AX_BBRPT_COM_ERR_IMR_ISR 0x960C 1393 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR BIT(16) 1394 #define B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN BIT(0) 1395 1396 #define R_AX_BBRPT_CHINFO_ERR_IMR 0x9628 1397 #define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7) 1398 #define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6) 1399 #define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5) 1400 #define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4) 1401 #define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3) 1402 #define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2) 1403 #define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1) 1404 #define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0) 1405 #define R_AX_BBRPT_CHINFO_IMR_SET_V1 (B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | \ 1406 B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | \ 1407 B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | \ 1408 B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | \ 1409 B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | \ 1410 B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | \ 1411 B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | \ 1412 B_AX_BBPRT_CHIF_TO_ERR_INT_EN) 1413 1414 #define R_AX_BBRPT_CHINFO_ERR_IMR_ISR 0x962C 1415 #define B_AX_BBPRT_CHIF_TO_ERR BIT(23) 1416 #define B_AX_BBPRT_CHIF_NULL_ERR BIT(22) 1417 #define B_AX_BBPRT_CHIF_LEFT2_ERR BIT(21) 1418 #define B_AX_BBPRT_CHIF_LEFT1_ERR BIT(20) 1419 #define B_AX_BBPRT_CHIF_HDRL_ERR BIT(19) 1420 #define B_AX_BBPRT_CHIF_BOVF_ERR BIT(18) 1421 #define B_AX_BBPRT_CHIF_OVF_ERR BIT(17) 1422 #define B_AX_BBPRT_CHIF_BB_TO_ERR BIT(16) 1423 #define B_AX_BBPRT_CHIF_TO_ERR_INT_EN BIT(7) 1424 #define B_AX_BBPRT_CHIF_NULL_ERR_INT_EN BIT(6) 1425 #define B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN BIT(5) 1426 #define B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN BIT(4) 1427 #define B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN BIT(3) 1428 #define B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN BIT(2) 1429 #define B_AX_BBPRT_CHIF_OVF_ERR_INT_EN BIT(1) 1430 #define B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN BIT(0) 1431 #define B_AX_BBRPT_CHINFO_IMR_CLR (B_AX_BBPRT_CHIF_BB_TO_ERR_INT_EN | \ 1432 B_AX_BBPRT_CHIF_OVF_ERR_INT_EN | \ 1433 B_AX_BBPRT_CHIF_BOVF_ERR_INT_EN | \ 1434 B_AX_BBPRT_CHIF_HDRL_ERR_INT_EN | \ 1435 B_AX_BBPRT_CHIF_LEFT1_ERR_INT_EN | \ 1436 B_AX_BBPRT_CHIF_LEFT2_ERR_INT_EN | \ 1437 B_AX_BBPRT_CHIF_NULL_ERR_INT_EN | \ 1438 B_AX_BBPRT_CHIF_TO_ERR_INT_EN) 1439 1440 #define R_AX_BBRPT_DFS_ERR_IMR 0x9638 1441 #define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0) 1442 1443 #define R_AX_BBRPT_DFS_ERR_IMR_ISR 0x963C 1444 #define B_AX_BBRPT_DFS_TO_ERR BIT(16) 1445 #define B_AX_BBRPT_DFS_TO_ERR_INT_EN BIT(0) 1446 1447 #define R_AX_LA_ERRFLAG 0x966C 1448 #define B_AX_LA_ISR_DATA_LOSS_ERR BIT(16) 1449 #define B_AX_LA_IMR_DATA_LOSS_ERR BIT(0) 1450 1451 #define R_AX_WD_BUF_REQ 0x9800 1452 #define R_AX_PL_BUF_REQ 0x9820 1453 #define B_AX_WD_BUF_REQ_EXEC BIT(31) 1454 #define B_AX_WD_BUF_REQ_QUOTA_ID_MASK GENMASK(23, 16) 1455 #define B_AX_WD_BUF_REQ_LEN_MASK GENMASK(15, 0) 1456 1457 #define R_AX_WD_BUF_STATUS 0x9804 1458 #define R_AX_PL_BUF_STATUS 0x9824 1459 #define B_AX_WD_BUF_STAT_DONE BIT(31) 1460 #define B_AX_WD_BUF_STAT_PKTID_MASK GENMASK(11, 0) 1461 1462 #define R_AX_WD_CPUQ_OP_0 0x9810 1463 #define R_AX_PL_CPUQ_OP_0 0x9830 1464 #define B_AX_WD_CPUQ_OP_EXEC BIT(31) 1465 #define B_AX_CPUQ_OP_CMD_TYPE_MASK GENMASK(27, 24) 1466 #define B_AX_CPUQ_OP_MACID_MASK GENMASK(23, 16) 1467 #define B_AX_CPUQ_OP_PKTNUM_MASK GENMASK(7, 0) 1468 1469 #define R_AX_WD_CPUQ_OP_1 0x9814 1470 #define R_AX_PL_CPUQ_OP_1 0x9834 1471 #define B_AX_CPUQ_OP_SRC_PID_MASK GENMASK(24, 22) 1472 #define B_AX_CPUQ_OP_SRC_QID_MASK GENMASK(21, 16) 1473 #define B_AX_CPUQ_OP_DST_PID_MASK GENMASK(8, 6) 1474 #define B_AX_CPUQ_OP_DST_QID_MASK GENMASK(5, 0) 1475 1476 #define R_AX_WD_CPUQ_OP_2 0x9818 1477 #define R_AX_PL_CPUQ_OP_2 0x9838 1478 #define B_AX_WD_CPUQ_OP_STRT_PKTID_MASK GENMASK(27, 16) 1479 #define B_AX_WD_CPUQ_OP_END_PKTID_MASK GENMASK(11, 0) 1480 1481 #define R_AX_WD_CPUQ_OP_STATUS 0x981C 1482 #define R_AX_PL_CPUQ_OP_STATUS 0x983C 1483 #define B_AX_WD_CPUQ_OP_STAT_DONE BIT(31) 1484 #define B_AX_WD_CPUQ_OP_PKTID_MASK GENMASK(11, 0) 1485 1486 #define R_AX_CPUIO_ERR_IMR 0x9840 1487 #define B_AX_PLEQUE_OP_ERR_INT_EN BIT(12) 1488 #define B_AX_PLEBUF_OP_ERR_INT_EN BIT(8) 1489 #define B_AX_WDEQUE_OP_ERR_INT_EN BIT(4) 1490 #define B_AX_WDEBUF_OP_ERR_INT_EN BIT(0) 1491 #define B_AX_CPUIO_IMR_CLR (B_AX_WDEBUF_OP_ERR_INT_EN | \ 1492 B_AX_WDEQUE_OP_ERR_INT_EN | \ 1493 B_AX_PLEBUF_OP_ERR_INT_EN | \ 1494 B_AX_PLEQUE_OP_ERR_INT_EN) 1495 #define B_AX_CPUIO_IMR_SET (B_AX_WDEBUF_OP_ERR_INT_EN | \ 1496 B_AX_WDEQUE_OP_ERR_INT_EN | \ 1497 B_AX_PLEBUF_OP_ERR_INT_EN | \ 1498 B_AX_PLEQUE_OP_ERR_INT_EN) 1499 1500 #define R_AX_CPUIO_ERR_ISR 0x9844 1501 1502 #define R_AX_SEC_ERR_IMR_ISR 0x991C 1503 1504 #define R_AX_PKTIN_SETTING 0x9A00 1505 #define B_AX_WD_ADDR_INFO_LENGTH BIT(1) 1506 1507 #define R_AX_PKTIN_ERR_IMR 0x9A20 1508 #define B_AX_PKTIN_GETPKTID_ERR_INT_EN BIT(0) 1509 1510 #define R_AX_PKTIN_ERR_ISR 0x9A24 1511 1512 #define R_AX_MPDU_TX_ERR_ISR 0x9BF0 1513 #define R_AX_MPDU_TX_ERR_IMR 0x9BF4 1514 #define B_AX_TX_KSRCH_ERR_EN BIT(9) 1515 #define B_AX_TX_NW_TYPE_ERR_EN BIT(8) 1516 #define B_AX_TX_LLC_PRE_ERR_EN BIT(7) 1517 #define B_AX_TX_ETH_TYPE_ERR_EN BIT(6) 1518 #define B_AX_TX_HDR3_SIZE_ERR_INT_EN BIT(5) 1519 #define B_AX_TX_OFFSET_ERR_INT_EN BIT(4) 1520 #define B_AX_TX_MPDU_SIZE_ZERO_INT_EN BIT(3) 1521 #define B_AX_TX_NXT_ERRPKTID_INT_EN BIT(2) 1522 #define B_AX_TX_GET_ERRPKTID_INT_EN BIT(1) 1523 #define B_AX_MPDU_TX_IMR_SET_V1 (B_AX_TX_GET_ERRPKTID_INT_EN | \ 1524 B_AX_TX_NXT_ERRPKTID_INT_EN | \ 1525 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | \ 1526 B_AX_TX_HDR3_SIZE_ERR_INT_EN | \ 1527 B_AX_TX_ETH_TYPE_ERR_EN | \ 1528 B_AX_TX_NW_TYPE_ERR_EN | \ 1529 B_AX_TX_KSRCH_ERR_EN) 1530 1531 #define R_AX_MPDU_PROC 0x9C00 1532 #define B_AX_A_ICV_ERR BIT(1) 1533 #define B_AX_APPEND_FCS BIT(0) 1534 1535 #define R_AX_ACTION_FWD0 0x9C04 1536 #define TRXCFG_MPDU_PROC_ACT_FRWD 0x02A95A95 1537 1538 #define R_AX_TF_FWD 0x9C14 1539 #define TRXCFG_MPDU_PROC_TF_FRWD 0x0000AA55 1540 1541 #define R_AX_HW_RPT_FWD 0x9C18 1542 #define B_AX_FWD_PPDU_STAT_MASK GENMASK(1, 0) 1543 #define RTW89_PRPT_DEST_HOST 1 1544 #define RTW89_PRPT_DEST_WLCPU 2 1545 1546 #define R_AX_CUT_AMSDU_CTRL 0x9C40 1547 #define TRXCFG_MPDU_PROC_CUT_CTRL 0x010E05F0 1548 1549 #define R_AX_MPDU_RX_ERR_ISR 0x9CF0 1550 #define R_AX_MPDU_RX_ERR_IMR 0x9CF4 1551 #define B_AX_RPT_ERR_INT_EN BIT(3) 1552 #define B_AX_MHDRLEN_ERR_INT_EN BIT(1) 1553 #define B_AX_GETPKTID_ERR_INT_EN BIT(0) 1554 #define B_AX_MPDU_RX_IMR_SET_V1 B_AX_RPT_ERR_INT_EN 1555 1556 #define R_AX_SEC_ENG_CTRL 0x9D00 1557 #define B_AX_TX_PARTIAL_MODE BIT(11) 1558 #define B_AX_CLK_EN_CGCMP BIT(10) 1559 #define B_AX_CLK_EN_WAPI BIT(9) 1560 #define B_AX_CLK_EN_WEP_TKIP BIT(8) 1561 #define B_AX_BMC_MGNT_DEC BIT(5) 1562 #define B_AX_UC_MGNT_DEC BIT(4) 1563 #define B_AX_MC_DEC BIT(3) 1564 #define B_AX_BC_DEC BIT(2) 1565 #define B_AX_SEC_RX_DEC BIT(1) 1566 #define B_AX_SEC_TX_ENC BIT(0) 1567 1568 #define R_AX_SEC_MPDU_PROC 0x9D04 1569 #define B_AX_APPEND_ICV BIT(1) 1570 #define B_AX_APPEND_MIC BIT(0) 1571 1572 #define R_AX_SEC_CAM_ACCESS 0x9D10 1573 #define R_AX_SEC_CAM_RDATA 0x9D14 1574 #define R_AX_SEC_CAM_WDATA 0x9D18 1575 1576 #define R_AX_SEC_DEBUG 0x9D1C 1577 #define B_AX_IMR_ERROR BIT(3) 1578 1579 #define R_AX_SEC_DEBUG1 0x9D1C 1580 #define B_AX_TX_TIMEOUT_SEL_MASK GENMASK(31, 30) 1581 #define AX_TX_TO_VAL 0x2 1582 1583 #define R_AX_SEC_TX_DEBUG 0x9D20 1584 #define R_AX_SEC_RX_DEBUG 0x9D24 1585 #define R_AX_SEC_TRX_PKT_CNT 0x9D28 1586 #define R_AX_SEC_TRX_BLK_CNT 0x9D2C 1587 1588 #define R_AX_SEC_ERROR_FLAG_IMR 0x9D2C 1589 #define B_AX_RX_HANG_IMR BIT(1) 1590 #define B_AX_TX_HANG_IMR BIT(0) 1591 1592 #define R_AX_SS_CTRL 0x9E10 1593 #define B_AX_SS_INIT_DONE_1 BIT(31) 1594 #define B_AX_SS_WARM_INIT_FLG BIT(29) 1595 #define B_AX_SS_NONEMPTY_SS2FINFO_EN BIT(28) 1596 #define B_AX_SS_EN BIT(0) 1597 1598 #define R_AX_SS2FINFO_PATH 0x9E50 1599 #define B_AX_SS_UL_REL BIT(31) 1600 #define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24) 1601 #define B_AX_SS_REL_PORT_MASK GENMASK(18, 16) 1602 #define B_AX_SS_DEST_QUEUE_MASK GENMASK(13, 8) 1603 #define SS2F_PATH_WLCPU 0x0A 1604 #define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0) 1605 1606 #define R_AX_SS_MACID_PAUSE_0 0x9EB0 1607 #define B_AX_SS_MACID31_0_PAUSE_SH 0 1608 #define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0) 1609 1610 #define R_AX_SS_MACID_PAUSE_1 0x9EB4 1611 #define B_AX_SS_MACID63_32_PAUSE_SH 0 1612 #define B_AX_SS_MACID63_32_PAUSE_MASK GENMASK(31, 0) 1613 1614 #define R_AX_SS_MACID_PAUSE_2 0x9EB8 1615 #define B_AX_SS_MACID95_64_PAUSE_SH 0 1616 #define B_AX_SS_MACID95_64_PAUSE_MASK GENMASK(31, 0) 1617 1618 #define R_AX_SS_MACID_PAUSE_3 0x9EBC 1619 #define B_AX_SS_MACID127_96_PAUSE_SH 0 1620 #define B_AX_SS_MACID127_96_PAUSE_MASK GENMASK(31, 0) 1621 1622 #define R_AX_STA_SCHEDULER_ERR_IMR 0x9EF0 1623 #define B_AX_PLE_B_PKTID_ERR_INT_EN BIT(2) 1624 #define B_AX_RPT_HANG_TIMEOUT_INT_EN BIT(1) 1625 #define B_AX_SEARCH_HANG_TIMEOUT_INT_EN BIT(0) 1626 #define B_AX_STA_SCHEDULER_IMR_SET (B_AX_SEARCH_HANG_TIMEOUT_INT_EN | \ 1627 B_AX_RPT_HANG_TIMEOUT_INT_EN | \ 1628 B_AX_PLE_B_PKTID_ERR_INT_EN) 1629 1630 #define R_AX_STA_SCHEDULER_ERR_ISR 0x9EF4 1631 1632 #define R_AX_TXPKTCTL_ERR_IMR_ISR 0x9F1C 1633 #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR BIT(25) 1634 #define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR BIT(24) 1635 #define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR BIT(19) 1636 #define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR BIT(18) 1637 #define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR BIT(17) 1638 #define B_AX_TXPKTCTL_USRCTL_REINIT_ERR BIT(16) 1639 #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9) 1640 #define B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN BIT(8) 1641 #define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3) 1642 #define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2) 1643 #define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1) 1644 #define B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN BIT(0) 1645 #define B_AX_TXPKTCTL_IMR_B0_CLR (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \ 1646 B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \ 1647 B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | \ 1648 B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | \ 1649 B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \ 1650 B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN) 1651 #define B_AX_TXPKTCTL_IMR_B1_CLR (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \ 1652 B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \ 1653 B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN | \ 1654 B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN | \ 1655 B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \ 1656 B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN) 1657 #define B_AX_TXPKTCTL_IMR_B0_SET (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \ 1658 B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN) 1659 #define B_AX_TXPKTCTL_IMR_B1_SET (B_AX_TXPKTCTL_USRCTL_REINIT_ERR_INT_EN | \ 1660 B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN | \ 1661 B_AX_TXPKTCTL_CMDPSR_CMDTYPE_ERR_INT_EN | \ 1662 B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN) 1663 1664 #define R_AX_TXPKTCTL_ERR_IMR_ISR_B1 0x9F2C 1665 #define B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN BIT(9) 1666 #define B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN BIT(3) 1667 #define B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN BIT(2) 1668 #define B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN BIT(1) 1669 1670 #define R_AX_DBG_FUN_INTF_CTL 0x9F30 1671 #define B_AX_DFI_ACTIVE BIT(31) 1672 #define B_AX_DFI_TRGSEL_MASK GENMASK(19, 16) 1673 #define B_AX_DFI_ADDR_MASK GENMASK(15, 0) 1674 #define R_AX_DBG_FUN_INTF_DATA 0x9F34 1675 #define B_AX_DFI_DATA_MASK GENMASK(31, 0) 1676 1677 #define R_AX_TXPKTCTL_B0_PRELD_CFG0 0x9F48 1678 #define B_AX_B0_PRELD_FEN BIT(31) 1679 #define B_AX_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16) 1680 #define PRELD_B0_ENT_NUM 10 1681 #define PRELD_AMSDU_SIZE 52 1682 #define B_AX_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8) 1683 #define B_AX_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0) 1684 1685 #define R_AX_TXPKTCTL_B0_PRELD_CFG1 0x9F4C 1686 #define B_AX_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8) 1687 #define PRELD_NEXT_WND 1 1688 #define B_AX_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0) 1689 1690 #define R_AX_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78 1691 #define B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG BIT(21) 1692 #define B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR BIT(20) 1693 #define B_AX_B0_IMR_ERR_MPDUIF_DATAERR BIT(18) 1694 #define B_AX_B0_IMR_ERR_MPDUINFO_RECFG BIT(16) 1695 #define B_AX_B0_IMR_ERR_CMDPSR_TBLSZ BIT(11) 1696 #define B_AX_B0_IMR_ERR_CMDPSR_FRZTO BIT(10) 1697 #define B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE BIT(9) 1698 #define B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR BIT(8) 1699 #define B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN BIT(3) 1700 #define B_AX_B0_IMR_ERR_USRCTL_RDNRLSCMD BIT(2) 1701 #define B_AX_B0_IMR_ERR_USRCTL_NOINIT BIT(1) 1702 #define B_AX_B0_IMR_ERR_USRCTL_REINIT BIT(0) 1703 #define B_AX_TXPKTCTL_IMR_B0_CLR_V1 (B_AX_B0_IMR_ERR_USRCTL_REINIT | \ 1704 B_AX_B0_IMR_ERR_USRCTL_NOINIT | \ 1705 B_AX_B0_IMR_ERR_USRCTL_RDNRLSCMD | \ 1706 B_AX_B0_IMR_ERR_USRCTL_RLSBMPLEN | \ 1707 B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \ 1708 B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \ 1709 B_AX_B0_IMR_ERR_CMDPSR_FRZTO | \ 1710 B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \ 1711 B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \ 1712 B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \ 1713 B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \ 1714 B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG) 1715 #define B_AX_TXPKTCTL_IMR_B0_SET_V1 (B_AX_B0_IMR_ERR_USRCTL_REINIT | \ 1716 B_AX_B0_IMR_ERR_USRCTL_NOINIT | \ 1717 B_AX_B0_IMR_ERR_CMDPSR_1STCMDERR | \ 1718 B_AX_B0_IMR_ERR_CMDPSR_CMDTYPE | \ 1719 B_AX_B0_IMR_ERR_CMDPSR_FRZTO | \ 1720 B_AX_B0_IMR_ERR_CMDPSR_TBLSZ | \ 1721 B_AX_B0_IMR_ERR_MPDUINFO_RECFG | \ 1722 B_AX_B0_IMR_ERR_MPDUIF_DATAERR | \ 1723 B_AX_B0_IMR_ERR_PRELD_RLSPKTSZERR | \ 1724 B_AX_B0_IMR_ERR_PRELD_ENTNUMCFG) 1725 1726 #define R_AX_TXPKTCTL_B1_PRELD_CFG0 0x9F88 1727 #define B_AX_B1_PRELD_FEN BIT(31) 1728 #define B_AX_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16) 1729 #define PRELD_B1_ENT_NUM 4 1730 #define B_AX_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8) 1731 #define B_AX_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0) 1732 1733 #define R_AX_TXPKTCTL_B1_PRELD_CFG1 0x9F8C 1734 #define B_AX_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8) 1735 #define B_AX_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0) 1736 1737 #define R_AX_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8 1738 #define B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG BIT(21) 1739 #define B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR BIT(20) 1740 #define B_AX_B1_IMR_ERR_MPDUIF_DATAERR BIT(18) 1741 #define B_AX_B1_IMR_ERR_MPDUINFO_RECFG BIT(16) 1742 #define B_AX_B1_IMR_ERR_CMDPSR_TBLSZ BIT(11) 1743 #define B_AX_B1_IMR_ERR_CMDPSR_FRZTO BIT(10) 1744 #define B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE BIT(9) 1745 #define B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR BIT(8) 1746 #define B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN BIT(3) 1747 #define B_AX_B1_IMR_ERR_USRCTL_RDNRLSCMD BIT(2) 1748 #define B_AX_B1_IMR_ERR_USRCTL_NOINIT BIT(1) 1749 #define B_AX_B1_IMR_ERR_USRCTL_REINIT BIT(0) 1750 #define B_AX_TXPKTCTL_IMR_B1_CLR_V1 (B_AX_B1_IMR_ERR_USRCTL_REINIT | \ 1751 B_AX_B1_IMR_ERR_USRCTL_NOINIT | \ 1752 B_AX_B1_IMR_ERR_USRCTL_RDNRLSCMD | \ 1753 B_AX_B1_IMR_ERR_USRCTL_RLSBMPLEN | \ 1754 B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR | \ 1755 B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE | \ 1756 B_AX_B1_IMR_ERR_CMDPSR_FRZTO | \ 1757 B_AX_B1_IMR_ERR_CMDPSR_TBLSZ | \ 1758 B_AX_B1_IMR_ERR_MPDUINFO_RECFG | \ 1759 B_AX_B1_IMR_ERR_MPDUIF_DATAERR | \ 1760 B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \ 1761 B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG) 1762 #define B_AX_TXPKTCTL_IMR_B1_SET_V1 (B_AX_B1_IMR_ERR_USRCTL_REINIT | \ 1763 B_AX_B1_IMR_ERR_USRCTL_NOINIT | \ 1764 B_AX_B1_IMR_ERR_CMDPSR_1STCMDERR | \ 1765 B_AX_B1_IMR_ERR_CMDPSR_CMDTYPE | \ 1766 B_AX_B1_IMR_ERR_CMDPSR_FRZTO | \ 1767 B_AX_B1_IMR_ERR_CMDPSR_TBLSZ | \ 1768 B_AX_B1_IMR_ERR_MPDUINFO_RECFG | \ 1769 B_AX_B1_IMR_ERR_MPDUIF_DATAERR | \ 1770 B_AX_B1_IMR_ERR_PRELD_RLSPKTSZERR | \ 1771 B_AX_B1_IMR_ERR_PRELD_ENTNUMCFG) 1772 1773 #define R_AX_AFE_CTRL1 0x0024 1774 1775 #define B_AX_R_SYM_WLCMAC1_P4_PC_EN BIT(4) 1776 #define B_AX_R_SYM_WLCMAC1_P3_PC_EN BIT(3) 1777 #define B_AX_R_SYM_WLCMAC1_P2_PC_EN BIT(2) 1778 #define B_AX_R_SYM_WLCMAC1_P1_PC_EN BIT(1) 1779 #define B_AX_R_SYM_WLCMAC1_PC_EN BIT(0) 1780 1781 #define R_AX_SYS_ISO_CTRL_EXTEND 0x0080 1782 #define B_AX_CMAC1_FEN BIT(30) 1783 #define B_AX_R_SYM_FEN_WLBBGLB_1 BIT(17) 1784 #define B_AX_R_SYM_FEN_WLBBFUN_1 BIT(16) 1785 #define B_AX_R_SYM_ISO_CMAC12PP BIT(5) 1786 1787 #define R_AX_CMAC_REG_START 0xC000 1788 1789 #define R_AX_CMAC_FUNC_EN 0xC000 1790 #define R_AX_CMAC_FUNC_EN_C1 0xE000 1791 #define B_AX_CMAC_CRPRT BIT(31) 1792 #define B_AX_CMAC_EN BIT(30) 1793 #define B_AX_CMAC_TXEN BIT(29) 1794 #define B_AX_CMAC_RXEN BIT(28) 1795 #define B_AX_FORCE_CMACREG_GCKEN BIT(15) 1796 #define B_AX_PHYINTF_EN BIT(5) 1797 #define B_AX_CMAC_DMA_EN BIT(4) 1798 #define B_AX_PTCLTOP_EN BIT(3) 1799 #define B_AX_SCHEDULER_EN BIT(2) 1800 #define B_AX_TMAC_EN BIT(1) 1801 #define B_AX_RMAC_EN BIT(0) 1802 1803 #define R_AX_CK_EN 0xC004 1804 #define R_AX_CK_EN_C1 0xE004 1805 #define B_AX_CMAC_ALLCKEN GENMASK(31, 0) 1806 #define B_AX_CMAC_CKEN BIT(30) 1807 #define B_AX_PHYINTF_CKEN BIT(5) 1808 #define B_AX_CMAC_DMA_CKEN BIT(4) 1809 #define B_AX_PTCLTOP_CKEN BIT(3) 1810 #define B_AX_SCHEDULER_CKEN BIT(2) 1811 #define B_AX_TMAC_CKEN BIT(1) 1812 #define B_AX_RMAC_CKEN BIT(0) 1813 1814 #define R_AX_WMAC_RFMOD 0xC010 1815 #define R_AX_WMAC_RFMOD_C1 0xE010 1816 #define B_AX_WMAC_RFMOD_MASK GENMASK(1, 0) 1817 #define AX_WMAC_RFMOD_20M 0 1818 #define AX_WMAC_RFMOD_40M 1 1819 #define AX_WMAC_RFMOD_80M 2 1820 #define AX_WMAC_RFMOD_160M 3 1821 1822 #define R_AX_GID_POSITION0 0xC070 1823 #define R_AX_GID_POSITION0_C1 0xE070 1824 #define R_AX_GID_POSITION1 0xC074 1825 #define R_AX_GID_POSITION1_C1 0xE074 1826 #define R_AX_GID_POSITION2 0xC078 1827 #define R_AX_GID_POSITION2_C1 0xE078 1828 #define R_AX_GID_POSITION3 0xC07C 1829 #define R_AX_GID_POSITION3_C1 0xE07C 1830 #define R_AX_GID_POSITION_EN0 0xC080 1831 #define R_AX_GID_POSITION_EN0_C1 0xE080 1832 #define R_AX_GID_POSITION_EN1 0xC084 1833 #define R_AX_GID_POSITION_EN1_C1 0xE084 1834 1835 #define R_AX_TX_SUB_CARRIER_VALUE 0xC088 1836 #define R_AX_TX_SUB_CARRIER_VALUE_C1 0xE088 1837 #define B_AX_TXSC_80M_MASK GENMASK(11, 8) 1838 #define B_AX_TXSC_40M_MASK GENMASK(7, 4) 1839 #define B_AX_TXSC_20M_MASK GENMASK(3, 0) 1840 1841 #define R_AX_PTCL_RRSR1 0xC090 1842 #define R_AX_PTCL_RRSR1_C1 0xE090 1843 #define B_AX_RRSR_RATE_EN_MASK GENMASK(11, 8) 1844 #define RRSR_OFDM_CCK_EN 3 1845 #define B_AX_RSC_MASK GENMASK(7, 6) 1846 #define B_AX_RRSR_CCK_MASK GENMASK(3, 0) 1847 1848 #define R_AX_CMAC_ERR_IMR 0xC160 1849 #define R_AX_CMAC_ERR_IMR_C1 0xE160 1850 #define B_AX_WMAC_TX_ERR_IND_EN BIT(7) 1851 #define B_AX_WMAC_RX_ERR_IND_EN BIT(6) 1852 #define B_AX_TXPWR_CTRL_ERR_IND_EN BIT(5) 1853 #define B_AX_PHYINTF_ERR_IND_EN BIT(4) 1854 #define B_AX_DMA_TOP_ERR_IND_EN BIT(3) 1855 #define B_AX_PTCL_TOP_ERR_IND_EN BIT(1) 1856 #define B_AX_SCHEDULE_TOP_ERR_IND_EN BIT(0) 1857 #define CMAC0_ERR_IMR_EN GENMASK(31, 0) 1858 #define CMAC1_ERR_IMR_EN GENMASK(31, 0) 1859 #define CMAC0_ERR_IMR_DIS 0 1860 #define CMAC1_ERR_IMR_DIS 0 1861 1862 #define R_AX_CMAC_ERR_ISR 0xC164 1863 #define R_AX_CMAC_ERR_ISR_C1 0xE164 1864 #define B_AX_WMAC_TX_ERR_IND BIT(7) 1865 #define B_AX_WMAC_RX_ERR_IND BIT(6) 1866 #define B_AX_TXPWR_CTRL_ERR_IND BIT(5) 1867 #define B_AX_PHYINTF_ERR_IND BIT(4) 1868 #define B_AX_DMA_TOP_ERR_IND BIT(3) 1869 #define B_AX_PTCL_TOP_ERR_IND BIT(1) 1870 #define B_AX_SCHEDULE_TOP_ERR_IND BIT(0) 1871 1872 #define R_AX_MACID_SLEEP_0 0xC2C0 1873 #define R_AX_MACID_SLEEP_0_C1 0xE2C0 1874 #define B_AX_MACID31_0_SLEEP_SH 0 1875 #define B_AX_MACID31_0_SLEEP_MASK GENMASK(31, 0) 1876 1877 #define R_AX_MACID_SLEEP_1 0xC2C4 1878 #define R_AX_MACID_SLEEP_1_C1 0xE2C4 1879 #define B_AX_MACID63_32_SLEEP_SH 0 1880 #define B_AX_MACID63_32_SLEEP_MASK GENMASK(31, 0) 1881 1882 #define R_AX_MACID_SLEEP_2 0xC2C8 1883 #define R_AX_MACID_SLEEP_2_C1 0xE2C8 1884 #define B_AX_MACID95_64_SLEEP_SH 0 1885 #define B_AX_MACID95_64_SLEEP_MASK GENMASK(31, 0) 1886 1887 #define R_AX_MACID_SLEEP_3 0xC2CC 1888 #define R_AX_MACID_SLEEP_3_C1 0xE2CC 1889 #define B_AX_MACID127_96_SLEEP_SH 0 1890 #define B_AX_MACID127_96_SLEEP_MASK GENMASK(31, 0) 1891 1892 #define SCH_PREBKF_24US 0x18 1893 #define R_AX_PREBKF_CFG_0 0xC338 1894 #define R_AX_PREBKF_CFG_0_C1 0xE338 1895 #define B_AX_PREBKF_TIME_MASK GENMASK(4, 0) 1896 1897 #define R_AX_PREBKF_CFG_1 0xC33C 1898 #define R_AX_PREBKF_CFG_1_C1 0xE33C 1899 #define B_AX_SIFS_TIMEOUT_TB_AGGR_MASK GENMASK(30, 24) 1900 #define B_AX_SIFS_PREBKF_MASK GENMASK(23, 16) 1901 #define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8) 1902 #define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0) 1903 #define SIFS_MACTXEN_T1 0x47 1904 #define SIFS_MACTXEN_T1_V1 0x41 1905 1906 #define R_AX_CCA_CFG_0 0xC340 1907 #define R_AX_CCA_CFG_0_C1 0xE340 1908 #define B_AX_BTCCA_BRK_TXOP_EN BIT(9) 1909 #define B_AX_BTCCA_EN BIT(5) 1910 #define B_AX_EDCCA_EN BIT(4) 1911 #define B_AX_SEC80_EN BIT(3) 1912 #define B_AX_SEC40_EN BIT(2) 1913 #define B_AX_SEC20_EN BIT(1) 1914 #define B_AX_CCA_EN BIT(0) 1915 1916 #define R_AX_CTN_TXEN 0xC348 1917 #define R_AX_CTN_TXEN_C1 0xE348 1918 #define B_AX_CTN_TXEN_TWT_1 BIT(15) 1919 #define B_AX_CTN_TXEN_TWT_0 BIT(14) 1920 #define B_AX_CTN_TXEN_ULQ BIT(13) 1921 #define B_AX_CTN_TXEN_BCNQ BIT(12) 1922 #define B_AX_CTN_TXEN_HGQ BIT(11) 1923 #define B_AX_CTN_TXEN_CPUMGQ BIT(10) 1924 #define B_AX_CTN_TXEN_MGQ1 BIT(9) 1925 #define B_AX_CTN_TXEN_MGQ BIT(8) 1926 #define B_AX_CTN_TXEN_VO_1 BIT(7) 1927 #define B_AX_CTN_TXEN_VI_1 BIT(6) 1928 #define B_AX_CTN_TXEN_BK_1 BIT(5) 1929 #define B_AX_CTN_TXEN_BE_1 BIT(4) 1930 #define B_AX_CTN_TXEN_VO_0 BIT(3) 1931 #define B_AX_CTN_TXEN_VI_0 BIT(2) 1932 #define B_AX_CTN_TXEN_BK_0 BIT(1) 1933 #define B_AX_CTN_TXEN_BE_0 BIT(0) 1934 #define B_AX_CTN_TXEN_ALL_MASK GENMASK(15, 0) 1935 1936 #define R_AX_MUEDCA_BE_PARAM_0 0xC350 1937 #define R_AX_MUEDCA_BE_PARAM_0_C1 0xE350 1938 #define B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK GENMASK(31, 16) 1939 #define B_AX_MUEDCA_BE_PARAM_0_CW_MASK GENMASK(15, 8) 1940 #define B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK GENMASK(7, 0) 1941 1942 #define R_AX_MUEDCA_BK_PARAM_0 0xC354 1943 #define R_AX_MUEDCA_BK_PARAM_0_C1 0xE354 1944 #define R_AX_MUEDCA_VI_PARAM_0 0xC358 1945 #define R_AX_MUEDCA_VI_PARAM_0_C1 0xE358 1946 #define R_AX_MUEDCA_VO_PARAM_0 0xC35C 1947 #define R_AX_MUEDCA_VO_PARAM_0_C1 0xE35C 1948 1949 #define R_AX_MUEDCA_EN 0xC370 1950 #define R_AX_MUEDCA_EN_C1 0xE370 1951 #define B_AX_MUEDCA_WMM_SEL BIT(8) 1952 #define B_AX_SET_MUEDCATIMER_TF_0 BIT(4) 1953 #define B_AX_MUEDCA_EN_0 BIT(0) 1954 1955 #define R_AX_CCA_CONTROL 0xC390 1956 #define R_AX_CCA_CONTROL_C1 0xE390 1957 #define B_AX_TB_CHK_TX_NAV BIT(31) 1958 #define B_AX_TB_CHK_BASIC_NAV BIT(30) 1959 #define B_AX_TB_CHK_BTCCA BIT(29) 1960 #define B_AX_TB_CHK_EDCCA BIT(28) 1961 #define B_AX_TB_CHK_CCA_S80 BIT(27) 1962 #define B_AX_TB_CHK_CCA_S40 BIT(26) 1963 #define B_AX_TB_CHK_CCA_S20 BIT(25) 1964 #define B_AX_TB_CHK_CCA_P20 BIT(24) 1965 #define B_AX_SIFS_CHK_BTCCA BIT(21) 1966 #define B_AX_SIFS_CHK_EDCCA BIT(20) 1967 #define B_AX_SIFS_CHK_CCA_S80 BIT(19) 1968 #define B_AX_SIFS_CHK_CCA_S40 BIT(18) 1969 #define B_AX_SIFS_CHK_CCA_S20 BIT(17) 1970 #define B_AX_SIFS_CHK_CCA_P20 BIT(16) 1971 #define B_AX_CTN_CHK_TXNAV BIT(8) 1972 #define B_AX_CTN_CHK_INTRA_NAV BIT(7) 1973 #define B_AX_CTN_CHK_BASIC_NAV BIT(6) 1974 #define B_AX_CTN_CHK_BTCCA BIT(5) 1975 #define B_AX_CTN_CHK_EDCCA BIT(4) 1976 #define B_AX_CTN_CHK_CCA_S80 BIT(3) 1977 #define B_AX_CTN_CHK_CCA_S40 BIT(2) 1978 #define B_AX_CTN_CHK_CCA_S20 BIT(1) 1979 #define B_AX_CTN_CHK_CCA_P20 BIT(0) 1980 1981 #define R_AX_CTN_DRV_TXEN 0xC398 1982 #define R_AX_CTN_DRV_TXEN_C1 0xE398 1983 #define B_AX_CTN_TXEN_TWT_3 BIT(17) 1984 #define B_AX_CTN_TXEN_TWT_2 BIT(16) 1985 #define B_AX_CTN_TXEN_ALL_MASK_V1 GENMASK(17, 0) 1986 1987 #define R_AX_SCHEDULE_ERR_IMR 0xC3E8 1988 #define R_AX_SCHEDULE_ERR_IMR_C1 0xE3E8 1989 #define B_AX_SORT_NON_IDLE_ERR_INT_EN BIT(1) 1990 1991 #define R_AX_SCHEDULE_ERR_ISR 0xC3EC 1992 #define R_AX_SCHEDULE_ERR_ISR_C1 0xE3EC 1993 1994 #define R_AX_SCH_DBG_SEL 0xC3F4 1995 #define R_AX_SCH_DBG_SEL_C1 0xE3F4 1996 #define B_AX_SCH_DBG_EN BIT(16) 1997 #define B_AX_SCH_CFG_CMD_SEL GENMASK(15, 8) 1998 #define B_AX_SCH_DBG_SEL_MASK GENMASK(7, 0) 1999 2000 #define R_AX_SCH_DBG 0xC3F8 2001 #define R_AX_SCH_DBG_C1 0xE3F8 2002 #define B_AX_SCHEDULER_DBG_MASK GENMASK(31, 0) 2003 2004 #define R_AX_SCH_EXT_CTRL 0xC3FC 2005 #define R_AX_SCH_EXT_CTRL_C1 0xE3FC 2006 #define B_AX_PORT_RST_TSF_ADV BIT(1) 2007 2008 #define R_AX_PORT_CFG_P0 0xC400 2009 #define R_AX_PORT_CFG_P1 0xC440 2010 #define R_AX_PORT_CFG_P2 0xC480 2011 #define R_AX_PORT_CFG_P3 0xC4C0 2012 #define R_AX_PORT_CFG_P4 0xC500 2013 #define B_AX_BRK_SETUP BIT(16) 2014 #define B_AX_TBTT_UPD_SHIFT_SEL BIT(15) 2015 #define B_AX_BCN_DROP_ALLOW BIT(14) 2016 #define B_AX_TBTT_PROHIB_EN BIT(13) 2017 #define B_AX_BCNTX_EN BIT(12) 2018 #define B_AX_NET_TYPE_MASK GENMASK(11, 10) 2019 #define B_AX_BCN_FORCETX_EN BIT(9) 2020 #define B_AX_TXBCN_BTCCA_EN BIT(8) 2021 #define B_AX_BCNERR_CNT_EN BIT(7) 2022 #define B_AX_BCN_AGRES BIT(6) 2023 #define B_AX_TSFTR_RST BIT(5) 2024 #define B_AX_RX_BSSID_FIT_EN BIT(4) 2025 #define B_AX_TSF_UDT_EN BIT(3) 2026 #define B_AX_PORT_FUNC_EN BIT(2) 2027 #define B_AX_TXBCN_RPT_EN BIT(1) 2028 #define B_AX_RXBCN_RPT_EN BIT(0) 2029 2030 #define R_AX_TBTT_PROHIB_P0 0xC404 2031 #define R_AX_TBTT_PROHIB_P1 0xC444 2032 #define R_AX_TBTT_PROHIB_P2 0xC484 2033 #define R_AX_TBTT_PROHIB_P3 0xC4C4 2034 #define R_AX_TBTT_PROHIB_P4 0xC504 2035 #define B_AX_TBTT_HOLD_MASK GENMASK(27, 16) 2036 #define B_AX_TBTT_SETUP_MASK GENMASK(7, 0) 2037 2038 #define R_AX_BCN_AREA_P0 0xC408 2039 #define R_AX_BCN_AREA_P1 0xC448 2040 #define R_AX_BCN_AREA_P2 0xC488 2041 #define R_AX_BCN_AREA_P3 0xC4C8 2042 #define R_AX_BCN_AREA_P4 0xC508 2043 #define B_AX_BCN_MSK_AREA_MASK GENMASK(27, 16) 2044 #define B_AX_BCN_CTN_AREA_MASK GENMASK(11, 0) 2045 2046 #define R_AX_BCNERLYINT_CFG_P0 0xC40C 2047 #define R_AX_BCNERLYINT_CFG_P1 0xC44C 2048 #define R_AX_BCNERLYINT_CFG_P2 0xC48C 2049 #define R_AX_BCNERLYINT_CFG_P3 0xC4CC 2050 #define R_AX_BCNERLYINT_CFG_P4 0xC50C 2051 #define B_AX_BCNERLY_MASK GENMASK(11, 0) 2052 2053 #define R_AX_TBTTERLYINT_CFG_P0 0xC40E 2054 #define R_AX_TBTTERLYINT_CFG_P1 0xC44E 2055 #define R_AX_TBTTERLYINT_CFG_P2 0xC48E 2056 #define R_AX_TBTTERLYINT_CFG_P3 0xC4CE 2057 #define R_AX_TBTTERLYINT_CFG_P4 0xC50E 2058 #define B_AX_TBTTERLY_MASK GENMASK(11, 0) 2059 2060 #define R_AX_TBTT_AGG_P0 0xC412 2061 #define R_AX_TBTT_AGG_P1 0xC452 2062 #define R_AX_TBTT_AGG_P2 0xC492 2063 #define R_AX_TBTT_AGG_P3 0xC4D2 2064 #define R_AX_TBTT_AGG_P4 0xC512 2065 #define B_AX_TBTT_AGG_NUM_MASK GENMASK(15, 8) 2066 2067 #define R_AX_BCN_SPACE_CFG_P0 0xC414 2068 #define R_AX_BCN_SPACE_CFG_P1 0xC454 2069 #define R_AX_BCN_SPACE_CFG_P2 0xC494 2070 #define R_AX_BCN_SPACE_CFG_P3 0xC4D4 2071 #define R_AX_BCN_SPACE_CFG_P4 0xC514 2072 #define B_AX_SUB_BCN_SPACE_MASK GENMASK(23, 16) 2073 #define B_AX_BCN_SPACE_MASK GENMASK(15, 0) 2074 2075 #define R_AX_BCN_FORCETX_P0 0xC418 2076 #define R_AX_BCN_FORCETX_P1 0xC458 2077 #define R_AX_BCN_FORCETX_P2 0xC498 2078 #define R_AX_BCN_FORCETX_P3 0xC4D8 2079 #define R_AX_BCN_FORCETX_P4 0xC518 2080 #define B_AX_FORCE_BCN_CURRCNT_MASK GENMASK(23, 16) 2081 #define B_AX_FORCE_BCN_NUM_MASK GENMASK(15, 0) 2082 #define B_AX_BCN_MAX_ERR_MASK GENMASK(7, 0) 2083 2084 #define R_AX_BCN_ERR_CNT_P0 0xC420 2085 #define R_AX_BCN_ERR_CNT_P1 0xC460 2086 #define R_AX_BCN_ERR_CNT_P2 0xC4A0 2087 #define R_AX_BCN_ERR_CNT_P3 0xC4E0 2088 #define R_AX_BCN_ERR_CNT_P4 0xC520 2089 #define B_AX_BCN_ERR_CNT_SUM_MASK GENMASK(31, 24) 2090 #define B_AX_BCN_ERR_CNT_NAV_MASK GENMASK(23, 16) 2091 #define B_AX_BCN_ERR_CNT_EDCCA_MASK GENMASK(15, 0) 2092 #define B_AX_BCN_ERR_CNT_CCA_MASK GENMASK(7, 0) 2093 2094 #define R_AX_BCN_ERR_FLAG_P0 0xC424 2095 #define R_AX_BCN_ERR_FLAG_P1 0xC464 2096 #define R_AX_BCN_ERR_FLAG_P2 0xC4A4 2097 #define R_AX_BCN_ERR_FLAG_P3 0xC4E4 2098 #define R_AX_BCN_ERR_FLAG_P4 0xC524 2099 #define B_AX_BCN_ERR_FLAG_OTHERS BIT(6) 2100 #define B_AX_BCN_ERR_FLAG_MAC BIT(5) 2101 #define B_AX_BCN_ERR_FLAG_TXON BIT(4) 2102 #define B_AX_BCN_ERR_FLAG_SRCHEND BIT(3) 2103 #define B_AX_BCN_ERR_FLAG_INVALID BIT(2) 2104 #define B_AX_BCN_ERR_FLAG_CMP BIT(1) 2105 #define B_AX_BCN_ERR_FLAG_LOCK BIT(0) 2106 2107 #define R_AX_DTIM_CTRL_P0 0xC426 2108 #define R_AX_DTIM_CTRL_P1 0xC466 2109 #define R_AX_DTIM_CTRL_P2 0xC4A6 2110 #define R_AX_DTIM_CTRL_P3 0xC4E6 2111 #define R_AX_DTIM_CTRL_P4 0xC526 2112 #define B_AX_DTIM_NUM_MASK GENMASK(15, 8) 2113 #define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0) 2114 2115 #define R_AX_TBTT_SHIFT_P0 0xC428 2116 #define R_AX_TBTT_SHIFT_P1 0xC468 2117 #define R_AX_TBTT_SHIFT_P2 0xC4A8 2118 #define R_AX_TBTT_SHIFT_P3 0xC4E8 2119 #define R_AX_TBTT_SHIFT_P4 0xC528 2120 #define B_AX_TBTT_SHIFT_OFST_MASK GENMASK(11, 0) 2121 #define B_AX_TBTT_SHIFT_OFST_SIGN BIT(11) 2122 #define B_AX_TBTT_SHIFT_OFST_MAG GENMASK(10, 0) 2123 2124 #define R_AX_BCN_CNT_TMR_P0 0xC434 2125 #define R_AX_BCN_CNT_TMR_P1 0xC474 2126 #define R_AX_BCN_CNT_TMR_P2 0xC4B4 2127 #define R_AX_BCN_CNT_TMR_P3 0xC4F4 2128 #define R_AX_BCN_CNT_TMR_P4 0xC534 2129 #define B_AX_BCN_CNT_TMR_MASK GENMASK(31, 0) 2130 2131 #define R_AX_TSFTR_LOW_P0 0xC438 2132 #define R_AX_TSFTR_LOW_P1 0xC478 2133 #define R_AX_TSFTR_LOW_P2 0xC4B8 2134 #define R_AX_TSFTR_LOW_P3 0xC4F8 2135 #define R_AX_TSFTR_LOW_P4 0xC538 2136 #define B_AX_TSFTR_LOW_MASK GENMASK(31, 0) 2137 2138 #define R_AX_TSFTR_HIGH_P0 0xC43C 2139 #define R_AX_TSFTR_HIGH_P1 0xC47C 2140 #define R_AX_TSFTR_HIGH_P2 0xC4BC 2141 #define R_AX_TSFTR_HIGH_P3 0xC4FC 2142 #define R_AX_TSFTR_HIGH_P4 0xC53C 2143 #define B_AX_TSFTR_HIGH_MASK GENMASK(31, 0) 2144 2145 #define R_AX_MBSSID_CTRL 0xC568 2146 #define R_AX_MBSSID_CTRL_C1 0xE568 2147 #define B_AX_P0MB_ALL_MASK GENMASK(23, 1) 2148 #define B_AX_P0MB_NUM_MASK GENMASK(19, 16) 2149 #define B_AX_P0MB15_EN BIT(15) 2150 #define B_AX_P0MB14_EN BIT(14) 2151 #define B_AX_P0MB13_EN BIT(13) 2152 #define B_AX_P0MB12_EN BIT(12) 2153 #define B_AX_P0MB11_EN BIT(11) 2154 #define B_AX_P0MB10_EN BIT(10) 2155 #define B_AX_P0MB9_EN BIT(9) 2156 #define B_AX_P0MB8_EN BIT(8) 2157 #define B_AX_P0MB7_EN BIT(7) 2158 #define B_AX_P0MB6_EN BIT(6) 2159 #define B_AX_P0MB5_EN BIT(5) 2160 #define B_AX_P0MB4_EN BIT(4) 2161 #define B_AX_P0MB3_EN BIT(3) 2162 #define B_AX_P0MB2_EN BIT(2) 2163 #define B_AX_P0MB1_EN BIT(1) 2164 2165 #define R_AX_P0MB_HGQ_WINDOW_CFG_0 0xC590 2166 #define R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 0xE590 2167 #define R_AX_PORT_HGQ_WINDOW_CFG 0xC5A0 2168 #define R_AX_PORT_HGQ_WINDOW_CFG_C1 0xE5A0 2169 2170 #define R_AX_PTCL_COMMON_SETTING_0 0xC600 2171 #define R_AX_PTCL_COMMON_SETTING_0_C1 0xE600 2172 #define B_AX_PCIE_MODE_MASK GENMASK(15, 14) 2173 #define B_AX_CPUMGQ_LIFETIME_EN BIT(8) 2174 #define B_AX_MGQ_LIFETIME_EN BIT(7) 2175 #define B_AX_LIFETIME_EN BIT(6) 2176 #define B_AX_PTCL_TRIGGER_SS_EN_UL BIT(4) 2177 #define B_AX_PTCL_TRIGGER_SS_EN_1 BIT(3) 2178 #define B_AX_PTCL_TRIGGER_SS_EN_0 BIT(2) 2179 #define B_AX_CMAC_TX_MODE_1 BIT(1) 2180 #define B_AX_CMAC_TX_MODE_0 BIT(0) 2181 2182 #define R_AX_AMPDU_AGG_LIMIT 0xC610 2183 #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24) 2184 #define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16) 2185 #define B_AX_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8) 2186 #define B_AX_MAX_AGG_NUM_MASK GENMASK(7, 0) 2187 2188 #define R_AX_AGG_LEN_HT_0 0xC614 2189 #define R_AX_AGG_LEN_HT_0_C1 0xE614 2190 #define B_AX_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16) 2191 #define B_AX_RTS_TXTIME_TH_MASK GENMASK(15, 8) 2192 #define B_AX_RTS_LEN_TH_MASK GENMASK(7, 0) 2193 2194 #define S_AX_CTS2S_TH_SEC_256B 1 2195 #define R_AX_SIFS_SETTING 0xC624 2196 #define R_AX_SIFS_SETTING_C1 0xE624 2197 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24) 2198 #define B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18) 2199 #define B_AX_HW_CTS2SELF_EN BIT(16) 2200 #define B_AX_SPEC_SIFS_OFDM_PTCL_SH 8 2201 #define B_AX_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8) 2202 #define B_AX_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0) 2203 #define S_AX_CTS2S_TH_1K 4 2204 2205 #define R_AX_TXRATE_CHK 0xC628 2206 #define R_AX_TXRATE_CHK_C1 0xE628 2207 #define B_AX_DEFT_RATE_MASK GENMASK(15, 7) 2208 #define B_AX_BAND_MODE BIT(4) 2209 #define B_AX_MAX_TXNSS_MASK GENMASK(3, 2) 2210 #define B_AX_RTS_LIMIT_IN_OFDM6 BIT(1) 2211 #define B_AX_CHECK_CCK_EN BIT(0) 2212 2213 #define R_AX_TXCNT 0xC62C 2214 #define R_AX_TXCNT_C1 0xE62C 2215 #define B_AX_ADD_TXCNT_BY BIT(31) 2216 #define B_AX_S_TXCNT_LMT_MASK GENMASK(29, 24) 2217 #define B_AX_L_TXCNT_LMT_MASK GENMASK(21, 16) 2218 2219 #define R_AX_MBSSID_DROP_0 0xC63C 2220 #define R_AX_MBSSID_DROP_0_C1 0xE63C 2221 #define B_AX_GI_LTF_FB_SEL BIT(30) 2222 #define B_AX_RATE_SEL_MASK GENMASK(29, 24) 2223 #define B_AX_PORT_DROP_4_0_MASK GENMASK(20, 16) 2224 #define B_AX_MBSSID_DROP_15_0_MASK GENMASK(15, 0) 2225 2226 #define R_AX_PTCLRPT_FULL_HDL 0xC660 2227 #define R_AX_PTCLRPT_FULL_HDL_C1 0xE660 2228 #define B_AX_RPT_LATCH_PHY_TIME_MASK GENMASK(15, 12) 2229 #define B_AX_F2PCMD_FWWD_RLS_MODE BIT(9) 2230 #define B_AX_F2PCMD_RPT_EN BIT(8) 2231 #define B_AX_BCN_RPT_PATH_MASK GENMASK(7, 6) 2232 #define B_AX_SPE_RPT_PATH_MASK GENMASK(5, 4) 2233 #define FWD_TO_WLCPU 1 2234 #define B_AX_TX_RPT_PATH_MASK GENMASK(3, 2) 2235 #define B_AX_F2PCMDRPT_FULL_DROP BIT(1) 2236 #define B_AX_NON_F2PCMDRPT_FULL_DROP BIT(0) 2237 2238 #define R_AX_BT_PLT 0xC67C 2239 #define R_AX_BT_PLT_C1 0xE67C 2240 #define B_AX_BT_PLT_PKT_CNT_MASK GENMASK(31, 16) 2241 #define B_AX_BT_PLT_RST BIT(9) 2242 #define B_AX_PLT_EN BIT(8) 2243 #define B_AX_RX_PLT_GNT_LTE_RX BIT(7) 2244 #define B_AX_RX_PLT_GNT_BT_RX BIT(6) 2245 #define B_AX_RX_PLT_GNT_BT_TX BIT(5) 2246 #define B_AX_RX_PLT_GNT_WL BIT(4) 2247 #define B_AX_TX_PLT_GNT_LTE_RX BIT(3) 2248 #define B_AX_TX_PLT_GNT_BT_RX BIT(2) 2249 #define B_AX_TX_PLT_GNT_BT_TX BIT(1) 2250 #define B_AX_TX_PLT_GNT_WL BIT(0) 2251 2252 #define R_AX_PTCL_BSS_COLOR_0 0xC6A0 2253 #define R_AX_PTCL_BSS_COLOR_0_C1 0xE6A0 2254 #define B_AX_BSS_COLOB_AX_PORT_3_MASK GENMASK(29, 24) 2255 #define B_AX_BSS_COLOB_AX_PORT_2_MASK GENMASK(21, 16) 2256 #define B_AX_BSS_COLOB_AX_PORT_1_MASK GENMASK(13, 8) 2257 #define B_AX_BSS_COLOB_AX_PORT_0_MASK GENMASK(5, 0) 2258 2259 #define R_AX_PTCL_BSS_COLOR_1 0xC6A4 2260 #define R_AX_PTCL_BSS_COLOR_1_C1 0xE6A4 2261 #define B_AX_BSS_COLOB_AX_PORT_4_MASK GENMASK(5, 0) 2262 2263 #define R_AX_PTCL_IMR0 0xC6C0 2264 #define R_AX_PTCL_IMR0_C1 0xE6C0 2265 #define B_AX_F2PCMD_PKTID_ERR_INT_EN BIT(31) 2266 #define B_AX_F2PCMD_RD_PKTID_ERR_INT_EN BIT(30) 2267 #define B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN BIT(29) 2268 #define B_AX_F2PCMD_USER_ALLC_ERR_INT_EN BIT(28) 2269 #define B_AX_RX_SPF_U0_PKTID_ERR_INT_EN BIT(27) 2270 #define B_AX_TX_SPF_U1_PKTID_ERR_INT_EN BIT(26) 2271 #define B_AX_TX_SPF_U2_PKTID_ERR_INT_EN BIT(25) 2272 #define B_AX_TX_SPF_U3_PKTID_ERR_INT_EN BIT(24) 2273 #define B_AX_TX_RECORD_PKTID_ERR_INT_EN BIT(23) 2274 #define B_AX_F2PCMD_EMPTY_ERR_INT_EN BIT(15) 2275 #define B_AX_TWTSP_QSEL_ERR_INT_EN BIT(14) 2276 #define B_AX_BCNQ_ORDER_ERR_INT_EN BIT(12) 2277 #define B_AX_Q_PKTID_ERR_INT_EN BIT(11) 2278 #define B_AX_D_PKTID_ERR_INT_EN BIT(10) 2279 #define B_AX_TXPRT_FULL_DROP_ERR_INT_EN BIT(9) 2280 #define B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN BIT(8) 2281 #define B_AX_FSM1_TIMEOUT_ERR_INT_EN BIT(1) 2282 #define B_AX_FSM_TIMEOUT_ERR_INT_EN BIT(0) 2283 #define B_AX_PTCL_IMR_CLR_ALL GENMASK(31, 0) 2284 #define B_AX_PTCL_IMR_CLR (B_AX_FSM_TIMEOUT_ERR_INT_EN | \ 2285 B_AX_F2PCMDRPT_FULL_DROP_ERR_INT_EN | \ 2286 B_AX_TXPRT_FULL_DROP_ERR_INT_EN | \ 2287 B_AX_D_PKTID_ERR_INT_EN | \ 2288 B_AX_Q_PKTID_ERR_INT_EN | \ 2289 B_AX_BCNQ_ORDER_ERR_INT_EN | \ 2290 B_AX_TWTSP_QSEL_ERR_INT_EN | \ 2291 B_AX_F2PCMD_EMPTY_ERR_INT_EN | \ 2292 B_AX_TX_RECORD_PKTID_ERR_INT_EN | \ 2293 B_AX_TX_SPF_U3_PKTID_ERR_INT_EN | \ 2294 B_AX_TX_SPF_U2_PKTID_ERR_INT_EN | \ 2295 B_AX_TX_SPF_U1_PKTID_ERR_INT_EN | \ 2296 B_AX_RX_SPF_U0_PKTID_ERR_INT_EN | \ 2297 B_AX_F2PCMD_USER_ALLC_ERR_INT_EN | \ 2298 B_AX_F2PCMD_ASSIGN_PKTID_ERR_INT_EN | \ 2299 B_AX_F2PCMD_RD_PKTID_ERR_INT_EN | \ 2300 B_AX_F2PCMD_PKTID_ERR_INT_EN) 2301 #define B_AX_PTCL_IMR_SET (B_AX_FSM_TIMEOUT_ERR_INT_EN | \ 2302 B_AX_TX_RECORD_PKTID_ERR_INT_EN | \ 2303 B_AX_F2PCMD_USER_ALLC_ERR_INT_EN) 2304 #define B_AX_PTCL_IMR_CLR_V1 (B_AX_FSM1_TIMEOUT_ERR_INT_EN | \ 2305 B_AX_FSM_TIMEOUT_ERR_INT_EN) 2306 #define B_AX_PTCL_IMR_SET_V1 (B_AX_FSM1_TIMEOUT_ERR_INT_EN | \ 2307 B_AX_FSM_TIMEOUT_ERR_INT_EN) 2308 2309 #define R_AX_PTCL_ISR0 0xC6C4 2310 #define R_AX_PTCL_ISR0_C1 0xE6C4 2311 2312 #define S_AX_PTCL_TO_2MS 0x3F 2313 #define R_AX_PTCL_FSM_MON 0xC6E8 2314 #define R_AX_PTCL_FSM_MON_C1 0xE6E8 2315 #define B_AX_PTCL_TX_ARB_TO_MODE BIT(6) 2316 #define B_AX_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0) 2317 2318 #define R_AX_PTCL_TX_CTN_SEL 0xC6EC 2319 #define R_AX_PTCL_TX_CTN_SEL_C1 0xE6EC 2320 #define B_AX_PTCL_TX_ON_STAT BIT(7) 2321 2322 #define R_AX_PTCL_DBG_INFO 0xC6F0 2323 #define R_AX_PTCL_DBG_INFO_C1 0xE6F0 2324 #define B_AX_PTCL_DBG_INFO_MASK GENMASK(31, 0) 2325 #define R_AX_PTCL_DBG 0xC6F4 2326 #define R_AX_PTCL_DBG_C1 0xE6F4 2327 #define B_AX_PTCL_DBG_EN BIT(8) 2328 #define B_AX_PTCL_DBG_SEL_MASK GENMASK(7, 0) 2329 2330 #define R_AX_DLE_CTRL 0xC800 2331 #define R_AX_DLE_CTRL_C1 0xE800 2332 #define B_AX_NO_RESERVE_PAGE_ERR_IMR BIT(23) 2333 #define B_AX_RXDATA_FSM_HANG_ERROR_IMR BIT(15) 2334 #define B_AX_RXSTS_FSM_HANG_ERROR_IMR BIT(14) 2335 #define B_AX_DLE_IMR_CLR (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \ 2336 B_AX_RXDATA_FSM_HANG_ERROR_IMR | \ 2337 B_AX_NO_RESERVE_PAGE_ERR_IMR) 2338 #define B_AX_DLE_IMR_SET (B_AX_RXSTS_FSM_HANG_ERROR_IMR | \ 2339 B_AX_RXDATA_FSM_HANG_ERROR_IMR) 2340 2341 #define R_AX_RXDMA_CTRL_0 0xC804 2342 #define R_AX_RXDMA_CTRL_0_C1 0xE804 2343 #define B_AX_RXDMA_DBGOUT_EN BIT(31) 2344 #define B_AX_RXDMA_DBG_SEL_MASK GENMASK(30, 29) 2345 #define B_AX_RXDMA_FIFO_DBG_SEL_MASK GENMASK(28, 25) 2346 #define B_AX_RXDMA_DEFAULT_PAGE_MASK GENMASK(22, 21) 2347 #define B_AX_RXDMA_BUFF_REQ_PRI_MASK GENMASK(20, 19) 2348 #define B_AX_RXDMA_TGT_QUEID_MASK GENMASK(18, 13) 2349 #define B_AX_RXDMA_TGT_PRID_MASK GENMASK(12, 10) 2350 #define B_AX_RXDMA_DIS_CSI_RELEASE BIT(9) 2351 #define B_AX_RXDMA_DIS_RXSTS_WAIT_PTR_CLR BIT(7) 2352 #define B_AX_RXDMA_DIS_CSI_WAIT_PTR_CLR BIT(6) 2353 #define B_AX_RXSTS_PTR_FULL_MODE BIT(5) 2354 #define B_AX_CSI_PTR_FULL_MODE BIT(4) 2355 #define B_AX_RU3_PTR_FULL_MODE BIT(3) 2356 #define B_AX_RU2_PTR_FULL_MODE BIT(2) 2357 #define B_AX_RU1_PTR_FULL_MODE BIT(1) 2358 #define B_AX_RU0_PTR_FULL_MODE BIT(0) 2359 #define RX_FULL_MODE (B_AX_RU0_PTR_FULL_MODE | B_AX_RU1_PTR_FULL_MODE | \ 2360 B_AX_RU2_PTR_FULL_MODE | B_AX_RU3_PTR_FULL_MODE | \ 2361 B_AX_CSI_PTR_FULL_MODE | B_AX_RXSTS_PTR_FULL_MODE) 2362 2363 #define R_AX_RXDMA_PKT_INFO_0 0xC814 2364 #define R_AX_RXDMA_PKT_INFO_1 0xC818 2365 #define R_AX_RXDMA_PKT_INFO_2 0xC81C 2366 2367 #define R_AX_RX_ERR_FLAG_IMR 0xC804 2368 #define R_AX_RX_ERR_FLAG_IMR_C1 0xE804 2369 #define B_AX_RX_GET_NULL_PKT_ERR_MSK BIT(30) 2370 #define B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK BIT(29) 2371 #define B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK BIT(28) 2372 #define B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK BIT(27) 2373 #define B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK BIT(26) 2374 #define B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK BIT(25) 2375 #define B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK BIT(24) 2376 #define B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK BIT(23) 2377 #define B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK BIT(22) 2378 #define B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK BIT(21) 2379 #define B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK BIT(20) 2380 #define B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK BIT(19) 2381 #define B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK BIT(18) 2382 #define B_AX_RX_RU0_ZERO_LEN_ERR_MSK BIT(17) 2383 #define B_AX_RX_RU1_ZERO_LEN_ERR_MSK BIT(16) 2384 #define B_AX_RX_RU2_ZERO_LEN_ERR_MSK BIT(15) 2385 #define B_AX_RX_RU3_ZERO_LEN_ERR_MSK BIT(14) 2386 #define B_AX_RX_RU4_ZERO_LEN_ERR_MSK BIT(13) 2387 #define B_AX_RX_RU5_ZERO_LEN_ERR_MSK BIT(12) 2388 #define B_AX_RX_RU6_ZERO_LEN_ERR_MSK BIT(11) 2389 #define B_AX_RX_RU7_ZERO_LEN_ERR_MSK BIT(10) 2390 #define B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK BIT(9) 2391 #define B_AX_RX_CSI_ZERO_LEN_ERR_MSK BIT(8) 2392 #define B_AX_PLE_DATA_OPT_FSM_HANG_MSK BIT(7) 2393 #define B_AX_PLE_RXDATA_REQ_BUF_FSM_HANG_MSK BIT(6) 2394 #define B_AX_PLE_TXRPT_REQ_BUF_FSM_HANG_MSK BIT(5) 2395 #define B_AX_PLE_WD_OPT_FSM_HANG_MSK BIT(4) 2396 #define B_AX_PLE_ENQ_FSM_HANG_MSK BIT(3) 2397 #define B_AX_RXDATA_ENQUE_ORDER_ERR_MSK BIT(2) 2398 #define B_AX_RXSTS_ENQUE_ORDER_ERR_MSK BIT(1) 2399 #define B_AX_RX_CSI_PKT_NUM_ERR_MSK BIT(0) 2400 #define B_AX_RX_ERR_IMR_CLR_V1 (B_AX_RXSTS_ENQUE_ORDER_ERR_MSK | \ 2401 B_AX_RXDATA_ENQUE_ORDER_ERR_MSK | \ 2402 B_AX_RX_CSI_ZERO_LEN_ERR_MSK | \ 2403 B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK | \ 2404 B_AX_RX_RU7_ZERO_LEN_ERR_MSK | \ 2405 B_AX_RX_RU6_ZERO_LEN_ERR_MSK | \ 2406 B_AX_RX_RU5_ZERO_LEN_ERR_MSK | \ 2407 B_AX_RX_RU4_ZERO_LEN_ERR_MSK | \ 2408 B_AX_RX_RU3_ZERO_LEN_ERR_MSK | \ 2409 B_AX_RX_RU2_ZERO_LEN_ERR_MSK | \ 2410 B_AX_RX_RU1_ZERO_LEN_ERR_MSK | \ 2411 B_AX_RX_RU0_ZERO_LEN_ERR_MSK | \ 2412 B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK | \ 2413 B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK | \ 2414 B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK | \ 2415 B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK | \ 2416 B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK | \ 2417 B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK | \ 2418 B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK | \ 2419 B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK | \ 2420 B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK | \ 2421 B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK | \ 2422 B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK | \ 2423 B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK | \ 2424 B_AX_RX_GET_NULL_PKT_ERR_MSK) 2425 #define B_AX_RX_ERR_IMR_SET_V1 (B_AX_RXSTS_ENQUE_ORDER_ERR_MSK | \ 2426 B_AX_RXDATA_ENQUE_ORDER_ERR_MSK | \ 2427 B_AX_RX_CSI_ZERO_LEN_ERR_MSK | \ 2428 B_AX_RX_RXSTS_ZERO_LEN_ERR_MSK | \ 2429 B_AX_RX_RU7_ZERO_LEN_ERR_MSK | \ 2430 B_AX_RX_RU6_ZERO_LEN_ERR_MSK | \ 2431 B_AX_RX_RU5_ZERO_LEN_ERR_MSK | \ 2432 B_AX_RX_RU4_ZERO_LEN_ERR_MSK | \ 2433 B_AX_RX_RU3_ZERO_LEN_ERR_MSK | \ 2434 B_AX_RX_RU2_ZERO_LEN_ERR_MSK | \ 2435 B_AX_RX_RU1_ZERO_LEN_ERR_MSK | \ 2436 B_AX_RX_RU0_ZERO_LEN_ERR_MSK | \ 2437 B_AX_RX_F2PCMD_FSM_HANG_MSK_ERR_MSK | \ 2438 B_AX_RX_TXRPT_FSM_HANG_MSK_ERR_MSK | \ 2439 B_AX_RX_CSI_FSM_HANG_MSK_ERR_MSK | \ 2440 B_AX_RX_RXSTS_FSM_HANG_MSK_ERR_MSK | \ 2441 B_AX_RX_RU7_FSM_HANG_MSK_ERR_MSK | \ 2442 B_AX_RX_RU6_FSM_HANG_MSK_ERR_MSK | \ 2443 B_AX_RX_RU5_FSM_HANG_MSK_ERR_MSK | \ 2444 B_AX_RX_RU4_FSM_HANG_MSK_ERR_MSK | \ 2445 B_AX_RX_RU3_FSM_HANG_MSK_ERR_MSK | \ 2446 B_AX_RX_RU2_FSM_HANG_MSK_ERR_MSK | \ 2447 B_AX_RX_RU1_FSM_HANG_MSK_ERR_MSK | \ 2448 B_AX_RX_RU0_FSM_HANG_MSK_ERR_MSK | \ 2449 B_AX_RX_GET_NULL_PKT_ERR_MSK) 2450 2451 #define R_AX_TX_ERR_FLAG_IMR 0xC870 2452 #define R_AX_TX_ERR_FLAG_IMR_C1 0xE870 2453 #define B_AX_TX_RU0_FSM_HANG_ERR_MSK BIT(31) 2454 #define B_AX_TX_RU1_FSM_HANG_ERR_MSK BIT(30) 2455 #define B_AX_TX_RU2_FSM_HANG_ERR_MSK BIT(29) 2456 #define B_AX_TX_RU3_FSM_HANG_ERR_MSK BIT(28) 2457 #define B_AX_TX_RU4_FSM_HANG_ERR_MSK BIT(27) 2458 #define B_AX_TX_RU5_FSM_HANG_ERR_MSK BIT(26) 2459 #define B_AX_TX_RU6_FSM_HANG_ERR_MSK BIT(25) 2460 #define B_AX_TX_RU7_FSM_HANG_ERR_MSK BIT(24) 2461 #define B_AX_TX_RU8_FSM_HANG_ERR_MSK BIT(23) 2462 #define B_AX_TX_RU9_FSM_HANG_ERR_MSK BIT(22) 2463 #define B_AX_TX_RU10_FSM_HANG_ERR_MSK BIT(21) 2464 #define B_AX_TX_RU11_FSM_HANG_ERR_MSK BIT(20) 2465 #define B_AX_TX_RU12_FSM_HANG_ERR_MSK BIT(19) 2466 #define B_AX_TX_RU13_FSM_HANG_ERR_MSK BIT(18) 2467 #define B_AX_TX_RU14_FSM_HANG_ERR_MSK BIT(17) 2468 #define B_AX_TX_RU15_FSM_HANG_ERR_MSK BIT(16) 2469 #define B_AX_TX_CSI_FSM_HANG_ERR_MSK BIT(15) 2470 #define B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK BIT(14) 2471 #define B_AX_TX_ERR_IMR_CLR_V1 (B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK | \ 2472 B_AX_TX_CSI_FSM_HANG_ERR_MSK | \ 2473 B_AX_TX_RU7_FSM_HANG_ERR_MSK | \ 2474 B_AX_TX_RU6_FSM_HANG_ERR_MSK | \ 2475 B_AX_TX_RU5_FSM_HANG_ERR_MSK | \ 2476 B_AX_TX_RU4_FSM_HANG_ERR_MSK | \ 2477 B_AX_TX_RU3_FSM_HANG_ERR_MSK | \ 2478 B_AX_TX_RU2_FSM_HANG_ERR_MSK | \ 2479 B_AX_TX_RU1_FSM_HANG_ERR_MSK | \ 2480 B_AX_TX_RU0_FSM_HANG_ERR_MSK) 2481 #define B_AX_TX_ERR_IMR_SET_V1 (B_AX_TX_WD_PLD_ID_FSM_HANG_ERR_MSK | \ 2482 B_AX_TX_CSI_FSM_HANG_ERR_MSK | \ 2483 B_AX_TX_RU7_FSM_HANG_ERR_MSK | \ 2484 B_AX_TX_RU6_FSM_HANG_ERR_MSK | \ 2485 B_AX_TX_RU5_FSM_HANG_ERR_MSK | \ 2486 B_AX_TX_RU4_FSM_HANG_ERR_MSK | \ 2487 B_AX_TX_RU3_FSM_HANG_ERR_MSK | \ 2488 B_AX_TX_RU2_FSM_HANG_ERR_MSK | \ 2489 B_AX_TX_RU1_FSM_HANG_ERR_MSK | \ 2490 B_AX_TX_RU0_FSM_HANG_ERR_MSK) 2491 2492 #define R_AX_TCR0 0xCA00 2493 #define R_AX_TCR0_C1 0xEA00 2494 #define B_AX_TCR_ZLD_NUM_MASK GENMASK(31, 24) 2495 #define B_AX_TCR_UDF_EN BIT(23) 2496 #define B_AX_TCR_UDF_THSD_MASK GENMASK(22, 16) 2497 #define TCR_UDF_THSD 0x6 2498 #define B_AX_TCR_ERRSTEN_MASK GENMASK(15, 10) 2499 #define B_AX_TCR_VHTSIGA1_TXPS BIT(9) 2500 #define B_AX_TCR_PLCP_ERRHDL_EN BIT(8) 2501 #define B_AX_TCR_PADSEL BIT(7) 2502 #define B_AX_TCR_MASK_SIGBCRC BIT(6) 2503 #define B_AX_TCR_SR_VAL15_ALLOW BIT(5) 2504 #define B_AX_TCR_EN_EOF BIT(4) 2505 #define B_AX_TCR_EN_SCRAM_INC BIT(3) 2506 #define B_AX_TCR_EN_20MST BIT(2) 2507 #define B_AX_TCR_CRC BIT(1) 2508 #define B_AX_TCR_DISGCLK BIT(0) 2509 2510 #define R_AX_TCR1 0xCA04 2511 #define R_AX_TCR1_C1 0xEA04 2512 #define B_AX_TXDFIFO_THRESHOLD GENMASK(31, 28) 2513 #define B_AX_TCR_CCK_LOCK_CLK BIT(27) 2514 #define B_AX_TCR_FORCE_READ_TXDFIFO BIT(26) 2515 #define B_AX_TCR_USTIME GENMASK(23, 16) 2516 #define B_AX_TCR_SMOOTH_VAL BIT(15) 2517 #define B_AX_TCR_SMOOTH_CTRL BIT(14) 2518 #define B_AX_CS_REQ_VAL BIT(13) 2519 #define B_AX_CS_REQ_SEL BIT(12) 2520 #define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8) 2521 #define B_AX_TCR_TXTIMEOUT GENMASK(7, 0) 2522 2523 #define R_AX_MD_TSFT_STMP_CTL 0xCA08 2524 #define R_AX_MD_TSFT_STMP_CTL_C1 0xEA08 2525 #define B_AX_TSFT_OFS_MASK GENMASK(31, 16) 2526 #define B_AX_STMP_THSD_MASK GENMASK(15, 8) 2527 #define B_AX_UPD_HGQMD BIT(1) 2528 #define B_AX_UPD_TIMIE BIT(0) 2529 2530 #define R_AX_PPWRBIT_SETTING 0xCA0C 2531 #define R_AX_PPWRBIT_SETTING_C1 0xEA0C 2532 2533 #define R_AX_TXD_FIFO_CTRL 0xCA1C 2534 #define R_AX_TXD_FIFO_CTRL_C1 0xEA1C 2535 #define B_AX_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(28, 24) 2536 #define B_AX_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(20, 16) 2537 #define B_AX_TXDFIFO_HIGH_MCS_THRE_MASK GENMASK(15, 12) 2538 #define TXDFIFO_HIGH_MCS_THRE 0x7 2539 #define B_AX_TXDFIFO_LOW_MCS_THRE_MASK GENMASK(11, 8) 2540 #define TXDFIFO_LOW_MCS_THRE 0x7 2541 #define B_AX_HIGH_MCS_PHY_RATE_MASK GENMASK(7, 4) 2542 #define B_AX_BW_PHY_RATE_MASK GENMASK(1, 0) 2543 2544 #define R_AX_MACTX_DBG_SEL_CNT 0xCA20 2545 #define R_AX_MACTX_DBG_SEL_CNT_C1 0xEA20 2546 #define B_AX_MACTX_MPDU_CNT GENMASK(31, 24) 2547 #define B_AX_MACTX_DMA_CNT GENMASK(23, 16) 2548 #define B_AX_LENGTH_ERR_FLAG_U3 BIT(11) 2549 #define B_AX_LENGTH_ERR_FLAG_U2 BIT(10) 2550 #define B_AX_LENGTH_ERR_FLAG_U1 BIT(9) 2551 #define B_AX_LENGTH_ERR_FLAG_U0 BIT(8) 2552 #define B_AX_DBGSEL_MACTX_MASK GENMASK(5, 0) 2553 2554 #define R_AX_WMAC_TX_CTRL_DEBUG 0xCAE4 2555 #define R_AX_WMAC_TX_CTRL_DEBUG_C1 0xEAE4 2556 #define B_AX_TX_CTRL_DEBUG_SEL_MASK GENMASK(3, 0) 2557 2558 #define R_AX_WMAC_TX_INFO0_DEBUG 0xCAE8 2559 #define R_AX_WMAC_TX_INFO0_DEBUG_C1 0xEAE8 2560 #define B_AX_TX_CTRL_INFO_P0_MASK GENMASK(31, 0) 2561 2562 #define R_AX_WMAC_TX_INFO1_DEBUG 0xCAEC 2563 #define R_AX_WMAC_TX_INFO1_DEBUG_C1 0xEAEC 2564 #define B_AX_TX_CTRL_INFO_P1_MASK GENMASK(31, 0) 2565 2566 #define R_AX_RSP_CHK_SIG 0xCC00 2567 #define R_AX_RSP_CHK_SIG_C1 0xEC00 2568 #define B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN BIT(30) 2569 #define B_AX_RSP_TBPPDU_CHK_PWR BIT(29) 2570 #define B_AX_RSP_CHK_BASIC_NAV BIT(21) 2571 #define B_AX_RSP_CHK_INTRA_NAV BIT(20) 2572 #define B_AX_RSP_CHK_TXNAV BIT(19) 2573 #define B_AX_TXDATA_END_PS_OPT BIT(18) 2574 #define B_AX_CHECK_SOUNDING_SEQ BIT(17) 2575 #define B_AX_RXBA_IGNOREA2 BIT(16) 2576 #define B_AX_ACKTO_CCK_MASK GENMASK(15, 8) 2577 #define B_AX_ACKTO_MASK GENMASK(7, 0) 2578 2579 #define R_AX_TRXPTCL_RESP_0 0xCC04 2580 #define R_AX_TRXPTCL_RESP_0_C1 0xEC04 2581 #define B_AX_WMAC_RESP_STBC_EN BIT(31) 2582 #define B_AX_WMAC_RXFTM_TXACK_SC BIT(30) 2583 #define B_AX_WMAC_RXFTM_TXACKBWEQ BIT(29) 2584 #define B_AX_RSP_CHK_SEC_CCA_80 BIT(28) 2585 #define B_AX_RSP_CHK_SEC_CCA_40 BIT(27) 2586 #define B_AX_RSP_CHK_SEC_CCA_20 BIT(26) 2587 #define B_AX_RSP_CHK_BTCCA BIT(25) 2588 #define B_AX_RSP_CHK_EDCCA BIT(24) 2589 #define B_AX_RSP_CHK_CCA BIT(23) 2590 #define B_AX_WMAC_LDPC_EN BIT(22) 2591 #define B_AX_WMAC_SGIEN BIT(21) 2592 #define B_AX_WMAC_SPLCPEN BIT(20) 2593 #define B_AX_WMAC_BESP_EARLY_TXBA BIT(17) 2594 #define B_AX_WMAC_SPEC_SIFS_OFDM_MASK GENMASK(15, 8) 2595 #define B_AX_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0) 2596 #define WMAC_SPEC_SIFS_OFDM_52A 0x15 2597 #define WMAC_SPEC_SIFS_OFDM_52B 0x11 2598 #define WMAC_SPEC_SIFS_OFDM_52C 0x11 2599 #define WMAC_SPEC_SIFS_CCK 0xA 2600 2601 #define R_AX_TRXPTCL_RRSR_CTL_0 0xCC08 2602 #define R_AX_TRXPTCL_RRSR_CTL_0_C1 0xEC08 2603 #define B_AX_RESP_TX_MACID_CCA_TH_EN BIT(31) 2604 #define B_AX_RESP_TX_PWRMODE_MASK GENMASK(30, 28) 2605 #define B_AX_FTM_RRSR_RATE_EN_MASK GENMASK(27, 24) 2606 #define B_AX_NESS_MASK GENMASK(23, 22) 2607 #define B_AX_WMAC_RESP_DOPPLEB_AX_EN BIT(21) 2608 #define B_AX_WMAC_RESP_DCM_EN BIT(20) 2609 #define B_AX_WMAC_RRSB_AX_CCK_MASK GENMASK(19, 16) 2610 #define B_AX_WMAC_RESP_RATE_EN_MASK GENMASK(15, 12) 2611 #define B_AX_WMAC_RESP_RSC_MASK GENMASK(11, 10) 2612 #define B_AX_WMAC_RESP_REF_RATE_SEL BIT(9) 2613 #define B_AX_WMAC_RESP_REF_RATE_MASK GENMASK(8, 0) 2614 2615 #define R_AX_MAC_LOOPBACK 0xCC20 2616 #define R_AX_MAC_LOOPBACK_C1 0xEC20 2617 #define B_AX_MACLBK_EN BIT(0) 2618 2619 #define R_AX_WMAC_NAV_CTL 0xCC80 2620 #define R_AX_WMAC_NAV_CTL_C1 0xEC80 2621 #define B_AX_WMAC_NAV_UPPER_EN BIT(26) 2622 #define B_AX_WMAC_0P125US_TIMER_MASK GENMASK(25, 18) 2623 #define B_AX_WMAC_PLCP_UP_NAV_EN BIT(17) 2624 #define B_AX_WMAC_TF_UP_NAV_EN BIT(16) 2625 #define B_AX_WMAC_NAV_UPPER_MASK GENMASK(15, 8) 2626 #define NAV_12MS 0xBC 2627 #define NAV_25MS 0xC4 2628 #define B_AX_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0) 2629 2630 #define R_AX_RXTRIG_TEST_USER_2 0xCCB0 2631 #define R_AX_RXTRIG_TEST_USER_2_C1 0xECB0 2632 #define B_AX_RXTRIG_MACID_MASK GENMASK(31, 24) 2633 #define B_AX_RXTRIG_RU26_DIS BIT(21) 2634 #define B_AX_RXTRIG_FCSCHK_EN BIT(20) 2635 #define B_AX_RXTRIG_PORT_SEL_MASK GENMASK(19, 17) 2636 #define B_AX_RXTRIG_EN BIT(16) 2637 #define B_AX_RXTRIG_USERINFO_2_MASK GENMASK(15, 0) 2638 2639 #define R_AX_TRXPTCL_ERROR_INDICA_MASK 0xCCBC 2640 #define R_AX_TRXPTCL_ERROR_INDICA_MASK_C1 0xECBC 2641 #define B_AX_WMAC_MODE BIT(22) 2642 #define B_AX_WMAC_TIMETOUT_THR_MASK GENMASK(21, 16) 2643 #define B_AX_RMAC_FTM BIT(8) 2644 #define B_AX_RMAC_CSI BIT(7) 2645 #define B_AX_TMAC_MIMO_CTRL BIT(6) 2646 #define B_AX_TMAC_RXTB BIT(5) 2647 #define B_AX_TMAC_HWSIGB_GEN BIT(4) 2648 #define B_AX_TMAC_TXPLCP BIT(3) 2649 #define B_AX_TMAC_RESP BIT(2) 2650 #define B_AX_TMAC_TXCTL BIT(1) 2651 #define B_AX_TMAC_MACTX BIT(0) 2652 #define B_AX_TMAC_IMR_CLR_V1 (B_AX_TMAC_MACTX | \ 2653 B_AX_TMAC_TXCTL | \ 2654 B_AX_TMAC_RESP | \ 2655 B_AX_TMAC_TXPLCP | \ 2656 B_AX_TMAC_HWSIGB_GEN | \ 2657 B_AX_TMAC_RXTB | \ 2658 B_AX_TMAC_MIMO_CTRL | \ 2659 B_AX_RMAC_CSI | \ 2660 B_AX_RMAC_FTM) 2661 #define B_AX_TMAC_IMR_SET_V1 (B_AX_TMAC_MACTX | \ 2662 B_AX_TMAC_TXCTL | \ 2663 B_AX_TMAC_RESP | \ 2664 B_AX_TMAC_TXPLCP | \ 2665 B_AX_TMAC_HWSIGB_GEN | \ 2666 B_AX_TMAC_RXTB | \ 2667 B_AX_TMAC_MIMO_CTRL | \ 2668 B_AX_RMAC_FTM) 2669 2670 #define R_AX_WMAC_TX_TF_INFO_0 0xCCD0 2671 #define R_AX_WMAC_TX_TF_INFO_0_C1 0xECD0 2672 #define B_AX_WMAC_TX_TF_INFO_SEL_MASK GENMASK(2, 0) 2673 2674 #define R_AX_WMAC_TX_TF_INFO_1 0xCCD4 2675 #define R_AX_WMAC_TX_TF_INFO_1_C1 0xECD4 2676 #define B_AX_WMAC_TX_TF_INFO_P0_MASK GENMASK(31, 0) 2677 2678 #define R_AX_WMAC_TX_TF_INFO_2 0xCCD8 2679 #define R_AX_WMAC_TX_TF_INFO_2_C1 0xECD8 2680 #define B_AX_WMAC_TX_TF_INFO_P1_MASK GENMASK(31, 0) 2681 2682 #define R_AX_TMAC_ERR_IMR_ISR 0xCCEC 2683 #define R_AX_TMAC_ERR_IMR_ISR_C1 0xECEC 2684 #define B_AX_TMAC_TXPLCP_ERR_CLR BIT(19) 2685 #define B_AX_TMAC_RESP_ERR_CLR BIT(18) 2686 #define B_AX_TMAC_TXCTL_ERR_CLR BIT(17) 2687 #define B_AX_TMAC_MACTX_ERR_CLR BIT(16) 2688 #define B_AX_TMAC_TXPLCP_ERR BIT(14) 2689 #define B_AX_TMAC_RESP_ERR BIT(13) 2690 #define B_AX_TMAC_TXCTL_ERR BIT(12) 2691 #define B_AX_TMAC_MACTX_ERR BIT(11) 2692 #define B_AX_TMAC_TXPLCP_INT_EN BIT(10) 2693 #define B_AX_TMAC_RESP_INT_EN BIT(9) 2694 #define B_AX_TMAC_TXCTL_INT_EN BIT(8) 2695 #define B_AX_TMAC_MACTX_INT_EN BIT(7) 2696 #define B_AX_WMAC_INT_MODE BIT(6) 2697 #define B_AX_TMAC_TIMETOUT_THR_MASK GENMASK(5, 0) 2698 #define B_AX_TMAC_IMR_CLR (B_AX_TMAC_MACTX_INT_EN | \ 2699 B_AX_TMAC_TXCTL_INT_EN | \ 2700 B_AX_TMAC_RESP_INT_EN | \ 2701 B_AX_TMAC_TXPLCP_INT_EN) 2702 #define B_AX_TMAC_IMR_SET (B_AX_TMAC_MACTX_INT_EN | \ 2703 B_AX_TMAC_TXCTL_INT_EN | \ 2704 B_AX_TMAC_RESP_INT_EN | \ 2705 B_AX_TMAC_TXPLCP_INT_EN) 2706 2707 #define R_AX_DBGSEL_TRXPTCL 0xCCF4 2708 #define R_AX_DBGSEL_TRXPTCL_C1 0xECF4 2709 #define B_AX_DBGSEL_TRXPTCL_MASK GENMASK(7, 0) 2710 2711 #define R_AX_PHYINFO_ERR_IMR_V1 0xCCF8 2712 #define R_AX_PHYINFO_ERR_IMR_V1_C1 0xECF8 2713 #define B_AX_PHYINTF_TIMEOUT_THR_MSAK_V1 GENMASK(21, 16) 2714 #define B_AX_CSI_ON_TIMEOUT_EN BIT(5) 2715 #define B_AX_STS_ON_TIMEOUT_EN BIT(4) 2716 #define B_AX_DATA_ON_TIMEOUT_EN BIT(3) 2717 #define B_AX_OFDM_CCA_TIMEOUT_EN BIT(2) 2718 #define B_AX_CCK_CCA_TIMEOUT_EN BIT(1) 2719 #define B_AX_PHY_TXON_TIMEOUT_EN BIT(0) 2720 #define B_AX_PHYINFO_IMR_CLR_V1 (B_AX_PHY_TXON_TIMEOUT_EN | \ 2721 B_AX_CCK_CCA_TIMEOUT_EN | \ 2722 B_AX_OFDM_CCA_TIMEOUT_EN | \ 2723 B_AX_DATA_ON_TIMEOUT_EN | \ 2724 B_AX_STS_ON_TIMEOUT_EN | \ 2725 B_AX_CSI_ON_TIMEOUT_EN) 2726 #define B_AX_PHYINFO_IMR_SET_V1 (B_AX_PHY_TXON_TIMEOUT_EN | \ 2727 B_AX_CCK_CCA_TIMEOUT_EN | \ 2728 B_AX_OFDM_CCA_TIMEOUT_EN | \ 2729 B_AX_DATA_ON_TIMEOUT_EN | \ 2730 B_AX_STS_ON_TIMEOUT_EN | \ 2731 B_AX_CSI_ON_TIMEOUT_EN) 2732 2733 #define R_AX_PHYINFO_ERR_IMR 0xCCFC 2734 #define R_AX_PHYINFO_ERR_IMR_C1 0xECFC 2735 #define B_AX_CSI_ON_TIMEOUT BIT(29) 2736 #define B_AX_STS_ON_TIMEOUT BIT(28) 2737 #define B_AX_DATA_ON_TIMEOUT BIT(27) 2738 #define B_AX_OFDM_CCA_TIMEOUT BIT(26) 2739 #define B_AX_CCK_CCA_TIMEOUT BIT(25) 2740 #define B_AXC_PHY_TXON_TIMEOUT BIT(24) 2741 #define B_AX_CSI_ON_TIMEOUT_INT_EN BIT(21) 2742 #define B_AX_STS_ON_TIMEOUT_INT_EN BIT(20) 2743 #define B_AX_DATA_ON_TIMEOUT_INT_EN BIT(19) 2744 #define B_AX_OFDM_CCA_TIMEOUT_INT_EN BIT(18) 2745 #define B_AX_CCK_CCA_TIMEOUT_INT_EN BIT(17) 2746 #define B_AX_PHY_TXON_TIMEOUT_INT_EN BIT(16) 2747 #define B_AX_PHYINTF_TIMEOUT_THR_MSAK GENMASK(5, 0) 2748 #define B_AX_PHYINFO_IMR_EN_ALL (B_AX_PHY_TXON_TIMEOUT_INT_EN | \ 2749 B_AX_CCK_CCA_TIMEOUT_INT_EN | \ 2750 B_AX_OFDM_CCA_TIMEOUT_INT_EN | \ 2751 B_AX_DATA_ON_TIMEOUT_INT_EN | \ 2752 B_AX_STS_ON_TIMEOUT_INT_EN | \ 2753 B_AX_CSI_ON_TIMEOUT_INT_EN) 2754 2755 #define R_AX_PHYINFO_ERR_ISR 0xCCFC 2756 #define R_AX_PHYINFO_ERR_ISR_C1 0xECFC 2757 2758 #define R_AX_BFMER_CTRL_0 0xCD78 2759 #define R_AX_BFMER_CTRL_0_C1 0xED78 2760 #define B_AX_BFMER_HE_CSI_OFFSET_MASK GENMASK(31, 24) 2761 #define B_AX_BFMER_VHT_CSI_OFFSET_MASK GENMASK(23, 16) 2762 #define B_AX_BFMER_HT_CSI_OFFSET_MASK GENMASK(15, 8) 2763 #define B_AX_BFMER_NDP_BFEN BIT(2) 2764 #define B_AX_BFMER_VHT_BFPRT_CHK BIT(0) 2765 2766 #define R_AX_BFMEE_RESP_OPTION 0xCD80 2767 #define R_AX_BFMEE_RESP_OPTION_C1 0xED80 2768 #define B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK GENMASK(31, 24) 2769 #define B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK GENMASK(23, 20) 2770 #define B_AX_MU_BFRPTSEG_SEL_MASK GENMASK(18, 17) 2771 #define B_AX_BFMEE_NDP_RXSTDBY_SEL BIT(16) 2772 #define BFRP_RX_STANDBY_TIMER 0x0 2773 #define NDP_RX_STANDBY_TIMER 0xFF 2774 #define B_AX_BFMEE_HE_NDPA_EN BIT(2) 2775 #define B_AX_BFMEE_VHT_NDPA_EN BIT(1) 2776 #define B_AX_BFMEE_HT_NDPA_EN BIT(0) 2777 2778 #define R_AX_TRXPTCL_RESP_CSI_CTRL_0 0xCD88 2779 #define R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1 0xED88 2780 #define R_AX_TRXPTCL_RESP_CSI_CTRL_1 0xCD94 2781 #define R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1 0xED94 2782 #define B_AX_BFMEE_CSISEQ_SEL BIT(29) 2783 #define B_AX_BFMEE_BFPARAM_SEL BIT(28) 2784 #define B_AX_BFMEE_OFDM_LEN_TH_MASK GENMASK(27, 24) 2785 #define B_AX_BFMEE_BF_PORT_SEL BIT(23) 2786 #define B_AX_BFMEE_USE_NSTS BIT(22) 2787 #define B_AX_BFMEE_CSI_RATE_FB_EN BIT(21) 2788 #define B_AX_BFMEE_CSI_GID_SEL BIT(20) 2789 #define B_AX_BFMEE_CSI_RSC_MASK GENMASK(19, 18) 2790 #define B_AX_BFMEE_CSI_FORCE_RETE_EN BIT(17) 2791 #define B_AX_BFMEE_CSI_USE_NDPARATE BIT(16) 2792 #define B_AX_BFMEE_CSI_WITHHTC_EN BIT(15) 2793 #define B_AX_BFMEE_CSIINFO0_BF_EN BIT(14) 2794 #define B_AX_BFMEE_CSIINFO0_STBC_EN BIT(13) 2795 #define B_AX_BFMEE_CSIINFO0_LDPC_EN BIT(12) 2796 #define B_AX_BFMEE_CSIINFO0_CS_MASK GENMASK(11, 10) 2797 #define B_AX_BFMEE_CSIINFO0_CB_MASK GENMASK(9, 8) 2798 #define B_AX_BFMEE_CSIINFO0_NG_MASK GENMASK(7, 6) 2799 #define B_AX_BFMEE_CSIINFO0_NR_MASK GENMASK(5, 3) 2800 #define B_AX_BFMEE_CSIINFO0_NC_MASK GENMASK(2, 0) 2801 2802 #define R_AX_TRXPTCL_RESP_CSI_RRSC 0xCD8C 2803 #define R_AX_TRXPTCL_RESP_CSI_RRSC_C1 0xED8C 2804 #define CSI_RRSC_BMAP 0x29292911 2805 2806 #define R_AX_TRXPTCL_RESP_CSI_RATE 0xCD90 2807 #define R_AX_TRXPTCL_RESP_CSI_RATE_C1 0xED90 2808 #define B_AX_BFMEE_HE_CSI_RATE_MASK GENMASK(22, 16) 2809 #define B_AX_BFMEE_VHT_CSI_RATE_MASK GENMASK(14, 8) 2810 #define B_AX_BFMEE_HT_CSI_RATE_MASK GENMASK(6, 0) 2811 #define CSI_INIT_RATE_HE 0x3 2812 #define CSI_INIT_RATE_VHT 0x3 2813 #define CSI_INIT_RATE_HT 0x3 2814 2815 #define R_AX_RCR 0xCE00 2816 #define R_AX_RCR_C1 0xEE00 2817 #define B_AX_STOP_RX_IN BIT(11) 2818 #define B_AX_DRV_INFO_SIZE_MASK GENMASK(10, 8) 2819 #define B_AX_CH_EN_MASK GENMASK(3, 0) 2820 2821 #define R_AX_DLK_PROTECT_CTL 0xCE02 2822 #define R_AX_DLK_PROTECT_CTL_C1 0xEE02 2823 #define B_AX_RX_DLK_CCA_TIME_MASK GENMASK(15, 8) 2824 #define B_AX_RX_DLK_DATA_TIME_MASK GENMASK(7, 4) 2825 2826 #define R_AX_PLCP_HDR_FLTR 0xCE04 2827 #define R_AX_PLCP_HDR_FLTR_C1 0xEE04 2828 #define B_AX_DIS_CHK_MIN_LEN BIT(8) 2829 #define B_AX_HE_SIGB_CRC_CHK BIT(6) 2830 #define B_AX_VHT_MU_SIGB_CRC_CHK BIT(5) 2831 #define B_AX_VHT_SU_SIGB_CRC_CHK BIT(4) 2832 #define B_AX_SIGA_CRC_CHK BIT(3) 2833 #define B_AX_LSIG_PARITY_CHK_EN BIT(2) 2834 #define B_AX_CCK_SIG_CHK BIT(1) 2835 #define B_AX_CCK_CRC_CHK BIT(0) 2836 2837 #define R_AX_RX_FLTR_OPT 0xCE20 2838 #define R_AX_RX_FLTR_OPT_C1 0xEE20 2839 #define B_AX_UID_FILTER_MASK GENMASK(31, 24) 2840 #define B_AX_UNSPT_FILTER_SH 22 2841 #define B_AX_UNSPT_FILTER_MASK GENMASK(23, 22) 2842 #define B_AX_RX_MPDU_MAX_LEN_MASK GENMASK(21, 16) 2843 #define B_AX_RX_MPDU_MAX_LEN_SIZE 0x3f 2844 #define B_AX_A_FTM_REQ BIT(14) 2845 #define B_AX_A_ERR_PKT BIT(13) 2846 #define B_AX_A_UNSUP_PKT BIT(12) 2847 #define B_AX_A_CRC32_ERR BIT(11) 2848 #define B_AX_A_PWR_MGNT BIT(10) 2849 #define B_AX_A_BCN_CHK_RULE_MASK GENMASK(9, 8) 2850 #define B_AX_A_BCN_CHK_EN BIT(7) 2851 #define B_AX_A_MC_LIST_CAM_MATCH BIT(6) 2852 #define B_AX_A_BC_CAM_MATCH BIT(5) 2853 #define B_AX_A_UC_CAM_MATCH BIT(4) 2854 #define B_AX_A_MC BIT(3) 2855 #define B_AX_A_BC BIT(2) 2856 #define B_AX_A_A1_MATCH BIT(1) 2857 #define B_AX_SNIFFER_MODE BIT(0) 2858 #define DEFAULT_AX_RX_FLTR (B_AX_A_A1_MATCH | B_AX_A_BC | B_AX_A_MC | \ 2859 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH | \ 2860 B_AX_A_PWR_MGNT | B_AX_A_FTM_REQ | \ 2861 u32_encode_bits(3, B_AX_UID_FILTER_MASK) | \ 2862 B_AX_A_BCN_CHK_EN) 2863 #define B_AX_RX_FLTR_CFG_MASK ((u32)~B_AX_RX_MPDU_MAX_LEN_MASK) 2864 2865 #define R_AX_CTRL_FLTR 0xCE24 2866 #define R_AX_CTRL_FLTR_C1 0xEE24 2867 #define R_AX_MGNT_FLTR 0xCE28 2868 #define R_AX_MGNT_FLTR_C1 0xEE28 2869 #define R_AX_DATA_FLTR 0xCE2C 2870 #define R_AX_DATA_FLTR_C1 0xEE2C 2871 #define RX_FLTR_FRAME_DROP 0x00000000 2872 #define RX_FLTR_FRAME_TO_HOST 0x55555555 2873 #define RX_FLTR_FRAME_TO_WLCPU 0xAAAAAAAA 2874 2875 #define R_AX_ADDR_CAM_CTRL 0xCE34 2876 #define R_AX_ADDR_CAM_CTRL_C1 0xEE34 2877 #define B_AX_ADDR_CAM_RANGE_MASK GENMASK(23, 16) 2878 #define B_AX_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12) 2879 #define B_AX_ADDR_CAM_CLR BIT(8) 2880 #define B_AX_ADDR_CAM_A2_B0_CHK BIT(2) 2881 #define B_AX_ADDR_CAM_SRCH_PERPKT BIT(1) 2882 #define B_AX_ADDR_CAM_EN BIT(0) 2883 2884 #define R_AX_RESPBA_CAM_CTRL 0xCE3C 2885 #define R_AX_RESPBA_CAM_CTRL_C1 0xEE3C 2886 #define B_AX_SSN_SEL BIT(2) 2887 #define B_AX_BACAM_RST_MASK GENMASK(1, 0) 2888 #define S_AX_BACAM_RST_ALL 2 2889 2890 #define R_AX_PPDU_STAT 0xCE40 2891 #define R_AX_PPDU_STAT_C1 0xEE40 2892 #define B_AX_PPDU_STAT_RPT_TRIG BIT(8) 2893 #define B_AX_PPDU_STAT_RPT_CRC32 BIT(5) 2894 #define B_AX_PPDU_STAT_RPT_A1M BIT(4) 2895 #define B_AX_APP_PLCP_HDR_RPT BIT(3) 2896 #define B_AX_APP_RX_CNT_RPT BIT(2) 2897 #define B_AX_APP_MAC_INFO_RPT BIT(1) 2898 #define B_AX_PPDU_STAT_RPT_EN BIT(0) 2899 2900 #define R_AX_RX_SR_CTRL 0xCE4A 2901 #define R_AX_RX_SR_CTRL_C1 0xEE4A 2902 #define B_AX_SR_EN BIT(0) 2903 2904 #define R_AX_CSIRPT_OPTION 0xCE64 2905 #define R_AX_CSIRPT_OPTION_C1 0xEE64 2906 #define B_AX_CSIPRT_HESU_AID_EN BIT(25) 2907 #define B_AX_CSIPRT_VHTSU_AID_EN BIT(24) 2908 2909 #define R_AX_RX_STATE_MONITOR 0xCEF0 2910 #define R_AX_RX_STATE_MONITOR_C1 0xEEF0 2911 #define B_AX_RX_STATE_MONITOR_MASK GENMASK(31, 0) 2912 #define B_AX_STATE_CUR_MASK GENMASK(31, 16) 2913 #define B_AX_STATE_NXT_MASK GENMASK(13, 8) 2914 #define B_AX_STATE_UPD BIT(7) 2915 #define B_AX_STATE_SEL_MASK GENMASK(4, 0) 2916 2917 #define R_AX_RMAC_ERR_ISR 0xCEF4 2918 #define R_AX_RMAC_ERR_ISR_C1 0xEEF4 2919 #define B_AX_RXERR_INTPS_EN BIT(31) 2920 #define B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN BIT(19) 2921 #define B_AX_RMAC_RX_TIMEOUT_INT_EN BIT(18) 2922 #define B_AX_RMAC_CSI_TIMEOUT_INT_EN BIT(17) 2923 #define B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN BIT(16) 2924 #define B_AX_RMAC_CCA_TIMEOUT_INT_EN BIT(15) 2925 #define B_AX_RMAC_DMA_TIMEOUT_INT_EN BIT(14) 2926 #define B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN BIT(13) 2927 #define B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN BIT(12) 2928 #define B_AX_RMAC_RX_CSI_TIMEOUT_FLAG BIT(7) 2929 #define B_AX_RMAC_RX_TIMEOUT_FLAG BIT(6) 2930 #define B_AX_BMAC_CSI_TIMEOUT_FLAG BIT(5) 2931 #define B_AX_BMAC_DATA_ON_TIMEOUT_FLAG BIT(4) 2932 #define B_AX_BMAC_CCA_TIMEOUT_FLAG BIT(3) 2933 #define B_AX_BMAC_DMA_TIMEOUT_FLAG BIT(2) 2934 #define B_AX_BMAC_DATA_ON_TO_IDLE_TIMEOUT_FLAG BIT(1) 2935 #define B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG BIT(0) 2936 #define B_AX_RMAC_IMR_CLR (B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN | \ 2937 B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN | \ 2938 B_AX_RMAC_DMA_TIMEOUT_INT_EN | \ 2939 B_AX_RMAC_CCA_TIMEOUT_INT_EN | \ 2940 B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN | \ 2941 B_AX_RMAC_CSI_TIMEOUT_INT_EN | \ 2942 B_AX_RMAC_RX_TIMEOUT_INT_EN | \ 2943 B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN) 2944 #define B_AX_RMAC_IMR_SET (B_AX_RMAC_DMA_TIMEOUT_INT_EN | \ 2945 B_AX_RMAC_CSI_TIMEOUT_INT_EN | \ 2946 B_AX_RMAC_RX_TIMEOUT_INT_EN | \ 2947 B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN) 2948 2949 #define R_AX_RX_ERR_IMR 0xCEF8 2950 #define R_AX_RX_ERR_IMR_C1 0xEEF8 2951 #define B_AX_RX_ERR_TRIG_ACT_TO_MSK BIT(9) 2952 #define B_AX_RX_ERR_STS_ACT_TO_MSK BIT(8) 2953 #define B_AX_RX_ERR_CSI_ACT_TO_MSK BIT(7) 2954 #define B_AX_RX_ERR_ACT_TO_MSK BIT(6) 2955 #define B_AX_CSI_DATAON_ASSERT_TO_MSK BIT(5) 2956 #define B_AX_DATAON_ASSERT_TO_MSK BIT(4) 2957 #define B_AX_CCA_ASSERT_TO_MSK BIT(3) 2958 #define B_AX_RX_ERR_DMA_TO_MSK BIT(2) 2959 #define B_AX_RX_ERR_DATA_TO_MSK BIT(1) 2960 #define B_AX_RX_ERR_CCA_TO_MSK BIT(0) 2961 #define B_AX_RMAC_IMR_CLR_V1 (B_AX_RX_ERR_CCA_TO_MSK | \ 2962 B_AX_RX_ERR_DATA_TO_MSK | \ 2963 B_AX_RX_ERR_DMA_TO_MSK | \ 2964 B_AX_CCA_ASSERT_TO_MSK | \ 2965 B_AX_DATAON_ASSERT_TO_MSK | \ 2966 B_AX_CSI_DATAON_ASSERT_TO_MSK | \ 2967 B_AX_RX_ERR_ACT_TO_MSK | \ 2968 B_AX_RX_ERR_CSI_ACT_TO_MSK | \ 2969 B_AX_RX_ERR_STS_ACT_TO_MSK | \ 2970 B_AX_RX_ERR_TRIG_ACT_TO_MSK) 2971 #define B_AX_RMAC_IMR_SET_V1 (B_AX_RX_ERR_CCA_TO_MSK | \ 2972 B_AX_RX_ERR_DATA_TO_MSK | \ 2973 B_AX_RX_ERR_DMA_TO_MSK | \ 2974 B_AX_CCA_ASSERT_TO_MSK | \ 2975 B_AX_DATAON_ASSERT_TO_MSK | \ 2976 B_AX_CSI_DATAON_ASSERT_TO_MSK | \ 2977 B_AX_RX_ERR_ACT_TO_MSK | \ 2978 B_AX_RX_ERR_CSI_ACT_TO_MSK | \ 2979 B_AX_RX_ERR_STS_ACT_TO_MSK | \ 2980 B_AX_RX_ERR_TRIG_ACT_TO_MSK) 2981 2982 #define R_AX_RMAC_PLCP_MON 0xCEF8 2983 #define R_AX_RMAC_PLCP_MON_C1 0xEEF8 2984 #define B_AX_RMAC_PLCP_MON_MASK GENMASK(31, 0) 2985 #define B_AX_PCLP_MON_SEL_MASK GENMASK(31, 28) 2986 #define B_AX_PCLP_MON_CONT_MASK GENMASK(27, 0) 2987 2988 #define R_AX_RX_DEBUG_SELECT 0xCEFC 2989 #define R_AX_RX_DEBUG_SELECT_C1 0xEEFC 2990 #define B_AX_DEBUG_SEL_MASK GENMASK(7, 0) 2991 2992 #define R_AX_PWR_RATE_CTRL 0xD200 2993 #define R_AX_PWR_RATE_CTRL_C1 0xF200 2994 #define B_AX_FORCE_PWR_BY_RATE_EN BIT(9) 2995 #define B_AX_FORCE_PWR_BY_RATE_VALUE_MASK GENMASK(8, 0) 2996 2997 #define R_AX_PWR_RATE_OFST_CTRL 0xD204 2998 #define R_AX_PWR_COEXT_CTRL 0xD220 2999 #define B_AX_TXAGC_BT_EN BIT(1) 3000 #define B_AX_TXAGC_BT_MASK GENMASK(11, 3) 3001 3002 #define R_AX_PWR_UL_CTRL0 0xD240 3003 #define R_AX_PWR_UL_CTRL2 0xD248 3004 #define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0) 3005 #define B_AX_PWR_UL_CTRL2_MASK 0x07700007 3006 #define R_AX_PWR_UL_TB_CTRL 0xD288 3007 #define B_AX_PWR_UL_TB_CTRL_EN BIT(31) 3008 #define R_AX_PWR_UL_TB_1T 0xD28C 3009 #define B_AX_PWR_UL_TB_1T_MASK GENMASK(4, 0) 3010 #define B_AX_PWR_UL_TB_1T_V1_MASK GENMASK(7, 0) 3011 #define R_AX_PWR_UL_TB_2T 0xD290 3012 #define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0) 3013 #define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0) 3014 #define R_AX_PWR_BY_RATE_TABLE0 0xD2C0 3015 #define R_AX_PWR_BY_RATE_TABLE10 0xD2E8 3016 #define R_AX_PWR_BY_RATE R_AX_PWR_BY_RATE_TABLE0 3017 #define R_AX_PWR_BY_RATE_MAX R_AX_PWR_BY_RATE_TABLE10 3018 #define R_AX_PWR_LMT_TABLE0 0xD2EC 3019 #define R_AX_PWR_LMT_TABLE19 0xD338 3020 #define R_AX_PWR_LMT R_AX_PWR_LMT_TABLE0 3021 #define R_AX_PWR_LMT_MAX R_AX_PWR_LMT_TABLE19 3022 #define R_AX_PWR_RU_LMT_TABLE0 0xD33C 3023 #define R_AX_PWR_RU_LMT_TABLE11 0xD368 3024 #define R_AX_PWR_RU_LMT R_AX_PWR_RU_LMT_TABLE0 3025 #define R_AX_PWR_RU_LMT_MAX R_AX_PWR_RU_LMT_TABLE11 3026 #define R_AX_PWR_MACID_LMT_TABLE0 0xD36C 3027 #define R_AX_PWR_MACID_LMT_TABLE127 0xD568 3028 3029 #define R_AX_PATH_COM0 0xD800 3030 #define AX_PATH_COM0_DFVAL 0x00000000 3031 #define AX_PATH_COM0_PATHA 0x08889880 3032 #define AX_PATH_COM0_PATHB 0x11111900 3033 #define AX_PATH_COM0_PATHAB 0x19999980 3034 #define R_AX_PATH_COM1 0xD804 3035 #define AX_PATH_COM1_DFVAL 0x00000000 3036 #define AX_PATH_COM1_PATHA 0x13111111 3037 #define AX_PATH_COM1_PATHB 0x23222222 3038 #define AX_PATH_COM1_PATHAB 0x33333333 3039 #define R_AX_PATH_COM2 0xD808 3040 #define AX_PATH_COM2_DFVAL 0x00000000 3041 #define AX_PATH_COM2_PATHA 0x01209313 3042 #define AX_PATH_COM2_PATHB 0x01209323 3043 #define AX_PATH_COM2_PATHAB 0x01209333 3044 #define R_AX_PATH_COM3 0xD80C 3045 #define AX_PATH_COM3_DFVAL 0x49249249 3046 #define R_AX_PATH_COM4 0xD810 3047 #define AX_PATH_COM4_DFVAL 0x1C9C9C49 3048 #define R_AX_PATH_COM5 0xD814 3049 #define AX_PATH_COM5_DFVAL 0x39393939 3050 #define R_AX_PATH_COM6 0xD818 3051 #define AX_PATH_COM6_DFVAL 0x39393939 3052 #define R_AX_PATH_COM7 0xD81C 3053 #define AX_PATH_COM7_DFVAL 0x39393939 3054 #define AX_PATH_COM7_PATHA 0x39393939 3055 #define AX_PATH_COM7_PATHB 0x39383939 3056 #define AX_PATH_COM7_PATHAB 0x39393939 3057 #define R_AX_PATH_COM8 0xD820 3058 #define AX_PATH_COM8_DFVAL 0x00000000 3059 #define AX_PATH_COM8_PATHA 0x00003939 3060 #define AX_PATH_COM8_PATHB 0x00003938 3061 #define AX_PATH_COM8_PATHAB 0x00003939 3062 #define R_AX_PATH_COM9 0xD824 3063 #define AX_PATH_COM9_DFVAL 0x000007C0 3064 #define R_AX_PATH_COM10 0xD828 3065 #define AX_PATH_COM10_DFVAL 0xE0000000 3066 #define R_AX_PATH_COM11 0xD82C 3067 #define AX_PATH_COM11_DFVAL 0x00000000 3068 #define R_P80_AT_HIGH_FREQ_BB_WRP 0xD848 3069 #define B_P80_AT_HIGH_FREQ_BB_WRP BIT(28) 3070 #define R_AX_TSSI_CTRL_HEAD 0xD908 3071 #define R_AX_BANDEDGE_CFG 0xD94C 3072 #define B_AX_BANDEDGE_CFG_IDX_MASK GENMASK(31, 30) 3073 #define R_AX_TSSI_CTRL_TAIL 0xD95C 3074 3075 #define R_AX_TXPWR_IMR 0xD9E0 3076 #define R_AX_TXPWR_IMR_C1 0xF9E0 3077 #define R_AX_TXPWR_ISR 0xD9E4 3078 #define R_AX_TXPWR_ISR_C1 0xF9E4 3079 3080 #define R_AX_BTC_CFG 0xDA00 3081 #define B_AX_BTC_EN BIT(31) 3082 #define B_AX_EN_EXT_BT_PINMUX BIT(29) 3083 #define B_AX_BTC_RST BIT(28) 3084 #define B_AX_BTC_DBG_SRC_SEL BIT(27) 3085 #define B_AX_BTC_MODE_MASK GENMASK(25, 24) 3086 #define B_AX_INV_WL_ACT2 BIT(17) 3087 #define B_AX_BTG_LNA1_GAIN_SEL BIT(16) 3088 #define B_AX_COEX_DLY_CLK_MASK GENMASK(15, 8) 3089 #define B_AX_IGN_GNT_BT2_RX BIT(7) 3090 #define B_AX_IGN_GNT_BT2_TX BIT(6) 3091 #define B_AX_IGN_GNT_BT2 BIT(5) 3092 #define B_AX_BTC_DBG_SEL_MASK GENMASK(4, 3) 3093 #define B_AX_DIS_BTC_CLK_G BIT(2) 3094 #define B_AX_GNT_WL_RX_CTRL BIT(1) 3095 #define B_AX_WL_SRC BIT(0) 3096 3097 #define R_AX_RTK_MODE_CFG_V1 0xDA04 3098 #define R_AX_RTK_MODE_CFG_V1_C1 0xFA04 3099 #define B_AX_BT_BLE_EN_V1 BIT(24) 3100 #define B_AX_BT_ULTRA_EN BIT(16) 3101 #define B_AX_BT_L_RX_ULTRA_MASK GENMASK(15, 14) 3102 #define B_AX_BT_L_TX_ULTRA_MASK GENMASK(13, 12) 3103 #define B_AX_BT_H_RX_ULTRA_MASK GENMASK(11, 10) 3104 #define B_AX_BT_H_TX_ULTRA_MASK GENMASK(9, 8) 3105 #define B_AX_SAMPLE_CLK_MASK GENMASK(7, 0) 3106 3107 #define R_AX_WL_PRI_MSK 0xDA10 3108 #define B_AX_PTA_WL_PRI_MASK_BCNQ BIT(8) 3109 3110 #define R_AX_BT_CNT_CFG 0xDA10 3111 #define R_AX_BT_CNT_CFG_C1 0xFA10 3112 #define B_AX_BT_CNT_RST_V1 BIT(1) 3113 #define B_AX_BT_CNT_EN BIT(0) 3114 3115 #define R_BTC_BT_CNT_HIGH 0xDA14 3116 #define R_BTC_BT_CNT_LOW 0xDA18 3117 3118 #define R_AX_BTC_FUNC_EN 0xDA20 3119 #define R_AX_BTC_FUNC_EN_C1 0xFA20 3120 #define B_AX_PTA_WL_TX_EN BIT(1) 3121 #define B_AX_PTA_EDCCA_EN BIT(0) 3122 3123 #define R_BTC_COEX_WL_REQ 0xDA24 3124 #define B_BTC_TX_BCN_HI BIT(22) 3125 #define B_BTC_RSP_ACK_HI BIT(10) 3126 3127 #define R_BTC_BREAK_TABLE 0xDA2C 3128 #define BTC_BREAK_PARAM 0xf0ffffff 3129 3130 #define R_BTC_BT_COEX_MSK_TABLE 0xDA30 3131 #define B_BTC_PRI_MASK_TX_RESP_V1 BIT(3) 3132 3133 #define R_AX_BT_COEX_CFG_2 0xDA34 3134 #define R_AX_BT_COEX_CFG_2_C1 0xFA34 3135 #define B_AX_GNT_BT_BYPASS_PRIORITY BIT(12) 3136 #define B_AX_GNT_BT_POLARITY BIT(8) 3137 #define B_AX_TIMER_MASK GENMASK(7, 0) 3138 #define MAC_AX_CSR_RATE 80 3139 3140 #define R_AX_CSR_MODE 0xDA40 3141 #define R_AX_CSR_MODE_C1 0xFA40 3142 #define B_AX_BT_CNT_RST BIT(16) 3143 #define B_AX_BT_STAT_DELAY_MASK GENMASK(15, 12) 3144 #define MAC_AX_CSR_DELAY 0 3145 #define B_AX_BT_TRX_INIT_DETECT_MASK GENMASK(11, 8) 3146 #define MAC_AX_CSR_TRX_TO 4 3147 #define B_AX_BT_PRI_DETECT_TO_MASK GENMASK(7, 4) 3148 #define MAC_AX_CSR_PRI_TO 5 3149 #define B_AX_WL_ACT_MSK BIT(3) 3150 #define B_AX_STATIS_BT_EN BIT(2) 3151 #define B_AX_WL_ACT_MASK_ENABLE BIT(1) 3152 #define B_AX_ENHANCED_BT BIT(0) 3153 3154 #define R_AX_BT_BREAK_TABLE 0xDA44 3155 3156 #define R_AX_BT_STAST_HIGH 0xDA44 3157 #define B_AX_STATIS_BT_HI_RX_MASK GENMASK(31, 16) 3158 #define B_AX_STATIS_BT_HI_TX_MASK GENMASK(15, 0) 3159 #define R_AX_BT_STAST_LOW 0xDA48 3160 #define B_AX_STATIS_BT_LO_TX_1_MASK GENMASK(15, 0) 3161 #define B_AX_STATIS_BT_LO_RX_1_MASK GENMASK(31, 16) 3162 3163 #define R_AX_GNT_SW_CTRL 0xDA48 3164 #define R_AX_GNT_SW_CTRL_C1 0xFA48 3165 #define B_AX_WL_ACT2_VAL BIT(21) 3166 #define B_AX_WL_ACT2_SWCTRL BIT(20) 3167 #define B_AX_WL_ACT_VAL BIT(19) 3168 #define B_AX_WL_ACT_SWCTRL BIT(18) 3169 #define B_AX_GNT_BT_RX_VAL BIT(17) 3170 #define B_AX_GNT_BT_RX_SWCTRL BIT(16) 3171 #define B_AX_GNT_BT_TX_VAL BIT(15) 3172 #define B_AX_GNT_BT_TX_SWCTRL BIT(14) 3173 #define B_AX_GNT_WL_RX_VAL BIT(13) 3174 #define B_AX_GNT_WL_RX_SWCTRL BIT(12) 3175 #define B_AX_GNT_WL_TX_VAL BIT(11) 3176 #define B_AX_GNT_WL_TX_SWCTRL BIT(10) 3177 #define B_AX_GNT_BT_RFC_S1_VAL BIT(9) 3178 #define B_AX_GNT_BT_RFC_S1_SWCTRL BIT(8) 3179 #define B_AX_GNT_WL_RFC_S1_VAL BIT(7) 3180 #define B_AX_GNT_WL_RFC_S1_SWCTRL BIT(6) 3181 #define B_AX_GNT_BT_RFC_S0_VAL BIT(5) 3182 #define B_AX_GNT_BT_RFC_S0_SWCTRL BIT(4) 3183 #define B_AX_GNT_WL_RFC_S0_VAL BIT(3) 3184 #define B_AX_GNT_WL_RFC_S0_SWCTRL BIT(2) 3185 #define B_AX_GNT_WL_BB_VAL BIT(1) 3186 #define B_AX_GNT_WL_BB_SWCTRL BIT(0) 3187 3188 #define R_AX_GNT_VAL 0x0054 3189 #define B_AX_GNT_BT_RFC_S1_STA BIT(5) 3190 #define B_AX_GNT_WL_RFC_S1_STA BIT(4) 3191 #define B_AX_GNT_BT_RFC_S0_STA BIT(3) 3192 #define B_AX_GNT_WL_RFC_S0_STA BIT(2) 3193 3194 #define R_AX_GNT_VAL_V1 0xDA4C 3195 #define B_AX_GNT_BT_RFC_S1 BIT(4) 3196 #define B_AX_GNT_BT_RFC_S0 BIT(3) 3197 #define B_AX_GNT_WL_RFC_S1 BIT(2) 3198 #define B_AX_GNT_WL_RFC_S0 BIT(1) 3199 3200 #define R_AX_TDMA_MODE 0xDA4C 3201 #define R_AX_TDMA_MODE_C1 0xFA4C 3202 #define B_AX_R_BT_CMD_RPT_MASK GENMASK(31, 16) 3203 #define B_AX_R_RPT_FROM_BT_MASK GENMASK(15, 8) 3204 #define B_AX_BT_HID_ISR_SET_MASK GENMASK(7, 6) 3205 #define B_AX_TDMA_BT_START_NOTIFY BIT(5) 3206 #define B_AX_ENABLE_TDMA_FW_MODE BIT(4) 3207 #define B_AX_ENABLE_PTA_TDMA_MODE BIT(3) 3208 #define B_AX_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) 3209 #define B_AX_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) 3210 #define B_AX_RTK_BT_ENABLE BIT(0) 3211 3212 #define R_AX_BT_COEX_CFG_5 0xDA6C 3213 #define R_AX_BT_COEX_CFG_5_C1 0xFA6C 3214 #define B_AX_BT_TIME_MASK GENMASK(31, 6) 3215 #define B_AX_BT_RPT_SAMPLE_RATE_MASK GENMASK(5, 0) 3216 #define MAC_AX_RTK_RATE 5 3217 3218 #define R_AX_LTE_CTRL 0xDAF0 3219 #define R_AX_LTE_WDATA 0xDAF4 3220 #define R_AX_LTE_RDATA 0xDAF8 3221 3222 #define R_AX_MACID_ANT_TABLE 0xDC00 3223 #define R_AX_MACID_ANT_TABLE_LAST 0xDDFC 3224 3225 #define CMAC1_START_ADDR 0xE000 3226 #define CMAC1_END_ADDR 0xFFFF 3227 #define R_AX_CMAC_REG_END 0xFFFF 3228 3229 #define R_AX_LTE_SW_CFG_1 0x0038 3230 #define R_AX_LTE_SW_CFG_1_C1 0x2038 3231 #define B_AX_GNT_BT_RFC_S1_SW_VAL BIT(31) 3232 #define B_AX_GNT_BT_RFC_S1_SW_CTRL BIT(30) 3233 #define B_AX_GNT_WL_RFC_S1_SW_VAL BIT(29) 3234 #define B_AX_GNT_WL_RFC_S1_SW_CTRL BIT(28) 3235 #define B_AX_GNT_BT_BB_S1_SW_VAL BIT(27) 3236 #define B_AX_GNT_BT_BB_S1_SW_CTRL BIT(26) 3237 #define B_AX_GNT_WL_BB_S1_SW_VAL BIT(25) 3238 #define B_AX_GNT_WL_BB_S1_SW_CTRL BIT(24) 3239 #define B_AX_BT_SW_CTRL_WL_PRIORITY BIT(19) 3240 #define B_AX_WL_SW_CTRL_WL_PRIORITY BIT(18) 3241 #define B_AX_LTE_PATTERN_2_EN BIT(17) 3242 #define B_AX_LTE_PATTERN_1_EN BIT(16) 3243 #define B_AX_GNT_BT_RFC_S0_SW_VAL BIT(15) 3244 #define B_AX_GNT_BT_RFC_S0_SW_CTRL BIT(14) 3245 #define B_AX_GNT_WL_RFC_S0_SW_VAL BIT(13) 3246 #define B_AX_GNT_WL_RFC_S0_SW_CTRL BIT(12) 3247 #define B_AX_GNT_BT_BB_S0_SW_VAL BIT(11) 3248 #define B_AX_GNT_BT_BB_S0_SW_CTRL BIT(10) 3249 #define B_AX_GNT_WL_BB_S0_SW_VAL BIT(9) 3250 #define B_AX_GNT_WL_BB_S0_SW_CTRL BIT(8) 3251 #define B_AX_LTECOEX_FUN_EN BIT(7) 3252 #define B_AX_LTECOEX_3WIRE_CTRL_MUX BIT(6) 3253 #define B_AX_LTECOEX_OP_MODE_SEL_MASK GENMASK(5, 4) 3254 #define B_AX_LTECOEX_UART_MUX BIT(3) 3255 #define B_AX_LTECOEX_UART_MODE_SEL_MASK GENMASK(2, 0) 3256 3257 #define R_AX_LTE_SW_CFG_2 0x003C 3258 #define R_AX_LTE_SW_CFG_2_C1 0x203C 3259 #define B_AX_WL_RX_CTRL BIT(8) 3260 #define B_AX_GNT_WL_RX_SW_VAL BIT(7) 3261 #define B_AX_GNT_WL_RX_SW_CTRL BIT(6) 3262 #define B_AX_GNT_WL_TX_SW_VAL BIT(5) 3263 #define B_AX_GNT_WL_TX_SW_CTRL BIT(4) 3264 #define B_AX_GNT_BT_RX_SW_VAL BIT(3) 3265 #define B_AX_GNT_BT_RX_SW_CTRL BIT(2) 3266 #define B_AX_GNT_BT_TX_SW_VAL BIT(1) 3267 #define B_AX_GNT_BT_TX_SW_CTRL BIT(0) 3268 3269 #define RR_MOD 0x00 3270 #define RR_MOD_V1 0x10000 3271 #define RR_MOD_IQK GENMASK(19, 4) 3272 #define RR_MOD_DPK GENMASK(19, 5) 3273 #define RR_MOD_MASK GENMASK(19, 16) 3274 #define RR_MOD_V_DOWN 0x0 3275 #define RR_MOD_V_STANDBY 0x1 3276 #define RR_MOD_V_TX 0x2 3277 #define RR_MOD_V_RX 0x3 3278 #define RR_MOD_V_TXIQK 0x4 3279 #define RR_MOD_V_DPK 0x5 3280 #define RR_MOD_V_RXK1 0x6 3281 #define RR_MOD_V_RXK2 0x7 3282 #define RR_MOD_NBW GENMASK(15, 14) 3283 #define RR_MOD_M_RXG GENMASK(13, 4) 3284 #define RR_MOD_M_RXBB GENMASK(9, 5) 3285 #define RR_MODOPT 0x01 3286 #define RR_MODOPT_M_TXPWR GENMASK(5, 0) 3287 #define RR_WLSEL 0x02 3288 #define RR_WLSEL_AG GENMASK(18, 16) 3289 #define RR_RSV1 0x05 3290 #define RR_RSV1_RST BIT(0) 3291 #define RR_BBDC 0x10005 3292 #define RR_BBDC_SEL BIT(0) 3293 #define RR_DTXLOK 0x08 3294 #define RR_RSV2 0x09 3295 #define RR_LOKVB 0x0a 3296 #define RR_LOKVB_COI GENMASK(19, 14) 3297 #define RR_LOKVB_COQ GENMASK(9, 4) 3298 #define RR_TXIG 0x11 3299 #define RR_TXIG_TG GENMASK(16, 12) 3300 #define RR_TXIG_GR1 GENMASK(6, 4) 3301 #define RR_TXIG_GR0 GENMASK(1, 0) 3302 #define RR_CHTR 0x17 3303 #define RR_CHTR_MOD GENMASK(11, 10) 3304 #define RR_CHTR_TXRX GENMASK(9, 0) 3305 #define RR_CFGCH 0x18 3306 #define RR_CFGCH_V1 0x10018 3307 #define RR_CFGCH_BAND1 GENMASK(17, 16) 3308 #define CFGCH_BAND1_2G 0 3309 #define CFGCH_BAND1_5G 1 3310 #define CFGCH_BAND1_6G 3 3311 #define RR_CFGCH_BAND0 GENMASK(9, 8) 3312 #define CFGCH_BAND0_2G 0 3313 #define CFGCH_BAND0_5G 1 3314 #define CFGCH_BAND0_6G 0 3315 #define RR_CFGCH_BW GENMASK(11, 10) 3316 #define RR_CFGCH_CH GENMASK(7, 0) 3317 #define CFGCH_BW_20M 3 3318 #define CFGCH_BW_40M 2 3319 #define CFGCH_BW_80M 1 3320 #define CFGCH_BW_160M 0 3321 #define RR_APK 0x19 3322 #define RR_APK_MOD GENMASK(5, 4) 3323 #define RR_BTC 0x1a 3324 #define RR_BTC_TXBB GENMASK(14, 12) 3325 #define RR_BTC_RXBB GENMASK(11, 10) 3326 #define RR_RCKC 0x1b 3327 #define RR_RCKC_CA GENMASK(14, 10) 3328 #define RR_RCKS 0x1c 3329 #define RR_RCKO 0x1d 3330 #define RR_RCKO_OFF GENMASK(13, 9) 3331 #define RR_RXKPLL 0x1e 3332 #define RR_RXKPLL_OFF GENMASK(5, 0) 3333 #define RR_RXKPLL_POW BIT(19) 3334 #define RR_RSV4 0x1f 3335 #define RR_RSV4_AGH GENMASK(17, 16) 3336 #define RR_RSV4_PLLCH GENMASK(9, 0) 3337 #define RR_RXK 0x20 3338 #define RR_RXK_SEL2G BIT(8) 3339 #define RR_RXK_SEL5G BIT(7) 3340 #define RR_RXK_PLLEN BIT(5) 3341 #define RR_LUTWA 0x33 3342 #define RR_LUTWA_MASK GENMASK(9, 0) 3343 #define RR_LUTWA_M2 GENMASK(4, 0) 3344 #define RR_LUTWD1 0x3e 3345 #define RR_LUTWD0 0x3f 3346 #define RR_LUTWD0_LB GENMASK(5, 0) 3347 #define RR_TM 0x42 3348 #define RR_TM_TRI BIT(19) 3349 #define RR_TM_VAL GENMASK(6, 1) 3350 #define RR_TM2 0x43 3351 #define RR_TM2_OFF GENMASK(19, 16) 3352 #define RR_TXG1 0x51 3353 #define RR_TXG1_ATT2 BIT(19) 3354 #define RR_TXG1_ATT1 BIT(11) 3355 #define RR_TXG2 0x52 3356 #define RR_TXG2_ATT0 BIT(11) 3357 #define RR_BSPAD 0x54 3358 #define RR_TXGA 0x55 3359 #define RR_TXGA_TRK_EN BIT(7) 3360 #define RR_TXGA_LOK_EXT GENMASK(4, 0) 3361 #define RR_TXGA_LOK_EN BIT(0) 3362 #define RR_GAINTX 0x56 3363 #define RR_GAINTX_ALL GENMASK(15, 0) 3364 #define RR_GAINTX_PAD GENMASK(9, 5) 3365 #define RR_GAINTX_BB GENMASK(4, 0) 3366 #define RR_TXMO 0x58 3367 #define RR_TXMO_COI GENMASK(19, 15) 3368 #define RR_TXMO_COQ GENMASK(14, 10) 3369 #define RR_TXMO_FII GENMASK(9, 6) 3370 #define RR_TXMO_FIQ GENMASK(5, 2) 3371 #define RR_TXA 0x5d 3372 #define RR_TXA_TRK GENMASK(19, 14) 3373 #define RR_TXRSV 0x5c 3374 #define RR_TXRSV_GAPK BIT(19) 3375 #define RR_BIAS 0x5e 3376 #define RR_BIAS_GAPK BIT(19) 3377 #define RR_BIASA 0x60 3378 #define RR_BIASA_TXG GENMASK(15, 12) 3379 #define RR_BIASA_TXA GENMASK(19, 16) 3380 #define RR_BIASA_A GENMASK(2, 0) 3381 #define RR_BIASA2 0x63 3382 #define RR_BIASA2_LB GENMASK(4, 2) 3383 #define RR_TXATANK 0x64 3384 #define RR_TXATANK_LBSW2 GENMASK(17, 15) 3385 #define RR_TXATANK_LBSW GENMASK(16, 15) 3386 #define RR_TXA2 0x65 3387 #define RR_TXA2_LDO GENMASK(19, 16) 3388 #define RR_TRXIQ 0x66 3389 #define RR_RSV6 0x6d 3390 #define RR_TXPOW 0x7f 3391 #define RR_TXPOW_TXA BIT(8) 3392 #define RR_TXPOW_TXAS BIT(7) 3393 #define RR_TXPOW_TXG BIT(1) 3394 #define RR_RXPOW 0x80 3395 #define RR_RXPOW_IQK GENMASK(17, 16) 3396 #define RR_RXBB 0x83 3397 #define RR_RXBB_VOBUF GENMASK(15, 12) 3398 #define RR_RXBB_C2G GENMASK(16, 10) 3399 #define RR_RXBB_C1G GENMASK(9, 8) 3400 #define RR_RXBB_ATTR GENMASK(7, 4) 3401 #define RR_RXBB_ATTC GENMASK(2, 0) 3402 #define RR_RXG 0x84 3403 #define RR_RXG_IQKMOD GENMASK(19, 16) 3404 #define RR_XGLNA2 0x85 3405 #define RR_XGLNA2_SW GENMASK(1, 0) 3406 #define RR_RXAE 0x89 3407 #define RR_RXAE_IQKMOD GENMASK(3, 0) 3408 #define RR_RXA 0x8a 3409 #define RR_RXA_DPK GENMASK(9, 8) 3410 #define RR_RXA2 0x8c 3411 #define RR_RXA2_C1 GENMASK(12, 10) 3412 #define RR_RXA2_C2 GENMASK(9, 3) 3413 #define RR_RXA2_IATT GENMASK(7, 4) 3414 #define RR_RXA2_ATT GENMASK(3, 0) 3415 #define RR_RXIQGEN 0x8d 3416 #define RR_RXIQGEN_ATTL GENMASK(12, 8) 3417 #define RR_RXIQGEN_ATTH GENMASK(14, 13) 3418 #define RR_RXBB2 0x8f 3419 #define RR_RXBB2_DAC_EN BIT(13) 3420 #define RR_RXBB2_CKT BIT(12) 3421 #define RR_EN_TIA_IDA GENMASK(11, 10) 3422 #define RR_RXBB2_IDAC GENMASK(11, 9) 3423 #define RR_RXBB2_EBW GENMASK(6, 5) 3424 #define RR_XALNA2 0x90 3425 #define RR_XALNA2_SW GENMASK(1, 0) 3426 #define RR_DCK 0x92 3427 #define RR_DCK_DONE GENMASK(7, 5) 3428 #define RR_DCK_FINE BIT(1) 3429 #define RR_DCK_LV BIT(0) 3430 #define RR_DCK1 0x93 3431 #define RR_DCK1_DONE BIT(5) 3432 #define RR_DCK1_CLR GENMASK(3, 0) 3433 #define RR_DCK1_SEL BIT(3) 3434 #define RR_DCK2 0x94 3435 #define RR_DCK2_CYCLE GENMASK(7, 2) 3436 #define RR_DCKC 0x95 3437 #define RR_DCKC_CHK BIT(3) 3438 #define RR_IQGEN 0x97 3439 #define RR_IQGEN_BIAS GENMASK(11, 8) 3440 #define RR_TXIQK 0x98 3441 #define RR_TXIQK_ATT2 GENMASK(15, 12) 3442 #define RR_TIA 0x9e 3443 #define RR_TIA_N6 BIT(8) 3444 #define RR_MIXER 0x9f 3445 #define RR_MIXER_GN GENMASK(4, 3) 3446 #define RR_LOGEN 0xa3 3447 #define RR_LOGEN_RPT GENMASK(19, 16) 3448 #define RR_XTALX2 0xb8 3449 #define RR_MALSEL 0xbe 3450 #define RR_LCK_TRG 0xd3 3451 #define RR_LCK_TRGSEL BIT(8) 3452 #define RR_IQKPLL 0xdc 3453 #define RR_IQKPLL_MOD GENMASK(9, 8) 3454 #define RR_RCKD 0xde 3455 #define RR_RCKD_POW GENMASK(19, 13) 3456 #define RR_RCKD_BW BIT(2) 3457 #define RR_TXADBG 0xde 3458 #define RR_LUTDBG 0xdf 3459 #define RR_LUTDBG_TIA BIT(12) 3460 #define RR_LUTDBG_LOK BIT(2) 3461 #define RR_LUTWE2 0xee 3462 #define RR_LUTWE2_RTXBW BIT(2) 3463 #define RR_LUTWE 0xef 3464 #define RR_LUTWE_LOK BIT(2) 3465 #define RR_RFC 0xf0 3466 #define RR_RFC_CKEN BIT(1) 3467 3468 #define R_UPD_P0 0x0000 3469 #define R_RSTB_WATCH_DOG 0x000C 3470 #define B_P0_RSTB_WATCH_DOG BIT(0) 3471 #define B_P1_RSTB_WATCH_DOG BIT(1) 3472 #define B_UPD_P0_EN BIT(31) 3473 #define R_ANAPAR_PW15 0x030C 3474 #define B_ANAPAR_PW15 GENMASK(31, 24) 3475 #define B_ANAPAR_PW15_H GENMASK(27, 24) 3476 #define B_ANAPAR_PW15_H2 GENMASK(27, 26) 3477 #define R_ANAPAR 0x032C 3478 #define B_ANAPAR_15 GENMASK(31, 16) 3479 #define B_ANAPAR_ADCCLK BIT(30) 3480 #define B_ANAPAR_FLTRST BIT(22) 3481 #define B_ANAPAR_CRXBB GENMASK(18, 16) 3482 #define B_ANAPAR_14 GENMASK(15, 0) 3483 #define R_RFE_E_A2 0x0334 3484 #define R_RFE_O_SEL_A2 0x0338 3485 #define R_RFE_SEL0_A2 0x033C 3486 #define R_RFE_SEL32_A2 0x0340 3487 #define R_SWSI_DATA_V1 0x0370 3488 #define B_SWSI_DATA_VAL_V1 GENMASK(19, 0) 3489 #define B_SWSI_DATA_ADDR_V1 GENMASK(27, 20) 3490 #define B_SWSI_DATA_PATH_V1 GENMASK(30, 28) 3491 #define B_SWSI_DATA_BIT_MASK_EN_V1 BIT(31) 3492 #define R_SWSI_BIT_MASK_V1 0x0374 3493 #define B_SWSI_BIT_MASK_V1 GENMASK(19, 0) 3494 #define R_SWSI_READ_ADDR_V1 0x0378 3495 #define B_SWSI_READ_ADDR_ADDR_V1 GENMASK(7, 0) 3496 #define B_SWSI_READ_ADDR_PATH_V1 GENMASK(10, 8) 3497 #define B_SWSI_READ_ADDR_V1 GENMASK(10, 0) 3498 #define R_UPD_CLK_ADC 0x0700 3499 #define B_UPD_CLK_ADC_VAL GENMASK(26, 25) 3500 #define B_UPD_CLK_ADC_ON BIT(24) 3501 #define B_ENABLE_CCK BIT(5) 3502 #define R_RSTB_ASYNC 0x0704 3503 #define B_RSTB_ASYNC_ALL BIT(1) 3504 #define R_MAC_PIN_SEL 0x0734 3505 #define B_CH_IDX_SEG0 GENMASK(23, 16) 3506 #define R_PLCP_HISTOGRAM 0x0738 3507 #define B_STS_PARSING_TIME GENMASK(19, 16) 3508 #define B_STS_DIS_TRIG_BY_FAIL BIT(3) 3509 #define B_STS_DIS_TRIG_BY_BRK BIT(2) 3510 #define R_PHY_STS_BITMAP_ADDR_START R_PHY_STS_BITMAP_SEARCH_FAIL 3511 #define B_PHY_STS_BITMAP_ADDR_MASK GENMASK(6, 2) 3512 #define R_PHY_STS_BITMAP_SEARCH_FAIL 0x073C 3513 #define B_PHY_STS_BITMAP_MSK_52A 0x337cff3f 3514 #define R_PHY_STS_BITMAP_R2T 0x0740 3515 #define R_PHY_STS_BITMAP_CCA_SPOOF 0x0744 3516 #define R_PHY_STS_BITMAP_OFDM_BRK 0x0748 3517 #define R_PHY_STS_BITMAP_CCK_BRK 0x074C 3518 #define R_PHY_STS_BITMAP_DL_MU_SPOOF 0x0750 3519 #define R_PHY_STS_BITMAP_HE_MU 0x0754 3520 #define R_PHY_STS_BITMAP_VHT_MU 0x0758 3521 #define R_PHY_STS_BITMAP_UL_TB_SPOOF 0x075C 3522 #define R_PHY_STS_BITMAP_TRIGBASE 0x0760 3523 #define R_PHY_STS_BITMAP_CCK 0x0764 3524 #define R_PHY_STS_BITMAP_LEGACY 0x0768 3525 #define R_PHY_STS_BITMAP_HT 0x076C 3526 #define R_PHY_STS_BITMAP_VHT 0x0770 3527 #define R_PHY_STS_BITMAP_HE 0x0774 3528 #define R_PMAC_GNT 0x0980 3529 #define B_PMAC_GNT_TXEN BIT(0) 3530 #define B_PMAC_GNT_RXEN BIT(16) 3531 #define B_PMAC_GNT_P1 GENMASK(20, 17) 3532 #define B_PMAC_GNT_P2 GENMASK(29, 26) 3533 #define R_PMAC_RX_CFG1 0x0988 3534 #define B_PMAC_OPT1_MSK GENMASK(11, 0) 3535 #define R_PMAC_RXMOD 0x0994 3536 #define B_PMAC_RXMOD_MSK GENMASK(7, 4) 3537 #define R_MAC_SEL 0x09A4 3538 #define B_MAC_SEL_OFDM_TRI_FILTER BIT(31) 3539 #define B_MAC_SEL_PWR_EN BIT(16) 3540 #define B_MAC_SEL_DPD_EN BIT(10) 3541 #define B_MAC_SEL_MOD GENMASK(4, 2) 3542 #define R_PMAC_TX_CTRL 0x09C0 3543 #define B_PMAC_TXEN_DIS BIT(0) 3544 #define R_PMAC_TX_PRD 0x09C4 3545 #define B_PMAC_TX_PRD_MSK GENMASK(31, 8) 3546 #define B_PMAC_CTX_EN BIT(0) 3547 #define B_PMAC_PTX_EN BIT(4) 3548 #define R_PMAC_TX_CNT 0x09C8 3549 #define B_PMAC_TX_CNT_MSK GENMASK(31, 0) 3550 #define R_P80_AT_HIGH_FREQ 0x09D8 3551 #define B_P80_AT_HIGH_FREQ BIT(26) 3552 #define R_DBCC_80P80_SEL_EVM_RPT 0x0A10 3553 #define B_DBCC_80P80_SEL_EVM_RPT_EN BIT(0) 3554 #define R_CCX 0x0C00 3555 #define B_CCX_EDCCA_OPT_MSK GENMASK(6, 4) 3556 #define B_MEASUREMENT_TRIG_MSK BIT(2) 3557 #define B_CCX_TRIG_OPT_MSK BIT(1) 3558 #define B_CCX_EN_MSK BIT(0) 3559 #define R_IFS_COUNTER 0x0C28 3560 #define B_IFS_CLM_PERIOD_MSK GENMASK(31, 16) 3561 #define B_IFS_CLM_COUNTER_UNIT_MSK GENMASK(15, 14) 3562 #define B_IFS_COUNTER_CLR_MSK BIT(13) 3563 #define B_IFS_COLLECT_EN BIT(12) 3564 #define R_IFS_T1 0x0C2C 3565 #define B_IFS_T1_TH_HIGH_MSK GENMASK(31, 16) 3566 #define B_IFS_T1_EN_MSK BIT(15) 3567 #define B_IFS_T1_TH_LOW_MSK GENMASK(14, 0) 3568 #define R_IFS_T2 0x0C30 3569 #define B_IFS_T2_TH_HIGH_MSK GENMASK(31, 16) 3570 #define B_IFS_T2_EN_MSK BIT(15) 3571 #define B_IFS_T2_TH_LOW_MSK GENMASK(14, 0) 3572 #define R_IFS_T3 0x0C34 3573 #define B_IFS_T3_TH_HIGH_MSK GENMASK(31, 16) 3574 #define B_IFS_T3_EN_MSK BIT(15) 3575 #define B_IFS_T3_TH_LOW_MSK GENMASK(14, 0) 3576 #define R_IFS_T4 0x0C38 3577 #define B_IFS_T4_TH_HIGH_MSK GENMASK(31, 16) 3578 #define B_IFS_T4_EN_MSK BIT(15) 3579 #define B_IFS_T4_TH_LOW_MSK GENMASK(14, 0) 3580 #define R_PD_CTRL 0x0C3C 3581 #define B_PD_HIT_DIS BIT(9) 3582 #define R_IOQ_IQK_DPK 0x0C60 3583 #define B_IOQ_IQK_DPK_EN BIT(1) 3584 #define R_GNT_BT_WGT_EN 0x0C6C 3585 #define B_GNT_BT_WGT_EN BIT(21) 3586 #define R_PD_ARBITER_OFF 0x0C80 3587 #define B_PD_ARBITER_OFF BIT(31) 3588 #define R_SNDCCA_A1 0x0C9C 3589 #define B_SNDCCA_A1_EN GENMASK(19, 12) 3590 #define R_SNDCCA_A2 0x0CA0 3591 #define B_SNDCCA_A2_VAL GENMASK(19, 12) 3592 #define R_RXHT_MCS_LIMIT 0x0D18 3593 #define B_RXHT_MCS_LIMIT GENMASK(9, 8) 3594 #define R_RXVHT_MCS_LIMIT 0x0D18 3595 #define B_RXVHT_MCS_LIMIT GENMASK(22, 21) 3596 #define R_P0_EN_SOUND_WO_NDP 0x0D7C 3597 #define B_P0_EN_SOUND_WO_NDP BIT(1) 3598 #define R_RXHE 0x0D80 3599 #define B_RXHETB_MAX_NSS GENMASK(25, 23) 3600 #define B_RXHE_MAX_NSS GENMASK(16, 14) 3601 #define B_RXHE_USER_MAX GENMASK(13, 6) 3602 #define R_SPOOF_ASYNC_RST 0x0D84 3603 #define B_SPOOF_ASYNC_RST BIT(15) 3604 #define R_NDP_BRK0 0xDA0 3605 #define R_NDP_BRK1 0xDA4 3606 #define B_NDP_RU_BRK BIT(0) 3607 #define R_BRK_ASYNC_RST_EN_1 0x0DC0 3608 #define R_BRK_ASYNC_RST_EN_2 0x0DC4 3609 #define R_BRK_ASYNC_RST_EN_3 0x0DC8 3610 #define R_S0_HW_SI_DIS 0x1200 3611 #define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28) 3612 #define R_P0_RXCK 0x12A0 3613 #define B_P0_RXCK_BW3 BIT(30) 3614 #define B_P0_TXCK_ALL GENMASK(19, 12) 3615 #define B_P0_RXCK_ON BIT(19) 3616 #define B_P0_RXCK_VAL GENMASK(18, 16) 3617 #define B_P0_TXCK_ON BIT(15) 3618 #define B_P0_TXCK_VAL GENMASK(14, 12) 3619 #define R_P0_RFMODE 0x12AC 3620 #define B_P0_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4) 3621 #define B_P0_RFMODE_MUX GENMASK(11, 4) 3622 #define R_P0_NRBW 0x12B8 3623 #define B_P0_NRBW_DBG BIT(30) 3624 #define R_S0_RXDC 0x12D4 3625 #define B_S0_RXDC_I GENMASK(25, 16) 3626 #define B_S0_RXDC_Q GENMASK(31, 26) 3627 #define R_S0_RXDC2 0x12D8 3628 #define B_S0_RXDC2_SEL GENMASK(9, 8) 3629 #define B_S0_RXDC2_AVG GENMASK(7, 6) 3630 #define B_S0_RXDC2_MEN GENMASK(5, 4) 3631 #define B_S0_RXDC2_Q2 GENMASK(3, 0) 3632 #define R_CFO_COMP_SEG0_L 0x1384 3633 #define R_CFO_COMP_SEG0_H 0x1388 3634 #define R_CFO_COMP_SEG0_CTRL 0x138C 3635 #define R_DBG32_D 0x1730 3636 #define R_SWSI_V1 0x174C 3637 #define B_SWSI_W_BUSY_V1 BIT(24) 3638 #define B_SWSI_R_BUSY_V1 BIT(25) 3639 #define B_SWSI_R_DATA_DONE_V1 BIT(26) 3640 #define R_TX_COUNTER 0x1A40 3641 #define R_IFS_CLM_TX_CNT 0x1ACC 3642 #define B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK GENMASK(31, 16) 3643 #define B_IFS_CLM_TX_CNT_MSK GENMASK(15, 0) 3644 #define R_IFS_CLM_CCA 0x1AD0 3645 #define B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK GENMASK(31, 16) 3646 #define B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK GENMASK(15, 0) 3647 #define R_IFS_CLM_FA 0x1AD4 3648 #define B_IFS_CLM_OFDM_FA_MSK GENMASK(31, 16) 3649 #define B_IFS_CLM_CCK_FA_MSK GENMASK(15, 0) 3650 #define R_IFS_HIS 0x1AD8 3651 #define B_IFS_T4_HIS_MSK GENMASK(31, 24) 3652 #define B_IFS_T3_HIS_MSK GENMASK(23, 16) 3653 #define B_IFS_T2_HIS_MSK GENMASK(15, 8) 3654 #define B_IFS_T1_HIS_MSK GENMASK(7, 0) 3655 #define R_IFS_AVG_L 0x1ADC 3656 #define B_IFS_T2_AVG_MSK GENMASK(31, 16) 3657 #define B_IFS_T1_AVG_MSK GENMASK(15, 0) 3658 #define R_IFS_AVG_H 0x1AE0 3659 #define B_IFS_T4_AVG_MSK GENMASK(31, 16) 3660 #define B_IFS_T3_AVG_MSK GENMASK(15, 0) 3661 #define R_IFS_CCA_L 0x1AE4 3662 #define B_IFS_T2_CCA_MSK GENMASK(31, 16) 3663 #define B_IFS_T1_CCA_MSK GENMASK(15, 0) 3664 #define R_IFS_CCA_H 0x1AE8 3665 #define B_IFS_T4_CCA_MSK GENMASK(31, 16) 3666 #define B_IFS_T3_CCA_MSK GENMASK(15, 0) 3667 #define R_IFSCNT 0x1AEC 3668 #define B_IFSCNT_DONE_MSK BIT(16) 3669 #define B_IFSCNT_TOTAL_CNT_MSK GENMASK(15, 0) 3670 #define R_TXAGC_TP 0x1C04 3671 #define B_TXAGC_TP GENMASK(2, 0) 3672 #define R_TSSI_THER 0x1C10 3673 #define B_TSSI_THER GENMASK(29, 24) 3674 #define R_TXAGC_BTP 0x1CA0 3675 #define B_TXAGC_BTP GENMASK(31, 24) 3676 #define R_TXAGC_BB 0x1C60 3677 #define B_TXAGC_BB_OFT GENMASK(31, 16) 3678 #define B_TXAGC_BB GENMASK(31, 24) 3679 #define R_S0_ADDCK 0x1E00 3680 #define B_S0_ADDCK_I GENMASK(9, 0) 3681 #define B_S0_ADDCK_Q GENMASK(19, 10) 3682 #define R_ADC_FIFO 0x20fc 3683 #define B_ADC_FIFO_RST GENMASK(31, 24) 3684 #define B_ADC_FIFO_RXK GENMASK(31, 16) 3685 #define B_ADC_FIFO_A3 BIT(28) 3686 #define B_ADC_FIFO_A2 BIT(24) 3687 #define B_ADC_FIFO_A1 BIT(20) 3688 #define B_ADC_FIFO_A0 BIT(16) 3689 #define R_TXFIR0 0x2300 3690 #define B_TXFIR_C01 GENMASK(23, 0) 3691 #define R_TXFIR2 0x2304 3692 #define B_TXFIR_C23 GENMASK(23, 0) 3693 #define R_TXFIR4 0x2308 3694 #define B_TXFIR_C45 GENMASK(23, 0) 3695 #define R_TXFIR6 0x230c 3696 #define B_TXFIR_C67 GENMASK(23, 0) 3697 #define R_TXFIR8 0x2310 3698 #define B_TXFIR_C89 GENMASK(23, 0) 3699 #define R_TXFIRA 0x2314 3700 #define B_TXFIR_CAB GENMASK(23, 0) 3701 #define R_TXFIRC 0x2318 3702 #define B_TXFIR_CCD GENMASK(23, 0) 3703 #define R_TXFIRE 0x231c 3704 #define B_TXFIR_CEF GENMASK(23, 0) 3705 #define R_11B_RX_V1 0x2320 3706 #define B_11B_RXCCA_DIS_V1 BIT(0) 3707 #define R_RPL_OFST 0x2340 3708 #define B_RPL_OFST_MASK GENMASK(14, 8) 3709 #define R_RXCCA 0x2344 3710 #define B_RXCCA_DIS BIT(31) 3711 #define R_RXCCA_V1 0x2320 3712 #define B_RXCCA_DIS_V1 BIT(0) 3713 #define R_RXSC 0x237C 3714 #define B_RXSC_EN BIT(0) 3715 #define R_RXSCOBC 0x23B0 3716 #define B_RXSCOBC_TH GENMASK(18, 0) 3717 #define R_RXSCOCCK 0x23B4 3718 #define B_RXSCOCCK_TH GENMASK(18, 0) 3719 #define R_P80_AT_HIGH_FREQ_RU_ALLOC 0x2410 3720 #define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1 BIT(14) 3721 #define B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0 BIT(13) 3722 #define R_DBCC_80P80_SEL_EVM_RPT2 0x2A10 3723 #define B_DBCC_80P80_SEL_EVM_RPT2_EN BIT(0) 3724 #define R_P1_EN_SOUND_WO_NDP 0x2D7C 3725 #define B_P1_EN_SOUND_WO_NDP BIT(1) 3726 #define R_S1_HW_SI_DIS 0x3200 3727 #define B_S1_HW_SI_DIS_W_R_TRIG GENMASK(30, 28) 3728 #define R_P1_RFMODE 0x32AC 3729 #define B_P1_RFMODE_ORI_TXRX_FTM_TX GENMASK(31, 4) 3730 #define B_P1_RFMODE_MUX GENMASK(11, 4) 3731 #define R_P1_DBGMOD 0x32B8 3732 #define B_P1_DBGMOD_ON BIT(30) 3733 #define R_S1_RXDC 0x32D4 3734 #define B_S1_RXDC_I GENMASK(25, 16) 3735 #define B_S1_RXDC_Q GENMASK(31, 26) 3736 #define R_S1_RXDC2 0x32D8 3737 #define B_S1_RXDC2_EN GENMASK(5, 4) 3738 #define B_S1_RXDC2_SEL GENMASK(9, 8) 3739 #define B_S1_RXDC2_Q2 GENMASK(3, 0) 3740 #define R_TXAGC_BB_S1 0x3C60 3741 #define B_TXAGC_BB_S1_OFT GENMASK(31, 16) 3742 #define B_TXAGC_BB_S1 GENMASK(31, 24) 3743 #define R_S1_ADDCK 0x3E00 3744 #define B_S1_ADDCK_I GENMASK(9, 0) 3745 #define B_S1_ADDCK_Q GENMASK(19, 10) 3746 #define R_MUIC 0x40F8 3747 #define B_MUIC_EN BIT(0) 3748 #define R_DCFO 0x4264 3749 #define B_DCFO GENMASK(1, 0) 3750 #define R_SEG0CSI 0x42AC 3751 #define B_SEG0CSI_IDX GENMASK(11, 0) 3752 #define R_SEG0CSI_EN 0x42C4 3753 #define B_SEG0CSI_EN BIT(23) 3754 #define R_BSS_CLR_MAP 0x43ac 3755 #define B_BSS_CLR_MAP_VLD0 BIT(28) 3756 #define B_BSS_CLR_MAP_TGT GENMASK(27, 22) 3757 #define B_BSS_CLR_MAP_STAID GENMASK(21, 11) 3758 #define R_CFO_TRK0 0x4404 3759 #define R_CFO_TRK1 0x440C 3760 #define B_CFO_TRK_MSK GENMASK(14, 10) 3761 #define R_T2F_GI_COMB 0x4424 3762 #define B_T2F_GI_COMB_EN BIT(2) 3763 #define R_BT_DYN_DC_EST_EN 0x441C 3764 #define B_BT_DYN_DC_EST_EN_MSK BIT(31) 3765 #define R_ASSIGN_SBD_OPT 0x4450 3766 #define B_ASSIGN_SBD_OPT_EN BIT(24) 3767 #define R_DCFO_COMP_S0 0x448C 3768 #define B_DCFO_COMP_S0_MSK GENMASK(11, 0) 3769 #define R_DCFO_WEIGHT 0x4490 3770 #define B_DCFO_WEIGHT_MSK GENMASK(27, 24) 3771 #define R_DCFO_OPT 0x4494 3772 #define B_DCFO_OPT_EN BIT(29) 3773 #define R_BANDEDGE 0x4498 3774 #define B_BANDEDGE_EN BIT(30) 3775 #define R_TXPATH_SEL 0x458C 3776 #define B_TXPATH_SEL_MSK GENMASK(31, 28) 3777 #define R_TXPWR 0x4594 3778 #define B_TXPWR_MSK GENMASK(30, 22) 3779 #define R_TXNSS_MAP 0x45B4 3780 #define B_TXNSS_MAP_MSK GENMASK(20, 17) 3781 #define R_PCOEFF0_V1 0x45BC 3782 #define B_PCOEFF01_MSK_V1 GENMASK(23, 0) 3783 #define R_PCOEFF2_V1 0x45CC 3784 #define B_PCOEFF23_MSK_V1 GENMASK(23, 0) 3785 #define R_PCOEFF4_V1 0x45D0 3786 #define B_PCOEFF45_MSK_V1 GENMASK(23, 0) 3787 #define R_PCOEFF6_V1 0x45D4 3788 #define B_PCOEFF67_MSK_V1 GENMASK(23, 0) 3789 #define R_PCOEFF8_V1 0x45D8 3790 #define B_PCOEFF89_MSK_V1 GENMASK(23, 0) 3791 #define R_PCOEFFA_V1 0x45C0 3792 #define B_PCOEFFAB_MSK_V1 GENMASK(23, 0) 3793 #define R_PCOEFFC_V1 0x45C4 3794 #define B_PCOEFFCD_MSK_V1 GENMASK(23, 0) 3795 #define R_PCOEFFE_V1 0x45C8 3796 #define B_PCOEFFEF_MSK_V1 GENMASK(23, 0) 3797 #define R_PATH0_IB_PKPW 0x4628 3798 #define B_PATH0_IB_PKPW_MSK GENMASK(11, 6) 3799 #define R_PATH0_LNA_ERR1 0x462C 3800 #define B_PATH0_LNA_ERR_G1_A_MSK GENMASK(29, 24) 3801 #define B_PATH0_LNA_ERR_G0_G_MSK GENMASK(17, 12) 3802 #define B_PATH0_LNA_ERR_G0_A_MSK GENMASK(11, 6) 3803 #define R_PATH0_LNA_ERR2 0x4630 3804 #define B_PATH0_LNA_ERR_G2_G_MSK GENMASK(23, 18) 3805 #define B_PATH0_LNA_ERR_G2_A_MSK GENMASK(17, 12) 3806 #define B_PATH0_LNA_ERR_G1_G_MSK GENMASK(5, 0) 3807 #define R_PATH0_LNA_ERR3 0x4634 3808 #define B_PATH0_LNA_ERR_G4_G_MSK GENMASK(29, 24) 3809 #define B_PATH0_LNA_ERR_G4_A_MSK GENMASK(23, 18) 3810 #define B_PATH0_LNA_ERR_G3_G_MSK GENMASK(11, 6) 3811 #define B_PATH0_LNA_ERR_G3_A_MSK GENMASK(5, 0) 3812 #define R_PATH0_LNA_ERR4 0x4638 3813 #define B_PATH0_LNA_ERR_G6_A_MSK GENMASK(29, 24) 3814 #define B_PATH0_LNA_ERR_G5_G_MSK GENMASK(17, 12) 3815 #define B_PATH0_LNA_ERR_G5_A_MSK GENMASK(11, 6) 3816 #define R_PATH0_LNA_ERR5 0x463C 3817 #define B_PATH0_LNA_ERR_G6_G_MSK GENMASK(5, 0) 3818 #define R_PATH0_TIA_ERR_G0 0x4640 3819 #define B_PATH0_TIA_ERR_G0_G_MSK GENMASK(23, 18) 3820 #define B_PATH0_TIA_ERR_G0_A_MSK GENMASK(17, 12) 3821 #define R_PATH0_TIA_ERR_G1 0x4644 3822 #define B_PATH0_TIA_ERR_G1_SEL GENMASK(31, 30) 3823 #define B_PATH0_TIA_ERR_G1_G_MSK GENMASK(11, 6) 3824 #define B_PATH0_TIA_ERR_G1_A_MSK GENMASK(5, 0) 3825 #define R_PATH0_IB_PBK 0x4650 3826 #define B_PATH0_IB_PBK_MSK GENMASK(14, 10) 3827 #define R_PATH0_RXB_INIT 0x4658 3828 #define B_PATH0_RXB_INIT_IDX_MSK GENMASK(9, 5) 3829 #define R_PATH0_LNA_INIT 0x4668 3830 #define R_PATH0_LNA_INIT_V1 0x472C 3831 #define B_PATH0_LNA_INIT_IDX_MSK GENMASK(26, 24) 3832 #define R_PATH0_BTG 0x466C 3833 #define B_PATH0_BTG_SHEN GENMASK(18, 17) 3834 #define R_PATH0_TIA_INIT 0x4674 3835 #define B_PATH0_TIA_INIT_IDX_MSK BIT(17) 3836 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC 0x46A0 3837 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1 0x4C24 3838 #define R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2 0x46E8 3839 #define B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) 3840 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC 0x46A4 3841 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1 0x4C28 3842 #define R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2 0x46EC 3843 #define B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) 3844 #define R_PATH0_RXB_INIT_V1 0x46A8 3845 #define B_PATH0_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10) 3846 #define R_PATH0_G_LNA6_OP1DB_V1 0x4688 3847 #define B_PATH0_G_LNA6_OP1DB_V1 GENMASK(31, 24) 3848 #define R_PATH0_G_TIA0_LNA6_OP1DB_V1 0x4694 3849 #define B_PATH0_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0) 3850 #define R_PATH0_G_TIA1_LNA6_OP1DB_V1 0x4694 3851 #define B_PATH0_R_G_OFST_MASK GENMASK(23, 16) 3852 #define B_PATH0_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8) 3853 #define R_CDD_EVM_CHK_EN 0x46C0 3854 #define B_CDD_EVM_CHK_EN BIT(0) 3855 #define R_PATH0_BAND_SEL_V1 0x4738 3856 #define B_PATH0_BAND_SEL_MSK_V1 BIT(17) 3857 #define R_PATH0_BT_SHARE_V1 0x4738 3858 #define B_PATH0_BT_SHARE_V1 BIT(19) 3859 #define R_PATH0_BTG_PATH_V1 0x4738 3860 #define B_PATH0_BTG_PATH_V1 BIT(22) 3861 #define R_P0_NBIIDX 0x469C 3862 #define B_P0_NBIIDX_VAL GENMASK(11, 0) 3863 #define B_P0_NBIIDX_NOTCH_EN BIT(12) 3864 #define R_P0_BACKOFF_IBADC_V1 0x469C 3865 #define B_P0_BACKOFF_IBADC_V1 GENMASK(31, 26) 3866 #define B_P0_NBIIDX_NOTCH_EN_V1 BIT(12) 3867 #define R_P1_MODE 0x4718 3868 #define B_P1_MODE_SEL GENMASK(31, 30) 3869 #define R_P0_AGC_CTL 0x4730 3870 #define B_P0_AGC_EN BIT(31) 3871 #define R_PATH1_LNA_INIT 0x473C 3872 #define R_PATH1_LNA_INIT_V1 0x4A80 3873 #define B_PATH1_LNA_INIT_IDX_MSK GENMASK(26, 24) 3874 #define R_PATH0_TIA_INIT_V1 0x473C 3875 #define B_PATH0_TIA_INIT_IDX_MSK_V1 BIT(9) 3876 #define R_PATH1_TIA_INIT 0x4748 3877 #define B_PATH1_TIA_INIT_IDX_MSK BIT(17) 3878 #define R_PATH1_BTG 0x4740 3879 #define B_PATH1_BTG_SHEN GENMASK(18, 17) 3880 #define R_PATH1_RXB_INIT 0x472C 3881 #define B_PATH1_RXB_INIT_IDX_MSK GENMASK(9, 5) 3882 #define R_PATH1_G_LNA6_OP1DB_V1 0x476C 3883 #define B_PATH1_G_LNA6_OP1DB_V1 GENMASK(31, 24) 3884 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC 0x4774 3885 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1 0x4CE8 3886 #define R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2 0x47A8 3887 #define B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) 3888 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC 0x4778 3889 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1 0x4CEC 3890 #define R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2 0x47AC 3891 #define B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK BIT(5) 3892 #define R_PATH1_G_TIA0_LNA6_OP1DB_V1 0x4778 3893 #define B_PATH1_G_TIA0_LNA6_OP1DB_V1 GENMASK(7, 0) 3894 #define R_PATH1_G_TIA1_LNA6_OP1DB_V1 0x4778 3895 #define B_PATH1_G_TIA1_LNA6_OP1DB_V1 GENMASK(15, 8) 3896 #define R_PATH1_BAND_SEL_V1 0x4AA4 3897 #define B_PATH1_BAND_SEL_MSK_V1 BIT(17) 3898 #define R_PATH1_BT_SHARE_V1 0x4AA4 3899 #define B_PATH1_BT_SHARE_V1 BIT(19) 3900 #define R_PATH1_BTG_PATH_V1 0x4AA4 3901 #define B_PATH1_BTG_PATH_V1 BIT(22) 3902 #define R_P1_NBIIDX 0x4770 3903 #define B_P1_NBIIDX_VAL GENMASK(11, 0) 3904 #define B_P1_NBIIDX_NOTCH_EN BIT(12) 3905 #define R_SEG0R_PD 0x481C 3906 #define R_SEG0R_PD_V1 0x4860 3907 #define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1 BIT(30) 3908 #define B_SEG0R_PD_SPATIAL_REUSE_EN_MSK BIT(29) 3909 #define B_SEG0R_PD_LOWER_BOUND_MSK GENMASK(10, 6) 3910 #define R_2P4G_BAND 0x4970 3911 #define B_2P4G_BAND_SEL BIT(1) 3912 #define R_FC0_BW 0x4974 3913 #define B_FC0_BW_INV GENMASK(6, 0) 3914 #define B_FC0_BW_SET GENMASK(31, 30) 3915 #define B_ANT_RX_BT_SEG0 GENMASK(25, 22) 3916 #define B_ANT_RX_1RCCA_SEG1 GENMASK(21, 18) 3917 #define B_ANT_RX_1RCCA_SEG0 GENMASK(17, 14) 3918 #define R_CHBW_MOD 0x4978 3919 #define B_BT_SHARE BIT(14) 3920 #define B_CHBW_MOD_SBW GENMASK(13, 12) 3921 #define B_CHBW_MOD_PRICH GENMASK(11, 8) 3922 #define B_ANT_RX_SEG0 GENMASK(3, 0) 3923 #define R_PD_BOOST_EN 0x49E8 3924 #define B_PD_BOOST_EN BIT(7) 3925 #define R_P1_BACKOFF_IBADC_V1 0x49F0 3926 #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26) 3927 #define R_BK_FC0_INV_V1 0x4A1C 3928 #define B_BK_FC0_INV_MSK_V1 GENMASK(18, 0) 3929 #define R_CCK_FC0_INV_V1 0x4A20 3930 #define B_CCK_FC0_INV_MSK_V1 GENMASK(18, 0) 3931 #define R_PATH1_RXB_INIT_V1 0x4A5C 3932 #define B_PATH1_RXB_INIT_IDX_MSK_V1 GENMASK(14, 10) 3933 #define R_P1_AGC_CTL 0x4A9C 3934 #define B_P1_AGC_EN BIT(31) 3935 #define R_PATH1_TIA_INIT_V1 0x4AA8 3936 #define B_PATH1_TIA_INIT_IDX_MSK_V1 BIT(9) 3937 #define R_PATH0_RXBB_V1 0x4AD4 3938 #define B_PATH0_RXBB_MSK_V1 GENMASK(31, 0) 3939 #define R_PATH1_RXBB_V1 0x4AE0 3940 #define B_PATH1_RXBB_MSK_V1 GENMASK(31, 0) 3941 #define R_PATH0_BT_BACKOFF_V1 0x4AE4 3942 #define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0) 3943 #define R_PATH1_BT_BACKOFF_V1 0x4AEC 3944 #define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0) 3945 #define R_PATH0_FRC_FIR_TYPE_V1 0x4C00 3946 #define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0) 3947 #define R_PATH0_NOTCH 0x4C14 3948 #define B_PATH0_NOTCH_EN BIT(12) 3949 #define B_PATH0_NOTCH_VAL GENMASK(11, 0) 3950 #define R_PATH0_NOTCH2 0x4C20 3951 #define B_PATH0_NOTCH2_EN BIT(12) 3952 #define B_PATH0_NOTCH2_VAL GENMASK(11, 0) 3953 #define R_PATH0_5MDET 0x4C4C 3954 #define B_PATH0_5MDET_EN BIT(12) 3955 #define B_PATH0_5MDET_SB2 BIT(8) 3956 #define B_PATH0_5MDET_SB0 BIT(6) 3957 #define B_PATH0_5MDET_TH GENMASK(5, 0) 3958 #define R_PATH1_FRC_FIR_TYPE_V1 0x4CC4 3959 #define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0) 3960 #define R_PATH1_NOTCH 0x4CD8 3961 #define B_PATH1_NOTCH_EN BIT(12) 3962 #define B_PATH1_NOTCH_VAL GENMASK(11, 0) 3963 #define R_PATH1_NOTCH2 0x4CE4 3964 #define B_PATH1_NOTCH2_EN BIT(12) 3965 #define B_PATH1_NOTCH2_VAL GENMASK(11, 0) 3966 #define R_PATH1_5MDET 0x4D10 3967 #define B_PATH1_5MDET_EN BIT(12) 3968 #define B_PATH1_5MDET_SB2 BIT(8) 3969 #define B_PATH1_5MDET_SB0 BIT(6) 3970 #define B_PATH1_5MDET_TH GENMASK(5, 0) 3971 #define R_RPL_BIAS_COMP 0x4DF0 3972 #define B_RPL_BIAS_COMP_MASK GENMASK(7, 0) 3973 #define R_RPL_PATHAB 0x4E0C 3974 #define B_RPL_PATHB_MASK GENMASK(23, 16) 3975 #define B_RPL_PATHA_MASK GENMASK(15, 8) 3976 #define R_RSSI_M_PATHAB 0x4E2C 3977 #define B_RSSI_M_PATHB_MASK GENMASK(15, 8) 3978 #define B_RSSI_M_PATHA_MASK GENMASK(7, 0) 3979 #define R_FC0_V1 0x4E30 3980 #define B_FC0_MSK_V1 GENMASK(12, 0) 3981 #define R_RX_BW40_2XFFT_EN_V1 0x4E30 3982 #define B_RX_BW40_2XFFT_EN_MSK_V1 BIT(26) 3983 #define R_DCFO_COMP_S0_V1 0x4A40 3984 #define B_DCFO_COMP_S0_V1_MSK GENMASK(13, 0) 3985 #define R_BMODE_PDTH_V1 0x4B64 3986 #define B_BMODE_PDTH_LOWER_BOUND_MSK_V1 GENMASK(31, 24) 3987 #define R_BMODE_PDTH_EN_V1 0x4B74 3988 #define B_BMODE_PDTH_LIMIT_EN_MSK_V1 BIT(30) 3989 #define R_CFO_COMP_SEG1_L 0x5384 3990 #define R_CFO_COMP_SEG1_H 0x5388 3991 #define R_CFO_COMP_SEG1_CTRL 0x538C 3992 #define B_CFO_COMP_VALID_BIT BIT(29) 3993 #define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24) 3994 #define B_CFO_COMP_VAL_MSK GENMASK(11, 0) 3995 #define R_UPD_CLK 0x5670 3996 #define B_DAC_VAL BIT(31) 3997 #define B_ACK_VAL GENMASK(30, 29) 3998 #define B_DPD_DIS BIT(14) 3999 #define B_DPD_GDIS BIT(13) 4000 #define B_IQK_RFC_ON BIT(1) 4001 #define R_TXPWRB 0x56CC 4002 #define B_TXPWRB_ON BIT(28) 4003 #define B_TXPWRB_VAL GENMASK(27, 19) 4004 #define R_DPD_OFT_EN 0x5800 4005 #define B_DPD_OFT_EN BIT(28) 4006 #define R_DPD_OFT_ADDR 0x5804 4007 #define B_DPD_OFT_ADDR GENMASK(31, 27) 4008 #define R_TXPWRB_H 0x580c 4009 #define B_TXPWRB_RDY BIT(15) 4010 #define R_P0_TMETER 0x5810 4011 #define B_P0_TMETER GENMASK(15, 10) 4012 #define B_P0_TMETER_DIS BIT(16) 4013 #define B_P0_TMETER_TRK BIT(24) 4014 #define R_P0_TSSI_TRK 0x5818 4015 #define B_P0_TSSI_TRK_EN BIT(30) 4016 #define B_P0_TSSI_OFT_EN BIT(28) 4017 #define B_P0_TSSI_OFT GENMASK(7, 0) 4018 #define R_P0_TSSI_AVG 0x5820 4019 #define B_P0_TSSI_AVG GENMASK(15, 12) 4020 #define R_P0_RFCTM 0x5864 4021 #define B_P0_RFCTM_VAL GENMASK(25, 20) 4022 #define R_P0_RFCTM_RDY BIT(26) 4023 #define R_P0_TRSW 0x5868 4024 #define B_P0_TRSW_B BIT(0) 4025 #define B_P0_TRSW_A BIT(1) 4026 #define B_P0_TRSW_X BIT(2) 4027 #define B_P0_TRSW_SO_A2 GENMASK(7, 5) 4028 #define R_P0_RFM 0x5894 4029 #define B_P0_RFM_DIS_WL BIT(7) 4030 #define B_P0_RFM_TX_OPT BIT(6) 4031 #define B_P0_RFM_BT_EN BIT(5) 4032 #define B_P0_RFM_OUT GENMASK(4, 0) 4033 #define R_P0_TXDPD 0x58D4 4034 #define B_P0_TXDPD GENMASK(31, 28) 4035 #define R_P0_TXPW_RSTB 0x58DC 4036 #define B_P0_TXPW_RSTB_MANON BIT(30) 4037 #define B_P0_TXPW_RSTB_TSSI BIT(31) 4038 #define R_P0_TSSI_MV_AVG 0x58E4 4039 #define B_P0_TSSI_MV_AVG GENMASK(13, 11) 4040 #define R_TXGAIN_SCALE 0x58F0 4041 #define B_TXGAIN_SCALE_EN BIT(19) 4042 #define B_TXGAIN_SCALE_OFT GENMASK(31, 24) 4043 #define R_P0_TSSI_BASE 0x5C00 4044 #define R_S0_DACKI 0x5E00 4045 #define B_S0_DACKI_AR GENMASK(31, 28) 4046 #define B_S0_DACKI_EN BIT(3) 4047 #define R_S0_DACKI2 0x5E30 4048 #define B_S0_DACKI2_K GENMASK(21, 12) 4049 #define R_S0_DACKI7 0x5E44 4050 #define B_S0_DACKI7_K GENMASK(15, 8) 4051 #define R_S0_DACKI8 0x5E48 4052 #define B_S0_DACKI8_K GENMASK(15, 8) 4053 #define R_S0_DACKQ 0x5E50 4054 #define B_S0_DACKQ_AR GENMASK(31, 28) 4055 #define B_S0_DACKQ_EN BIT(3) 4056 #define R_S0_DACKQ2 0x5E80 4057 #define B_S0_DACKQ2_K GENMASK(21, 12) 4058 #define R_S0_DACKQ7 0x5E94 4059 #define B_S0_DACKQ7_K GENMASK(15, 8) 4060 #define R_S0_DACKQ8 0x5E98 4061 #define B_S0_DACKQ8_K GENMASK(15, 8) 4062 #define R_RPL_BIAS_COMP1 0x6DF0 4063 #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0) 4064 #define R_P1_TMETER 0x7810 4065 #define B_P1_TMETER GENMASK(15, 10) 4066 #define B_P1_TMETER_DIS BIT(16) 4067 #define B_P1_TMETER_TRK BIT(24) 4068 #define R_P1_TSSI_TRK 0x7818 4069 #define B_P1_TSSI_TRK_EN BIT(30) 4070 #define B_P1_TSSI_OFT_EN BIT(28) 4071 #define B_P1_TSSI_OFT GENMASK(7, 0) 4072 #define R_P1_TSSI_AVG 0x7820 4073 #define B_P1_TSSI_AVG GENMASK(15, 12) 4074 #define R_P1_RFCTM 0x7864 4075 #define R_P1_RFCTM_RDY BIT(26) 4076 #define B_P1_RFCTM_VAL GENMASK(25, 20) 4077 #define R_P1_TXPW_RSTB 0x78DC 4078 #define B_P1_TXPW_RSTB_MANON BIT(30) 4079 #define B_P1_TXPW_RSTB_TSSI BIT(31) 4080 #define R_P1_TSSI_MV_AVG 0x78E4 4081 #define B_P1_TSSI_MV_AVG GENMASK(13, 11) 4082 #define R_TSSI_THOF 0x7C00 4083 #define R_S1_DACKI 0x7E00 4084 #define B_S1_DACKI_AR GENMASK(31, 28) 4085 #define B_S1_DACKI_EN BIT(3) 4086 #define R_S1_DACKI2 0x7E30 4087 #define B_S1_DACKI2_K GENMASK(21, 12) 4088 #define R_S1_DACKI7 0x7E44 4089 #define B_S1_DACKI_K GENMASK(15, 8) 4090 #define R_S1_DACKI8 0x7E48 4091 #define B_S1_DACKI8_K GENMASK(15, 8) 4092 #define R_S1_DACKQ 0x7E50 4093 #define B_S1_DACKQ_AR GENMASK(31, 28) 4094 #define B_S1_DACKQ_EN BIT(3) 4095 #define R_S1_DACKQ2 0x7E80 4096 #define B_S1_DACKQ2_K GENMASK(21, 12) 4097 #define R_S1_DACKQ7 0x7E94 4098 #define B_S1_DACKQ7_K GENMASK(15, 8) 4099 #define R_S1_DACKQ8 0x7E98 4100 #define B_S1_DACKQ8_K GENMASK(15, 8) 4101 #define R_NCTL_CFG 0x8000 4102 #define B_NCTL_CFG_SPAGE GENMASK(2, 1) 4103 #define R_NCTL_RPT 0x8008 4104 #define B_NCTL_RPT_FLG BIT(26) 4105 #define R_NCTL_N1 0x8010 4106 #define B_NCTL_N1_CIP GENMASK(7, 0) 4107 #define R_NCTL_N2 0x8014 4108 #define R_IQK_COM 0x8018 4109 #define R_IQK_DIF 0x801C 4110 #define B_IQK_DIF_TRX GENMASK(1, 0) 4111 #define R_IQK_DIF1 0x8020 4112 #define B_IQK_DIF1_TXPI GENMASK(19, 0) 4113 #define R_IQK_DIF2 0x8024 4114 #define B_IQK_DIF2_RXPI GENMASK(19, 0) 4115 #define R_IQK_DIF4 0x802C 4116 #define B_IQK_DIF4_RXT GENMASK(27, 16) 4117 #define B_IQK_DIF4_TXT GENMASK(11, 0) 4118 #define IQK_DF4_TXT_8_25MHZ 0x021 4119 #define R_IQK_CFG 0x8034 4120 #define B_IQK_CFG_SET GENMASK(5, 4) 4121 #define R_TPG_SEL 0x8068 4122 #define R_TPG_MOD 0x806C 4123 #define B_TPG_MOD_F GENMASK(2, 1) 4124 #define R_MDPK_SYNC 0x8070 4125 #define B_MDPK_SYNC_SEL BIT(31) 4126 #define B_MDPK_SYNC_MAN GENMASK(31, 28) 4127 #define R_MDPK_RX_DCK 0x8074 4128 #define B_MDPK_RX_DCK_EN BIT(31) 4129 #define R_KIP_MOD 0x8078 4130 #define B_KIP_MOD GENMASK(19, 0) 4131 #define R_NCTL_RW 0x8080 4132 #define R_KIP_SYSCFG 0x8088 4133 #define R_KIP_CLK 0x808C 4134 #define R_DPK_IDL 0x809C 4135 #define B_DPK_IDL BIT(8) 4136 #define R_LDL_NORM 0x80A0 4137 #define B_LDL_NORM_MA BIT(16) 4138 #define B_LDL_NORM_PN GENMASK(12, 8) 4139 #define B_LDL_NORM_OP GENMASK(1, 0) 4140 #define R_DPK_CTL 0x80B0 4141 #define B_DPK_CTL_EN BIT(28) 4142 #define R_DPK_CFG 0x80B8 4143 #define B_DPK_CFG_IDX GENMASK(14, 12) 4144 #define R_DPK_CFG2 0x80BC 4145 #define B_DPK_CFG2_ST BIT(14) 4146 #define R_DPK_CFG3 0x80C0 4147 #define R_KPATH_CFG 0x80D0 4148 #define B_KPATH_CFG_ED GENMASK(21, 20) 4149 #define R_KIP_RPT1 0x80D4 4150 #define B_KIP_RPT1_SEL GENMASK(21, 16) 4151 #define R_SRAM_IQRX 0x80D8 4152 #define R_GAPK 0x80E0 4153 #define B_GAPK_ADR BIT(0) 4154 #define R_SRAM_IQRX2 0x80E8 4155 #define R_DPK_MPA 0x80EC 4156 #define B_DPK_MPA_T0 BIT(10) 4157 #define B_DPK_MPA_T1 BIT(9) 4158 #define B_DPK_MPA_T2 BIT(8) 4159 #define R_DPK_WR 0x80F4 4160 #define B_DPK_WR_ST BIT(29) 4161 #define R_DPK_TRK 0x80f0 4162 #define B_DPK_TRK_DIS BIT(31) 4163 #define R_RPT_COM 0x80FC 4164 #define B_PRT_COM_SYNERR BIT(30) 4165 #define B_PRT_COM_DCI GENMASK(27, 16) 4166 #define B_PRT_COM_CORV GENMASK(15, 8) 4167 #define B_PRT_COM_DCQ GENMASK(11, 0) 4168 #define B_PRT_COM_RXOV BIT(8) 4169 #define B_PRT_COM_GL GENMASK(7, 4) 4170 #define B_PRT_COM_CORI GENMASK(7, 0) 4171 #define B_PRT_COM_RXBB GENMASK(5, 0) 4172 #define B_PRT_COM_DONE BIT(0) 4173 #define R_COEF_SEL 0x8104 4174 #define B_COEF_SEL_IQC BIT(0) 4175 #define B_COEF_SEL_MDPD BIT(8) 4176 #define R_CFIR_SYS 0x8120 4177 #define R_IQK_RES 0x8124 4178 #define B_IQK_RES_TXCFIR GENMASK(11, 8) 4179 #define B_IQK_RES_RXCFIR GENMASK(3, 0) 4180 #define R_TXIQC 0x8138 4181 #define R_RXIQC 0x813c 4182 #define B_RXIQC_BYPASS BIT(0) 4183 #define B_RXIQC_BYPASS2 BIT(2) 4184 #define B_RXIQC_NEWP GENMASK(19, 8) 4185 #define B_RXIQC_NEWX GENMASK(31, 20) 4186 #define R_KIP 0x8140 4187 #define B_KIP_DBCC BIT(0) 4188 #define B_KIP_RFGAIN BIT(8) 4189 #define R_RFGAIN 0x8144 4190 #define B_RFGAIN_PAD GENMASK(4, 0) 4191 #define B_RFGAIN_TXBB GENMASK(12, 8) 4192 #define R_RFGAIN_BND 0x8148 4193 #define B_RFGAIN_BND GENMASK(4, 0) 4194 #define R_CFIR_MAP 0x8150 4195 #define R_CFIR_LUT 0x8154 4196 #define B_CFIR_LUT_SEL BIT(8) 4197 #define B_CFIR_LUT_SET BIT(4) 4198 #define B_CFIR_LUT_G3 BIT(3) 4199 #define B_CFIR_LUT_G2 BIT(2) 4200 #define B_CFIR_LUT_GP_V1 GENMASK(2, 0) 4201 #define B_CFIR_LUT_GP GENMASK(1, 0) 4202 #define R_DPK_GN 0x819C 4203 #define B_DPK_GN_EN GENMASK(17, 16) 4204 #define B_DPK_GN_AG GENMASK(9, 0) 4205 #define R_DPD_V1 0x81a0 4206 #define B_DPD_LBK BIT(7) 4207 #define R_DPD_CH0 0x81AC 4208 #define R_DPD_BND 0x81B4 4209 #define R_DPD_CH0A 0x81BC 4210 #define B_DPD_MEN GENMASK(31, 28) 4211 #define B_DPD_ORDER GENMASK(26, 24) 4212 #define B_DPD_SEL GENMASK(13, 8) 4213 #define R_TXAGC_RFK 0x81C4 4214 #define B_TXAGC_RFK_CH0 GENMASK(5, 0) 4215 #define R_DPD_COM 0x81C8 4216 #define R_KIP_IQP 0x81CC 4217 #define B_KIP_IQP_SW GENMASK(13, 12) 4218 #define B_KIP_IQP_IQSW GENMASK(5, 0) 4219 #define R_KIP_RPT 0x81D4 4220 #define B_KIP_RPT_SEL GENMASK(21, 16) 4221 #define R_W_COEF 0x81D8 4222 #define R_LOAD_COEF 0x81DC 4223 #define B_LOAD_COEF_MDPD BIT(16) 4224 #define B_LOAD_COEF_CFIR GENMASK(1, 0) 4225 #define B_LOAD_COEF_DI BIT(1) 4226 #define B_LOAD_COEF_AUTO BIT(0) 4227 #define R_DPK_GL 0x81F0 4228 #define B_DPK_GL_A0 GENMASK(31, 28) 4229 #define B_DPK_GL_A1 GENMASK(17, 0) 4230 #define R_RPT_PER 0x81FC 4231 #define B_RPT_PER_TSSI GENMASK(28, 16) 4232 #define B_RPT_PER_OF GENMASK(15, 8) 4233 #define B_RPT_PER_TH GENMASK(5, 0) 4234 #define R_RXCFIR_P0C0 0x8D40 4235 #define R_RXCFIR_P0C1 0x8D84 4236 #define R_RXCFIR_P0C2 0x8DC8 4237 #define R_RXCFIR_P0C3 0x8E0C 4238 #define R_TXCFIR_P0C0 0x8F50 4239 #define R_TXCFIR_P0C1 0x8F84 4240 #define R_TXCFIR_P0C2 0x8FB8 4241 #define R_TXCFIR_P0C3 0x8FEC 4242 #define R_RXCFIR_P1C0 0x9140 4243 #define R_RXCFIR_P1C1 0x9184 4244 #define R_RXCFIR_P1C2 0x91C8 4245 #define R_RXCFIR_P1C3 0x920C 4246 #define R_TXCFIR_P1C0 0x9350 4247 #define R_TXCFIR_P1C1 0x9384 4248 #define R_TXCFIR_P1C2 0x93B8 4249 #define R_TXCFIR_P1C3 0x93EC 4250 #define R_IQKINF 0x9FE0 4251 #define B_IQKINF_VER GENMASK(31, 24) 4252 #define B_IQKINF_FAIL_RXGRP GENMASK(23, 16) 4253 #define B_IQKINF_FAIL_TXGRP GENMASK(15, 8) 4254 #define B_IQKINF_FAIL GENMASK(3, 0) 4255 #define B_IQKINF_F_RX BIT(3) 4256 #define B_IQKINF_FTX BIT(2) 4257 #define B_IQKINF_FFIN BIT(1) 4258 #define B_IQKINF_FCOR BIT(0) 4259 #define R_IQKCH 0x9FE4 4260 #define B_IQKCH_CH GENMASK(15, 8) 4261 #define B_IQKCH_BW GENMASK(7, 4) 4262 #define B_IQKCH_BAND GENMASK(3, 0) 4263 #define R_IQKINF2 0x9FE8 4264 #define B_IQKINF2_FCNT GENMASK(23, 16) 4265 #define B_IQKINF2_KCNT GENMASK(15, 8) 4266 #define B_IQKINF2_NCTLV GENMASK(7, 0) 4267 #define R_DCOF0 0xC000 4268 #define B_DCOF0_V GENMASK(4, 1) 4269 #define R_DCOF1 0xC004 4270 #define B_DCOF1_S BIT(0) 4271 #define R_DCOF8 0xC020 4272 #define B_DCOF8_V GENMASK(4, 1) 4273 #define R_DACK_S0P0 0xC040 4274 #define B_DACK_S0P0_OK BIT(31) 4275 #define R_DACK_BIAS00 0xc048 4276 #define B_DACK_BIAS00 GENMASK(11, 2) 4277 #define R_DACK_S0P2 0xC05C 4278 #define B_DACK_S0M0 GENMASK(31, 24) 4279 #define B_DACK_S0P2_OK BIT(2) 4280 #define R_DACK_DADCK00 0xC060 4281 #define B_DACK_DADCK00 GENMASK(31, 24) 4282 #define R_DACK_S0P1 0xC064 4283 #define B_DACK_S0P1_OK BIT(31) 4284 #define R_DACK_BIAS01 0xC06C 4285 #define B_DACK_BIAS01 GENMASK(11, 2) 4286 #define R_DACK_S0P3 0xC080 4287 #define B_DACK_S0M1 GENMASK(31, 24) 4288 #define B_DACK_S0P3_OK BIT(2) 4289 #define R_DACK_DADCK01 0xC084 4290 #define B_DACK_DADCK01 GENMASK(31, 24) 4291 #define R_DRCK 0xC0C4 4292 #define B_DRCK_IDLE BIT(9) 4293 #define B_DRCK_EN BIT(6) 4294 #define B_DRCK_VAL GENMASK(4, 0) 4295 #define R_DRCK_RES 0xC0C8 4296 #define B_DRCK_RES GENMASK(19, 15) 4297 #define B_DRCK_POL BIT(3) 4298 #define R_PATH0_SAMPL_DLY_T_V1 0xC0D4 4299 #define B_PATH0_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26) 4300 #define R_P0_CFCH_BW0 0xC0D4 4301 #define B_P0_CFCH_BW0 GENMASK(27, 26) 4302 #define R_P0_CFCH_BW1 0xC0D8 4303 #define B_P0_CFCH_BW1 GENMASK(8, 5) 4304 #define R_ADDCK0 0xC0F4 4305 #define B_ADDCK0 GENMASK(9, 8) 4306 #define B_ADDCK0_EN BIT(4) 4307 #define B_ADDCK0_RST BIT(2) 4308 #define R_ADDCK0_RL 0xC0F8 4309 #define B_ADDCK0_RLS GENMASK(29, 28) 4310 #define B_ADDCK0_RL1 GENMASK(27, 18) 4311 #define B_ADDCK0_RL0 GENMASK(17, 8) 4312 #define R_ADDCKR0 0xC0FC 4313 #define B_ADDCKR0_A0 GENMASK(19, 10) 4314 #define B_ADDCKR0_A1 GENMASK(9, 0) 4315 #define R_DACK10 0xC100 4316 #define B_DACK10 GENMASK(4, 1) 4317 #define R_DACK1_K 0xc104 4318 #define B_DACK1_EN BIT(0) 4319 #define R_DACK11 0xC120 4320 #define B_DACK11 GENMASK(4, 1) 4321 #define R_DACK_S1P0 0xC140 4322 #define B_DACK_S1P0_OK BIT(31) 4323 #define R_DACK_BIAS10 0xC148 4324 #define B_DACK_BIAS10 GENMASK(11, 2) 4325 #define R_DACK10S 0xC15C 4326 #define B_DACK10S GENMASK(31, 24) 4327 #define R_DACK_S1P2 0xC15C 4328 #define B_DACK_S1P2_OK BIT(2) 4329 #define R_DACK_DADCK10 0xC160 4330 #define B_DACK_DADCK10 GENMASK(31, 24) 4331 #define R_DACK_S1P1 0xC164 4332 #define B_DACK_S1P1_OK BIT(31) 4333 #define R_DACK_BIAS11 0xC16C 4334 #define B_DACK_BIAS11 GENMASK(11, 2) 4335 #define R_DACK11S 0xC180 4336 #define B_DACK11S GENMASK(31, 24) 4337 #define R_DACK_S1P3 0xC180 4338 #define B_DACK_S1P3_OK BIT(2) 4339 #define R_DACK_DADCK11 0xC184 4340 #define B_DACK_DADCK11 GENMASK(31, 24) 4341 #define R_PATH1_SAMPL_DLY_T_V1 0xC1D4 4342 #define B_PATH1_SAMPL_DLY_T_MSK_V1 GENMASK(27, 26) 4343 #define R_PATH0_BW_SEL_V1 0xC0D8 4344 #define B_PATH0_BW_SEL_MSK_V1 GENMASK(8, 5) 4345 #define R_PATH1_BW_SEL_V1 0xC1D8 4346 #define B_PATH1_BW_SEL_MSK_V1 GENMASK(8, 5) 4347 #define R_ADDCK1 0xC1F4 4348 #define B_ADDCK1 GENMASK(9, 8) 4349 #define B_ADDCK1_EN BIT(4) 4350 #define B_ADDCK1_RST BIT(2) 4351 #define R_ADDCK1_RL 0xC1F8 4352 #define B_ADDCK1_RLS GENMASK(29, 28) 4353 #define B_ADDCK1_RL1 GENMASK(27, 18) 4354 #define B_ADDCK1_RL0 GENMASK(17, 8) 4355 #define R_ADDCKR1 0xC1fC 4356 #define B_ADDCKR1_A0 GENMASK(19, 10) 4357 #define B_ADDCKR1_A1 GENMASK(9, 0) 4358 4359 /* WiFi CPU local domain */ 4360 #define R_AX_WDT_CTRL 0x0040 4361 #define B_AX_WDT_EN BIT(31) 4362 #define B_AX_WDT_OPT_RESET_PLATFORM_EN BIT(29) 4363 #define B_AX_IO_HANG_IMR BIT(27) 4364 #define B_AX_IO_HANG_CMAC_RDATA_EN BIT(26) 4365 #define B_AX_IO_HANG_DMAC_EN BIT(25) 4366 #define B_AX_WDT_CLR BIT(16) 4367 #define B_AX_WDT_COUNT_MASK GENMASK(15, 0) 4368 #define WDT_CTRL_ALL_DIS 0 4369 4370 #define R_AX_WDT_STATUS 0x0044 4371 #define B_AX_FS_WDT_INT BIT(8) 4372 #define B_AX_FS_WDT_INT_MSK BIT(0) 4373 4374 #endif 4375