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Searched refs:RREG32_NO_KIQ (Results 1 – 17 of 17) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c325 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
330 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
339 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_send_ack()
347 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_set_valid()
358 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0); in xgpu_vi_mailbox_trans_msg()
374 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_mailbox_rcv_msg()
379 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_vi_mailbox_rcv_msg()
395 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
405 reg = RREG32_NO_KIQ(mmMAILBOX_CONTROL); in xgpu_vi_poll_ack()
504 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_vi_set_mailbox_ack_irq()
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Dmxgpu_ai.c58 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_peek_msg()
68 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_rcv_msg()
140 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_trans_msg()
182 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_send_access_requests()
243 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq()
303 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_rcv_irq()
Dmxgpu_nv.c57 return RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_nv_mailbox_peek_msg()
66 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); in xgpu_nv_mailbox_rcv_msg()
193 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW1); in xgpu_nv_send_access_requests()
204 RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW2); in xgpu_nv_send_access_requests()
264 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_nv_set_mailbox_ack_irq()
330 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL); in xgpu_nv_set_mailbox_rcv_irq()
Dvega10_ih.c356 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega10_ih_get_wptr()
372 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in vega10_ih_get_wptr()
397 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in vega10_ih_irq_rearm()
Dvega20_ih.c407 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega20_ih_get_wptr()
423 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in vega20_ih_get_wptr()
449 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in vega20_ih_irq_rearm()
Dih_v6_0.c402 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_0_get_wptr()
417 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in ih_v6_0_get_wptr()
441 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in ih_v6_0_irq_rearm()
Dnavi10_ih.c427 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in navi10_ih_get_wptr()
442 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in navi10_ih_get_wptr()
467 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in navi10_ih_irq_rearm()
Dvi.c309 (void)RREG32_NO_KIQ(mmPCIE_INDEX); in vi_pcie_rreg()
310 r = RREG32_NO_KIQ(mmPCIE_DATA); in vi_pcie_rreg()
321 (void)RREG32_NO_KIQ(mmPCIE_INDEX); in vi_pcie_wreg()
323 (void)RREG32_NO_KIQ(mmPCIE_DATA); in vi_pcie_wreg()
334 r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); in vi_smc_rreg()
Dgmc_v11_0.c243 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); in gmc_v11_0_flush_vm_hub()
249 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); in gmc_v11_0_flush_vm_hub()
Damdgpu_virt.c50 return RREG32_NO_KIQ(0xc040) == 0xffffffff; in amdgpu_virt_mmio_blocked()
1044 return RREG32_NO_KIQ(offset); in amdgpu_sriov_rreg()
Damdgpu.h1138 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) macro
Dgmc_v9_0.c842 RREG32_NO_KIQ(hub->vm_inv_eng0_req + in gmc_v9_0_flush_gpu_tlb()
Damdgpu_device.c330 *data++ = RREG32_NO_KIQ(mmMM_DATA); in amdgpu_device_mm_access()
Dgfx_v11_0.c4996 data = RREG32_NO_KIQ(reg); in gfx_v11_0_update_spm_vmid()
Dgfx_v9_0.c4904 data = RREG32_NO_KIQ(reg); in gfx_v9_0_update_spm_vmid()
Dgfx_v8_0.c5614 data = RREG32_NO_KIQ(mmRLC_SPM_VMID); in gfx_v8_0_update_spm_vmid()
Dgfx_v10_0.c8100 data = RREG32_NO_KIQ(reg); in gfx_v10_0_update_spm_vmid()