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Searched refs:RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK (Results 1 – 18 of 18) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c4843 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; in gfx_v9_0_update_coarse_grain_clock_gating()
4846 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; in gfx_v9_0_update_coarse_grain_clock_gating()
4862 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v9_0_update_coarse_grain_clock_gating()
5050 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) in gfx_v9_0_get_clockgating_state()
Dgfx_v6_0.c2561 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v6_0_enable_cgcg()
2570 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v6_0_enable_cgcg()
Dgfx_v11_0.c4866 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; in gfx_v11_0_update_coarse_grain_clock_gating()
4928 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; in gfx_v11_0_update_coarse_grain_clock_gating()
5133 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) in gfx_v11_0_get_clockgating_state()
Dgfx_v7_0.c3577 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v7_0_enable_cgcg()
3589 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v7_0_enable_cgcg()
Dgfx_v8_0.c5477 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) in gfx_v8_0_get_clockgating_state()
5776 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; in gfx_v8_0_update_coarse_grain_clock_gating()
5828 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | in gfx_v8_0_update_coarse_grain_clock_gating()
Dgfx_v10_0.c7883 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; in gfx_v10_0_update_coarse_grain_clock_gating()
7903 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; in gfx_v10_0_update_coarse_grain_clock_gating()
8294 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) in gfx_v10_0_get_clockgating_state()
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h7060 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L macro
Dgfx_7_2_sh_mask.h7887 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 macro
Dgfx_8_0_sh_mask.h8805 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 macro
Dgfx_8_1_sh_mask.h9355 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h23123 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK macro
Dgc_9_1_sh_mask.h24414 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK macro
Dgc_9_2_1_sh_mask.h24475 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK macro
Dgc_9_4_2_sh_mask.h21924 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK macro
Dgc_11_0_0_sh_mask.h34438 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK macro
Dgc_10_1_0_sh_mask.h33461 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK macro
Dgc_11_0_3_sh_mask.h37685 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK macro
Dgc_10_3_0_sh_mask.h32535 #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK macro