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Searched refs:REG_UPDATE (Results 1 – 25 of 99) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_mmhubbub.c83 REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, params->swlock); in mmhubbub2_config_mcif_buf()
86 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub2_config_mcif_buf()
87 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub2_config_mcif_buf()
89 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, 0); in mmhubbub2_config_mcif_buf()
92 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub2_config_mcif_buf()
93 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub2_config_mcif_buf()
95 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, 0); in mmhubbub2_config_mcif_buf()
98 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub2_config_mcif_buf()
99 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub2_config_mcif_buf()
101 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, 0); in mmhubbub2_config_mcif_buf()
[all …]
Ddcn20_dwb.c83 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 1); in dwb2_config_dwb_cnv()
84 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_X, params->cnv_params.crop_x); in dwb2_config_dwb_cnv()
85 REG_UPDATE(CNV_WINDOW_START, CNV_WINDOW_START_Y, params->cnv_params.crop_y); in dwb2_config_dwb_cnv()
86 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_WIDTH, params->cnv_params.crop_width); in dwb2_config_dwb_cnv()
87 REG_UPDATE(CNV_WINDOW_SIZE, CNV_WINDOW_HEIGHT, params->cnv_params.crop_height); in dwb2_config_dwb_cnv()
89 REG_UPDATE(CNV_MODE, CNV_WINDOW_CROP_EN, 0); in dwb2_config_dwb_cnv()
93 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_RATE, params->capture_rate); in dwb2_config_dwb_cnv()
96 REG_UPDATE(CNV_MODE, CNV_OUT_BPC, params->cnv_params.cnv_out_bpc); in dwb2_config_dwb_cnv()
118 REG_UPDATE(WB_ENABLE, WB_ENABLE, 1); in dwb2_enable()
127 REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE); in dwb2_enable()
[all …]
Ddcn20_stream_encoder.c84 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc2_update_hdmi_info_packet()
91 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc2_update_hdmi_info_packet()
98 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc2_update_hdmi_info_packet()
105 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc2_update_hdmi_info_packet()
112 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc2_update_hdmi_info_packet()
119 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc2_update_hdmi_info_packet()
126 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc2_update_hdmi_info_packet()
133 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc2_update_hdmi_info_packet()
152 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); in enc2_stream_encoder_update_hdmi_info_packets()
228 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 1); in enc2_update_gsp7_128_info_packet()
[all …]
Ddcn20_dpp.c81 REG_UPDATE(CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, power_on == true ? 1:0); in dpp2_power_on_obuf()
83 REG_UPDATE(OBUF_MEM_PWR_CTRL, in dpp2_power_on_obuf()
86 REG_UPDATE(DSCL_MEM_PWR_CTRL, in dpp2_power_on_obuf()
122 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); in dpp2_cnv_setup()
123 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); in dpp2_cnv_setup()
124 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); in dpp2_cnv_setup()
125 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); in dpp2_cnv_setup()
219 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); in dpp2_cnv_setup()
220 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); in dpp2_cnv_setup()
221 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp2_cnv_setup()
[all …]
Ddcn20_optc.c55 REG_UPDATE(OPTC_DATA_SOURCE_SELECT, in optc2_enable_crtc()
59 REG_UPDATE(CONTROL, in optc2_enable_crtc()
107 REG_UPDATE(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
110 REG_UPDATE(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
113 REG_UPDATE(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, gsl_ready_signal); in optc2_set_gsl_source_select()
132 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, in optc2_set_dsc_config()
138 REG_UPDATE(OPTC_WIDTH_CONTROL, in optc2_set_dsc_config()
174 REG_UPDATE(OTG_H_TIMING_CNTL, in optc2_set_odm_bypass()
215 REG_UPDATE(OPTC_WIDTH_CONTROL, in optc2_set_odm_combine()
251 REG_UPDATE(DWB_SOURCE_SELECT, in optc2_set_dwb_source()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_mmhubbub.c97 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1); in mmhubbub32_warmup_mcif()
100 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false); in mmhubbub32_warmup_mcif()
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub32_config_mcif_buf()
111 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub32_config_mcif_buf()
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub32_config_mcif_buf()
115 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub32_config_mcif_buf()
118 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub32_config_mcif_buf()
119 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub32_config_mcif_buf()
122 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); in mmhubbub32_config_mcif_buf()
123 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub32_config_mcif_buf()
[all …]
Ddcn32_dio_stream_encoder.c59 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, odm_combine ? 1 : 0); in enc32_dp_set_odm_combine()
88 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); in enc32_stream_encoder_dvi_set_stream_attribute()
128 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); in enc32_stream_encoder_hdmi_set_stream_attribute()
152 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in enc32_stream_encoder_hdmi_set_stream_attribute()
216 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); in enc32_stream_encoder_hdmi_set_stream_attribute()
221 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in enc32_stream_encoder_hdmi_set_stream_attribute()
228 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, in enc32_stream_encoder_hdmi_set_stream_attribute()
232 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); in enc32_stream_encoder_hdmi_set_stream_attribute()
312 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); in enc32_stream_encoder_dp_unblank()
318 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); in enc32_stream_encoder_dp_unblank()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_vpg.c79 REG_UPDATE(VPG_GENERIC_STATUS, VPG_GENERIC_CONFLICT_CLR, 1); in vpg3_update_generic_info_packet()
82 REG_UPDATE(VPG_GENERIC_PACKET_ACCESS_CTRL, in vpg3_update_generic_info_packet()
113 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
117 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
121 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
125 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
129 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
133 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
137 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
141 REG_UPDATE(VPG_GSP_IMMEDIATE_UPDATE_CTRL, in vpg3_update_generic_info_packet()
[all …]
Ddcn30_mmhubbub.c97 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_SW_INT_ACK, 1); in mmhubbub3_warmup_mcif()
100 REG_UPDATE(MMHUBBUB_WARMUP_CONTROL_STATUS, MMHUBBUB_WARMUP_EN, false); in mmhubbub3_warmup_mcif()
110 REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0])); in mmhubbub3_config_mcif_buf()
111 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
114 REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0])); in mmhubbub3_config_mcif_buf()
115 …REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
118 REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1])); in mmhubbub3_config_mcif_buf()
119 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_addre… in mmhubbub3_config_mcif_buf()
122 REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1])); in mmhubbub3_config_mcif_buf()
123 …REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_add… in mmhubbub3_config_mcif_buf()
[all …]
Ddcn30_dio_stream_encoder.c87 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc3_update_hdmi_info_packet()
94 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1, in enc3_update_hdmi_info_packet()
101 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc3_update_hdmi_info_packet()
108 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2, in enc3_update_hdmi_info_packet()
115 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc3_update_hdmi_info_packet()
122 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3, in enc3_update_hdmi_info_packet()
129 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc3_update_hdmi_info_packet()
136 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4, in enc3_update_hdmi_info_packet()
143 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7, in enc3_update_hdmi_info_packet()
150 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7, in enc3_update_hdmi_info_packet()
[all …]
Ddcn30_dwb.c76 REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 1); in dwb3_config_fc()
77 REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_X, params->cnv_params.crop_x); in dwb3_config_fc()
78 REG_UPDATE(FC_WINDOW_START, FC_WINDOW_START_Y, params->cnv_params.crop_y); in dwb3_config_fc()
79 REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_WIDTH, params->cnv_params.crop_width); in dwb3_config_fc()
80 REG_UPDATE(FC_WINDOW_SIZE, FC_WINDOW_HEIGHT, params->cnv_params.crop_height); in dwb3_config_fc()
82 REG_UPDATE(FC_MODE_CTRL, FC_WINDOW_CROP_EN, 0); in dwb3_config_fc()
86 REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_RATE, params->capture_rate); in dwb3_config_fc()
97 REG_UPDATE(DWB_ENABLE_CLK_CTRL, DWB_ENABLE, 1); in dwb3_enable()
111 REG_UPDATE(FC_MODE_CTRL, FC_FRAME_CAPTURE_EN, DWB_FRAME_CAPTURE_ENABLE); in dwb3_enable()
114 REG_UPDATE(FC_FLOW_CTRL, FC_FIRST_PIXEL_DELAY_COUNT, 96); in dwb3_enable()
[all …]
Ddcn30_afmt.c56 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in afmt3_setup_hdmi_audio()
71 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); in afmt3_setup_hdmi_audio()
141 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); in afmt3_se_audio_setup()
145 REG_UPDATE(AFMT_MEM_PWR, AFMT_MEM_PWR_FORCE, 0); in afmt3_se_audio_setup()
158 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); in afmt3_audio_mute_control()
167 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in afmt3_audio_info_immediate_update()
179 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); in afmt3_setup_dp_audio()
188 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); in afmt3_setup_dp_audio()
191 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); in afmt3_setup_dp_audio()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.c74 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); in dce110_update_generic_info_packet()
94 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); in dce110_update_generic_info_packet()
99 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in dce110_update_generic_info_packet()
140 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
144 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
148 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
152 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
156 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
160 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
164 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in dce110_update_generic_info_packet()
[all …]
Ddce_dmcu.c113 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); in dce_get_dmcu_psr_state()
126 REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); in dce_get_dmcu_psr_state()
145 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
148 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
152 REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); in dce_dmcu_set_psr_enable()
195 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
199 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
203 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
207 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
224 REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, in dce_dmcu_setup_psr()
[all …]
Ddce_ipp.c49 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); in dce_ipp_cursor_set_position()
53 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); in dce_ipp_cursor_set_position()
64 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); in dce_ipp_cursor_set_position()
75 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true); in dce_ipp_cursor_set_attributes()
134 REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false); in dce_ipp_cursor_set_attributes()
144 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
160 REG_UPDATE(PRESCALE_GRPH_CONTROL, in dce_ipp_program_prescale()
164 REG_UPDATE(INPUT_GAMMA_CONTROL, in dce_ipp_program_prescale()
184 REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0); in dce_ipp_program_input_lut()
213 REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); in dce_ipp_program_input_lut()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_hwseq.c57 REG_UPDATE(DOMAIN1_PG_CONFIG, in dcn302_dpp_pg_control()
65 REG_UPDATE(DOMAIN3_PG_CONFIG, in dcn302_dpp_pg_control()
73 REG_UPDATE(DOMAIN5_PG_CONFIG, in dcn302_dpp_pg_control()
81 REG_UPDATE(DOMAIN7_PG_CONFIG, in dcn302_dpp_pg_control()
89 REG_UPDATE(DOMAIN9_PG_CONFIG, in dcn302_dpp_pg_control()
114 REG_UPDATE(DOMAIN0_PG_CONFIG, in dcn302_hubp_pg_control()
122 REG_UPDATE(DOMAIN2_PG_CONFIG, in dcn302_hubp_pg_control()
130 REG_UPDATE(DOMAIN4_PG_CONFIG, in dcn302_hubp_pg_control()
138 REG_UPDATE(DOMAIN6_PG_CONFIG, in dcn302_hubp_pg_control()
146 REG_UPDATE(DOMAIN8_PG_CONFIG, in dcn302_hubp_pg_control()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hpo_dp_stream_encoder.c66 REG_UPDATE(DP_STREAM_ENC_CLOCK_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
70 REG_UPDATE(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
78 REG_UPDATE(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
86 REG_UPDATE(DP_SYM32_ENC_CONTROL, in dcn31_hpo_dp_stream_enc_enable_stream()
97 REG_UPDATE(DP_STREAM_ENC_INPUT_MUX_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
101 REG_UPDATE(DP_SYM32_ENC_VID_STREAM_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
105 REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
110 REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
115 REG_UPDATE(DP_SYM32_ENC_VID_FIFO_CONTROL, in dcn31_hpo_dp_stream_enc_dp_unblank()
119 REG_UPDATE(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, in dcn31_hpo_dp_stream_enc_dp_unblank()
[all …]
Ddcn31_dccg.c66 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg31_update_dpp_dto()
71 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg31_update_dpp_dto()
77 REG_UPDATE(DPPCLK_DTO_CTRL, in dccg31_update_dpp_dto()
104 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
108 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
112 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
116 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_enable_dpstreamclk()
140 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
144 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
148 REG_UPDATE(DPSTREAMCLK_CNTL, in dccg31_disable_dpstreamclk()
[all …]
Ddcn31_hpo_dp_link_encoder.c62 REG_UPDATE(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, 1); in dcn31_hpo_dp_link_enc_enable()
66 REG_UPDATE(DP_DPHY_SYM32_CONTROL, DPHY_RESET, 1); in dcn31_hpo_dp_link_enc_enable()
67 REG_UPDATE(DP_DPHY_SYM32_CONTROL, DPHY_RESET, 0); in dcn31_hpo_dp_link_enc_enable()
83 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_disable()
87 REG_UPDATE(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC_CLOCK_EN, 0); in dcn31_hpo_dp_link_enc_disable()
99 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
103 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
107 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
116 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
125 REG_UPDATE(DP_DPHY_SYM32_CONTROL, in dcn31_hpo_dp_link_enc_set_link_test_pattern()
[all …]
Ddcn31_dio_link_encoder.c145 REG_UPDATE(DIO_LINKA_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
148 REG_UPDATE(DIO_LINKA_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
150 REG_UPDATE(DIO_LINKA_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
155 REG_UPDATE(DIO_LINKB_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
158 REG_UPDATE(DIO_LINKB_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
160 REG_UPDATE(DIO_LINKB_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
165 REG_UPDATE(DIO_LINKC_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
168 REG_UPDATE(DIO_LINKC_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
170 REG_UPDATE(DIO_LINKC_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
175 REG_UPDATE(DIO_LINKD_CNTL, in dcn31_link_encoder_set_dio_phy_mux()
[all …]
Ddcn31_apg.c53 REG_UPDATE(APG_CONTROL, APG_RESET, 1); in apg31_enable()
57 REG_UPDATE(APG_CONTROL, APG_RESET, 0); in apg31_enable()
63 REG_UPDATE(APG_CONTROL2, APG_ENABLE, 1); in apg31_enable()
72 REG_UPDATE(APG_CONTROL2, APG_ENABLE, 0); in apg31_disable()
128 REG_UPDATE(APG_CONTROL2, APG_DP_AUDIO_STREAM_ID, 0); in apg31_se_audio_setup()
132 REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 0xFF); in apg31_se_audio_setup()
136 REG_UPDATE(APG_MEM_PWR, APG_MEM_PWR_FORCE, 0); in apg31_se_audio_setup()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c68 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); in enc1_update_generic_info_packet()
87 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); in enc1_update_generic_info_packet()
90 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, in enc1_update_generic_info_packet()
122 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
126 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
130 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
134 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
138 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, in enc1_update_generic_info_packet()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_gpio.c54 REG_UPDATE(MASK_reg, MASK, gpio->store.mask); in restore_registers()
55 REG_UPDATE(A_reg, A, gpio->store.a); in restore_registers()
56 REG_UPDATE(EN_reg, EN, gpio->store.en); in restore_registers()
107 REG_UPDATE(A_reg, A, value); in dal_hw_gpio_set_value()
114 REG_UPDATE(EN_reg, EN, ~value); in dal_hw_gpio_set_value()
151 REG_UPDATE(EN_reg, EN, 0); in dal_hw_gpio_config_mode()
152 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
157 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
158 REG_UPDATE(MASK_reg, MASK, 1); in dal_hw_gpio_config_mode()
163 REG_UPDATE(A_reg, A, 0); in dal_hw_gpio_config_mode()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn314/
Ddcn314_dio_stream_encoder.c58 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_RESET, reset_val); in enc314_reset_fifo()
71 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7); in enc314_enable_fifo()
76 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 1); in enc314_enable_fifo()
83 REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0); in enc314_disable_fifo()
92 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_PER_CYCLE_PROCESSING_MODE, odm_combine); in enc314_dp_set_odm_combine()
121 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); in enc314_stream_encoder_dvi_set_stream_attribute()
161 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); in enc314_stream_encoder_hdmi_set_stream_attribute()
185 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); in enc314_stream_encoder_hdmi_set_stream_attribute()
248 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); in enc314_stream_encoder_hdmi_set_stream_attribute()
252 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); in enc314_stream_encoder_hdmi_set_stream_attribute()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_hw_sequencer.c208 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
211 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
214 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
219 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
222 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
225 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()
230 REG_UPDATE(DCHUB_AGP_BASE, in dce120_update_dchub()
233 REG_UPDATE(DCHUB_AGP_BOT, in dce120_update_dchub()
236 REG_UPDATE(DCHUB_AGP_TOP, in dce120_update_dchub()

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