| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_ipp.c | 102 REG_SET_3(CUR_COLOR1, 0, in dce_ipp_cursor_set_attributes()
107 REG_SET_3(CUR_COLOR2, 0, in dce_ipp_cursor_set_attributes()
187 REG_SET_3(DC_LUT_CONTROL, 0, in dce_ipp_program_input_lut()
226 REG_SET_3(DEGAMMA_CONTROL, 0, in dce_ipp_set_degamma()
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| D | dce_abm.c | 148 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, in dce_abm_init()
153 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, in dce_abm_init()
171 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, in dce_abm_init()
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| D | dmub_abm.c | 89 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, in dmub_abm_init()
94 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, in dmub_abm_init()
112 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, in dmub_abm_init()
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| D | dce_i2c_hw.c | 110 REG_SET_3(DC_I2C_DATA, 0, in process_channel_reply()
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| D | dce_link_encoder.c | 173 REG_SET_3(DP_DPHY_SYM0, 0, in program_pattern_symbols()
181 REG_SET_3(DP_DPHY_SYM1, 0, in program_pattern_symbols()
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| D | dce_transform.c | 237 REG_SET_3(SCL_COEF_RAM_SELECT, 0, in program_multi_taps_filter()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_optc.c | 92 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, in optc3_lock_doublebuffer_enable()
139 REG_SET_3(OTG_BLANK_DATA_COLOR, 0, in optc3_program_blank_color()
144 REG_SET_3(OTG_BLANK_DATA_COLOR_EXT, 0, in optc3_program_blank_color()
248 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc3_set_odm_combine()
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| D | dcn30_mmhubbub.c | 89 REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true, in mmhubbub3_warmup_mcif()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_opp.c | 223 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
234 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
245 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
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| D | dcn20_optc.c | 167 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc2_set_odm_bypass()
210 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc2_set_odm_combine()
433 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, in optc2_lock_doublebuffer_enable()
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| D | dcn20_dsc.c | 579 REG_SET_3(DSCC_CONFIG0, 0, in dsc_write_to_registers()
603 REG_SET_3(DSCC_PPS_CONFIG0, 0, in dsc_write_to_registers()
637 REG_SET_3(DSCC_PPS_CONFIG6, 0, in dsc_write_to_registers()
654 REG_SET_3(DSCC_PPS_CONFIG10, 0, in dsc_write_to_registers()
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| D | dcn20_hubp.c | 151 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp2_program_deadline()
156 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp2_program_deadline()
161 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp2_program_deadline()
682 REG_SET_3(DMDATA_QOS_CNTL, 0, in hubp2_dmdata_set_attributes()
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| D | dcn20_dwb_scl.c | 701 REG_SET_3(WBSCL_COEF_RAM_SELECT, 0, in wbscl_set_scaler_filter()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_reg.h | 70 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ macro
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_mmhubbub.c | 89 REG_SET_3(MMHUBBUB_WARMUP_CONTROL_STATUS, 0, MMHUBBUB_WARMUP_EN, true, in mmhubbub32_warmup_mcif()
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| D | dcn32_optc.c | 80 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc32_set_odm_combine()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_optc.c | 85 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc314_set_odm_combine()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_dpp.c | 304 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
310 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
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| D | dcn10_dpp_dscl.c | 255 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0, in dpp1_dscl_set_scaler_filter()
653 REG_SET_3(DSCL_AUTOCAL, 0, in dpp1_dscl_set_scaler_manual_scale()
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| D | dcn10_optc.c | 559 REG_SET_3(OTG_BLACK_COLOR, 0, in optc1_program_blank_color()
734 REG_SET_3(OTG_TRIGA_CNTL, 0, in optc1_enable_reset_trigger()
743 REG_SET_3(OTG_TRIGA_CNTL, 0, in optc1_enable_reset_trigger()
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| D | dcn10_hubp.c | 658 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp1_program_deadline()
663 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp1_program_deadline()
668 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp1_program_deadline()
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| D | dcn10_link_encoder.c | 144 REG_SET_3(DP_DPHY_SYM0, 0, in program_pattern_symbols()
152 REG_SET_3(DP_DPHY_SYM1, 0, in program_pattern_symbols()
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| D | dcn10_dpp_cm.c | 714 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_full_bypass()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_optc.c | 74 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc31_set_odm_combine()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/ |
| D | reg_helper.h | 72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ macro
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