Searched refs:REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL (Results 1 – 2 of 2) sorted by relevance
1080 #define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL 0x000000ac macro
443 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL, 0x37); in hdmi_8996_pll_set_clk_rate()