Searched refs:REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM (Results 1 – 2 of 2) sorted by relevance
1092 #define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM 0x000000c4 macro
498 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM, 0x15); in hdmi_8996_pll_set_clk_rate()