Searched refs:REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 (Results 1 – 2 of 2) sorted by relevance
1110 #define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x000000e4 macro
476 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0, in hdmi_8996_pll_set_clk_rate()