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Searched refs:REG_GET_FIELD (Results 1 – 25 of 71) sorted by relevance

123

/linux-6.1.9/drivers/gpu/drm/amd/amdkfd/
Dkfd_int_process_v11.c154 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE), in print_sq_intr_info_auto()
155 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, WLT), in print_sq_intr_info_auto()
156 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE_BUF_FULL), in print_sq_intr_info_auto()
157 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, REG_TIMESTAMP), in print_sq_intr_info_auto()
158 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, CMD_TIMESTAMP), in print_sq_intr_info_auto()
159 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, HOST_CMD_OVERFLOW), in print_sq_intr_info_auto()
160 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, HOST_REG_OVERFLOW), in print_sq_intr_info_auto()
161 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, IMMED_OVERFLOW), in print_sq_intr_info_auto()
162 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE_UTC_ERROR)); in print_sq_intr_info_auto()
169 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, DATA), in print_sq_intr_info_inst()
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Dkfd_int_process_v9.c279 encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING); in event_interrupt_wq_v9()
284 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, SE_ID), in event_interrupt_wq_v9()
285 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE), in event_interrupt_wq_v9()
286 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, WLT), in event_interrupt_wq_v9()
287 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, THREAD_TRACE_BUF_FULL), in event_interrupt_wq_v9()
288 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, REG_TIMESTAMP), in event_interrupt_wq_v9()
289 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, CMD_TIMESTAMP), in event_interrupt_wq_v9()
290 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_CMD_OVERFLOW), in event_interrupt_wq_v9()
291 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, HOST_REG_OVERFLOW), in event_interrupt_wq_v9()
292 REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID, IMMED_OVERFLOW), in event_interrupt_wq_v9()
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/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dumc_v8_7.c64 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_7_ecc_info_query_correctable_error_count()
65 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v8_7_ecc_info_query_correctable_error_count()
81 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
82 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
83 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
84 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
85 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
86 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
149 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_7_ecc_info_query_error_address()
150 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) { in umc_v8_7_ecc_info_query_error_address()
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Damdgpu_mca.c36 if (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in amdgpu_mca_query_correctable_error_count()
37 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in amdgpu_mca_query_correctable_error_count()
47 if ((REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in amdgpu_mca_query_uncorrectable_error_count()
48 (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
49 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
50 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
51 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in amdgpu_mca_query_uncorrectable_error_count()
52 REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in amdgpu_mca_query_uncorrectable_error_count()
Dumc_v6_7.c73 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1) in umc_v6_7_query_error_status_helper()
117 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_7_ecc_info_query_correctable_error_count()
118 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) { in umc_v6_7_ecc_info_query_correctable_error_count()
129 err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); in umc_v6_7_ecc_info_query_correctable_error_count()
158 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
159 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
160 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
161 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
162 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
163 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) { in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
[all …]
Dumc_v8_10.c115 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_10_query_correctable_error_count()
116 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v8_10_query_correctable_error_count()
131 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v8_10_query_uncorrectable_error_count()
132 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v8_10_query_uncorrectable_error_count()
133 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v8_10_query_uncorrectable_error_count()
134 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v8_10_query_uncorrectable_error_count()
135 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 || in umc_v8_10_query_uncorrectable_error_count()
136 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) in umc_v8_10_query_uncorrectable_error_count()
236 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v8_10_query_error_address()
237 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 && in umc_v8_10_query_error_address()
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Dumc_v6_1.c82 return REG_GET_FIELD(rsmu_umc_val, in umc_v6_1_get_umc_index_mode_state()
204 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_1_query_correctable_error_count()
214 (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_EccErrCnt, EccErrCnt) - in umc_v6_1_query_correctable_error_count()
220 if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 && in umc_v6_1_query_correctable_error_count()
221 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && in umc_v6_1_query_correctable_error_count()
222 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) in umc_v6_1_query_correctable_error_count()
245 if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) && in umc_v6_1_querry_uncorrectable_error_count()
246 (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
247 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
248 REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 || in umc_v6_1_querry_uncorrectable_error_count()
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Dgfxhub_v1_1.c54 seg_size = REG_GET_FIELD( in gfxhub_v1_1_get_xgmi_info()
58 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE, PF_MAX_REGION); in gfxhub_v1_1_get_xgmi_info()
61 seg_size = REG_GET_FIELD( in gfxhub_v1_1_get_xgmi_info()
65 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); in gfxhub_v1_1_get_xgmi_info()
96 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE, in gfxhub_v1_1_get_xgmi_info()
100 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, in gfxhub_v1_1_get_xgmi_info()
Dsmu_v11_0_i2c.c90 if (REG_GET_FIELD(en_stat, CKSVII2C_IC_ENABLE_STATUS, IC_EN)) in smu_v11_0_i2c_enable()
189 } while (REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFE) == 0); in smu_v11_0_i2c_poll_tx_status()
197 if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { in smu_v11_0_i2c_poll_tx_status()
202 if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_tx_status()
208 } else if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_tx_status()
233 if (REG_GET_FIELD(reg_c_tx_abrt_source, in smu_v11_0_i2c_poll_rx_status()
251 } while (REG_GET_FIELD(reg_ic_status, CKSVII2C_IC_STATUS, RFNE) == 0); in smu_v11_0_i2c_poll_rx_status()
299 if (!REG_GET_FIELD(reg, CKSVII2C_IC_STATUS, TFNF)) { in smu_v11_0_i2c_transmit()
423 data[bytes_received] = REG_GET_FIELD(reg, CKSVII2C_IC_DATA_CMD, DAT); in smu_v11_0_i2c_receive()
470 if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) && in smu_v11_0_i2c_activity_done()
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Dsmuio_v13_0.c86 die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID); in smuio_v13_0_get_die_id()
103 socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID); in smuio_v13_0_get_socket_id()
120 data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID); in smuio_v13_0_is_host_gpu_xgmi_supported()
Dgmc_v7_0.c97 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v7_0_mc_stop()
203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v7_0_mc_load_microcode()
226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v7_0_mc_load_microcode()
333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v7_0_mc_init()
339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v7_0_mc_init()
774 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v7_0_vm_decode_fault()
775 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
781 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
786 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v7_0_vm_decode_fault()
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Dgfx_v9_4.c711 sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT); in gfx_v9_4_query_utc_edc_status()
719 ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT); in gfx_v9_4_query_utc_edc_status()
732 sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
741 ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
755 sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT); in gfx_v9_4_query_utc_edc_status()
763 ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT); in gfx_v9_4_query_utc_edc_status()
776 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
785 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
799 sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
808 ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL, in gfx_v9_4_query_utc_edc_status()
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Ddf_v3_6.c228 adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp, in df_v3_6_query_hashes()
231 adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp, in df_v3_6_query_hashes()
234 adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp, in df_v3_6_query_hashes()
650 v0 = REG_GET_FIELD(hw_assert_msklo, in df_v3_6_query_ras_poison_mode()
652 v1 = REG_GET_FIELD(hw_assert_msklo, in df_v3_6_query_ras_poison_mode()
654 v28 = REG_GET_FIELD(hw_assert_mskhi, in df_v3_6_query_ras_poison_mode()
656 v31 = REG_GET_FIELD(hw_assert_mskhi, in df_v3_6_query_ras_poison_mode()
Dgmc_v8_0.c186 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v8_0_mc_stop()
319 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); in gmc_v8_0_tonga_mc_load_microcode()
342 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
348 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), in gmc_v8_0_tonga_mc_load_microcode()
526 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { in gmc_v8_0_mc_init()
532 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { in gmc_v8_0_mc_init()
1014 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v8_0_vm_decode_fault()
1015 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
1021 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
1026 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v8_0_vm_decode_fault()
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Dgfxhub_v2_0.c79 u32 cid = REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
89 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
92 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
95 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
98 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
101 REG_GET_FIELD(status, in gfxhub_v2_0_print_l2_protection_fault_status()
Dgfxhub_v3_0_3.c81 u32 cid = REG_GET_FIELD(status, in gfxhub_v3_0_3_print_l2_protection_fault_status()
91 REG_GET_FIELD(status, in gfxhub_v3_0_3_print_l2_protection_fault_status()
94 REG_GET_FIELD(status, in gfxhub_v3_0_3_print_l2_protection_fault_status()
97 REG_GET_FIELD(status, in gfxhub_v3_0_3_print_l2_protection_fault_status()
100 REG_GET_FIELD(status, in gfxhub_v3_0_3_print_l2_protection_fault_status()
103 REG_GET_FIELD(status, in gfxhub_v3_0_3_print_l2_protection_fault_status()
Dcz_ih.c197 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
350 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_is_idle()
365 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in cz_ih_wait_for_idle()
Diceland_ih.c197 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
344 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_is_idle()
359 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) in iceland_ih_wait_for_idle()
Dgfxhub_v2_1.c82 u32 cid = REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
92 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
95 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
98 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
101 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
104 REG_GET_FIELD(status, in gfxhub_v2_1_print_l2_protection_fault_status()
506 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); in gfxhub_v2_1_get_xgmi_info()
526 REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); in gfxhub_v2_1_get_xgmi_info()
530 adev->gmc.xgmi.node_segment_size = REG_GET_FIELD( in gfxhub_v2_1_get_xgmi_info()
Dgfxhub_v3_0.c78 u32 cid = REG_GET_FIELD(status, in gfxhub_v3_0_print_l2_protection_fault_status()
88 REG_GET_FIELD(status, in gfxhub_v3_0_print_l2_protection_fault_status()
91 REG_GET_FIELD(status, in gfxhub_v3_0_print_l2_protection_fault_status()
94 REG_GET_FIELD(status, in gfxhub_v3_0_print_l2_protection_fault_status()
97 REG_GET_FIELD(status, in gfxhub_v3_0_print_l2_protection_fault_status()
100 REG_GET_FIELD(status, in gfxhub_v3_0_print_l2_protection_fault_status()
Dmmhub_v3_0_2.c102 cid = REG_GET_FIELD(status, in mmhub_v3_0_2_print_l2_protection_fault_status()
104 rw = REG_GET_FIELD(status, in mmhub_v3_0_2_print_l2_protection_fault_status()
115 REG_GET_FIELD(status, in mmhub_v3_0_2_print_l2_protection_fault_status()
118 REG_GET_FIELD(status, in mmhub_v3_0_2_print_l2_protection_fault_status()
121 REG_GET_FIELD(status, in mmhub_v3_0_2_print_l2_protection_fault_status()
124 REG_GET_FIELD(status, in mmhub_v3_0_2_print_l2_protection_fault_status()
Dgmc_v6_0.c71 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { in gmc_v6_0_mc_stop()
614 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in gmc_v6_0_vm_decode_fault()
615 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
620 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
625 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, in gmc_v6_0_vm_decode_fault()
802 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { in gmc_v6_0_get_vbios_fb_size()
806 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * in gmc_v6_0_get_vbios_fb_size()
807 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * in gmc_v6_0_get_vbios_fb_size()
Dmmhub_v3_0_1.c102 cid = REG_GET_FIELD(status, in mmhub_v3_0_1_print_l2_protection_fault_status()
104 rw = REG_GET_FIELD(status, in mmhub_v3_0_1_print_l2_protection_fault_status()
123 REG_GET_FIELD(status, in mmhub_v3_0_1_print_l2_protection_fault_status()
126 REG_GET_FIELD(status, in mmhub_v3_0_1_print_l2_protection_fault_status()
129 REG_GET_FIELD(status, in mmhub_v3_0_1_print_l2_protection_fault_status()
132 REG_GET_FIELD(status, in mmhub_v3_0_1_print_l2_protection_fault_status()
Damdgpu_amdkfd_gfx_v7.c397 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { in kgd_hqd_destroy()
401 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { in kgd_hqd_destroy()
402 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) in kgd_hqd_destroy()
409 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) in kgd_hqd_destroy()
560 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); in read_vmid_from_vmfault_reg()
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega10_thermal.c74 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_get_fan_speed_pwm()
76 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS), in vega10_fan_ctrl_get_fan_speed_pwm()
104 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), in vega10_fan_ctrl_get_fan_speed_rpm()
132 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
135 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), in vega10_fan_ctrl_set_static_mode()
263 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), in vega10_fan_ctrl_set_fan_speed_pwm()

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