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Searched refs:REG_GENMASK (Results 1 – 12 of 12) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_snps_phy_regs.h23 #define SNPS_PHY_MPLLB_CP_INT REG_GENMASK(31, 25)
24 #define SNPS_PHY_MPLLB_CP_INT_GS REG_GENMASK(23, 17)
25 #define SNPS_PHY_MPLLB_CP_PROP REG_GENMASK(15, 9)
26 #define SNPS_PHY_MPLLB_CP_PROP_GS REG_GENMASK(7, 1)
32 #define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
33 #define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
34 #define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
38 #define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
44 #define SNPS_PHY_MPLLB_FRACN_DEN REG_GENMASK(15, 0)
47 #define SNPS_PHY_MPLLB_FRACN_REM REG_GENMASK(31, 16)
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Dintel_dmc_regs.h45 #define DMC_EVT_CTL_TYPE_MASK REG_GENMASK(17, 16)
51 #define DMC_EVT_CTL_EVENT_ID_MASK REG_GENMASK(15, 8)
Dicl_dsi_regs.h33 #define TX_ESC_CLK_DIV_PHY_MASK REG_GENMASK(23, 16)
101 #define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12)
109 #define DSI_T_INIT_MASTER_MASK REG_GENMASK(15, 0)
Dintel_combo_phy_regs.h155 #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
/linux-6.1.9/drivers/gpu/drm/i915/
Dintel_mchbar_regs.h82 #define MLTR_WM2_MASK REG_GENMASK(13, 8)
83 #define MLTR_WM1_MASK REG_GENMASK(5, 0)
126 #define DG1_DRAM_T_RDPRE_MASK REG_GENMASK(16, 11)
127 #define DG1_DRAM_T_RP_MASK REG_GENMASK(6, 0)
129 #define DG1_DRAM_T_RCD_MASK REG_GENMASK(15, 9)
130 #define DG1_DRAM_T_RAS_MASK REG_GENMASK(8, 1)
189 #define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
195 #define RP0_CAP_MASK REG_GENMASK(7, 0)
196 #define RP1_CAP_MASK REG_GENMASK(15, 8)
197 #define RPN_CAP_MASK REG_GENMASK(23, 16)
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Di915_reg.h656 #define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
658 #define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
677 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
680 #define PORT_PLL_N_MASK REG_GENMASK(11, 8)
683 #define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0)
688 #define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16)
690 #define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8)
692 #define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0)
695 #define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0)
698 #define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
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Di915_reg_defs.h34 #define REG_GENMASK(__high, __low) \ macro
/linux-6.1.9/drivers/gpu/drm/i915/gt/uc/abi/
Dguc_actions_slpc_abi.h159 #define SLPC_MAX_UNSLICE_FREQ_MASK REG_GENMASK(7, 0)
160 #define SLPC_MIN_UNSLICE_FREQ_MASK REG_GENMASK(15, 8)
161 #define SLPC_MAX_SLICE_FREQ_MASK REG_GENMASK(23, 16)
162 #define SLPC_MIN_SLICE_FREQ_MASK REG_GENMASK(31, 24)
/linux-6.1.9/drivers/gpu/drm/i915/gt/
Dintel_gt_regs.h263 #define VERT_WM_VAL REG_GENMASK(9, 0)
388 #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
390 #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
483 #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0)
527 #define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24)
528 #define HSW_F1_EU_DIS_MASK REG_GENMASK(17, 16)
883 #define MSG_IDLE_FW_MASK REG_GENMASK(13, 9)
992 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
1002 #define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
1113 #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2)
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Dintel_gpu_commands.h130 #define MI_SEMAPHORE_TOKEN_MASK REG_GENMASK(9, 5)
240 #define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20)
241 #define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13)
253 #define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
254 #define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
Dintel_engine_regs.h130 #define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
131 #define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
147 #define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 7)
148 #define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 0)
206 #define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2)
/linux-6.1.9/drivers/gpu/drm/i915/gvt/
Dhandlers.c767 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2); in force_nonpriv_write()