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Searched refs:REG_FIELD_PREP (Results 1 – 16 of 16) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_snps_phy.c54 val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, in intel_snps_phy_update_psr_power_state()
76 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing); in intel_snps_phy_set_signal_levels()
77 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.pre_cursor); in intel_snps_phy_set_signal_levels()
78 val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.post_cursor); in intel_snps_phy_set_signal_levels()
91 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
93 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
94 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
95 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
96 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
98 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
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Dintel_lvds.c218 …REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps-… in intel_lvds_pps_init_hw()
221 …REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, … in intel_lvds_pps_init_hw()
224 …REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_M… in intel_lvds_pps_init_hw()
Dicl_dsi_regs.h34 #define TX_ESC_CLK_DIV_PHY REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)
102 #define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
Dintel_pps.c1347 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | in pps_init_registers()
1348 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); in pps_init_registers()
1349 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | in pps_init_registers()
1350 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); in pps_init_registers()
1383 …REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_… in pps_init_registers()
1389 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); in pps_init_registers()
Dintel_dmc.c284 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, in disable_event_handler()
286 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, in disable_event_handler()
302 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, in disable_flip_queue_event()
304 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, in disable_flip_queue_event()
Dintel_combo_phy_regs.h156 #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MAS…
Dskl_watermark.c2257 val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks); in skl_write_wm_level()
2258 val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines); in skl_write_wm_level()
/linux-6.1.9/drivers/gpu/drm/i915/
Di915_reg.h657 #define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
659 #define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
678 #define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
681 #define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
684 #define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))
689 #define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))
691 #define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
693 #define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))
696 #define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))
699 #define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))
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Dintel_pcode.c224 mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd) in snb_pcode_read_p()
225 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1) in snb_pcode_read_p()
226 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2); in snb_pcode_read_p()
240 mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd) in snb_pcode_write_p()
241 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1) in snb_pcode_write_p()
242 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2); in snb_pcode_write_p()
Di915_reg_defs.h70 #define REG_FIELD_PREP(__mask, __val) \ macro
/linux-6.1.9/drivers/gpu/drm/i915/gt/
Dintel_gpu_commands.h243 REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
245 REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
257 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1)
259 REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1)
Dintel_engine_regs.h135 (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
136 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
152 (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
153 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
Dintel_gt_regs.h389 #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
391 #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
1003 #define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
1114 #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
1138 #define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL, 0x2)
Dintel_workarounds.c573 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); in dg2_ctx_gt_tuning_init()
2138 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); in rcs_engine_wa_init()
Dintel_lrc.c1277 *cs++ = REG_FIELD_PREP(VERT_WM_VAL, 0x3FF); in dg2_emit_draw_watermark_setting()
/linux-6.1.9/drivers/gpu/drm/i915/gt/uc/
Dintel_guc.c131 u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); in gen11_enable_guc_interrupts()