Searched refs:REGBASE (Results 1 – 6 of 6) sorted by relevance
88 REGBASE = DPRBASE + 0x1000 define89 PICR = REGBASE + 0x026 // 16-bit periodic irq control90 PITR = REGBASE + 0x02A // 16-bit periodic irq timing91 OR1 = REGBASE + 0x064 // 32-bit RAM bank #1 options92 CICR = REGBASE + 0x540 // 32(24)-bit CP interrupt config93 CIMR = REGBASE + 0x548 // 32-bit CP interrupt mask94 CISR = REGBASE + 0x54C // 32-bit CP interrupts in-service95 PADIR = REGBASE + 0x550 // 16-bit PortA data direction bitmap96 PAPAR = REGBASE + 0x552 // 16-bit PortA pin assignment bitmap97 PAODR = REGBASE + 0x554 // 16-bit PortA open drain bitmap[all …]
11 #define IC_GROUP0_PEND (REGBASE + 0x38000)12 #define IC_GROUP0_MASK (REGBASE + 0x38008)
10 #define REGBASE 0x18000000 macro11 #define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))
58 .start = REGBASE + GPIOBASE,59 .end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
44 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
215 .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),