Searched refs:RADEON_AIC_CNTL (Results 1 – 2 of 2) sorted by relevance
675 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; in r100_pci_gart_enable()676 WREG32(RADEON_AIC_CNTL, tmp); in r100_pci_gart_enable()682 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; in r100_pci_gart_enable()683 WREG32(RADEON_AIC_CNTL, tmp); in r100_pci_gart_enable()697 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; in r100_pci_gart_disable()698 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); in r100_pci_gart_disable()832 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; in r100_irq_process()833 WREG32(RADEON_AIC_CNTL, msi_rearm); in r100_irq_process()834 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); in r100_irq_process()
3365 #define RADEON_AIC_CNTL 0x01d0 macro