1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #ifndef ATH11K_QMI_H
8 #define ATH11K_QMI_H
9 
10 #include <linux/mutex.h>
11 #include <linux/soc/qcom/qmi.h>
12 
13 #define ATH11K_HOST_VERSION_STRING		"WIN"
14 #define ATH11K_QMI_WLANFW_TIMEOUT_MS		10000
15 #define ATH11K_QMI_MAX_BDF_FILE_NAME_SIZE	64
16 #define ATH11K_QMI_CALDB_ADDRESS		0x4BA00000
17 #define ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01	128
18 #define ATH11K_QMI_WLFW_SERVICE_ID_V01		0x45
19 #define ATH11K_QMI_WLFW_SERVICE_VERS_V01	0x01
20 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01	0x02
21 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390	0x01
22 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074	0x02
23 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074	0x07
24 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_WCN6750	0x03
25 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01	32
26 #define ATH11K_QMI_RESP_LEN_MAX			8192
27 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01	52
28 #define ATH11K_QMI_CALDB_SIZE			0x480000
29 #define ATH11K_QMI_BDF_EXT_STR_LENGTH		0x20
30 #define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT	5
31 
32 #define QMI_WLFW_REQUEST_MEM_IND_V01		0x0035
33 #define QMI_WLFW_FW_MEM_READY_IND_V01		0x0037
34 #define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01	0x003E
35 #define QMI_WLFW_FW_READY_IND_V01		0x0021
36 #define QMI_WLFW_FW_INIT_DONE_IND_V01		0x0038
37 
38 #define QMI_WLANFW_MAX_DATA_SIZE_V01		6144
39 #define ATH11K_FIRMWARE_MODE_OFF		4
40 #define ATH11K_COLD_BOOT_FW_RESET_DELAY		(40 * HZ)
41 
42 #define ATH11K_QMI_DEVICE_BAR_SIZE		0x200000
43 
44 struct ath11k_base;
45 
46 enum ath11k_qmi_file_type {
47 	ATH11K_QMI_FILE_TYPE_BDF_GOLDEN,
48 	ATH11K_QMI_FILE_TYPE_CALDATA = 2,
49 	ATH11K_QMI_FILE_TYPE_EEPROM,
50 	ATH11K_QMI_MAX_FILE_TYPE,
51 };
52 
53 enum ath11k_qmi_bdf_type {
54 	ATH11K_QMI_BDF_TYPE_BIN			= 0,
55 	ATH11K_QMI_BDF_TYPE_ELF			= 1,
56 	ATH11K_QMI_BDF_TYPE_REGDB		= 4,
57 };
58 
59 enum ath11k_qmi_event_type {
60 	ATH11K_QMI_EVENT_SERVER_ARRIVE,
61 	ATH11K_QMI_EVENT_SERVER_EXIT,
62 	ATH11K_QMI_EVENT_REQUEST_MEM,
63 	ATH11K_QMI_EVENT_FW_MEM_READY,
64 	ATH11K_QMI_EVENT_FW_READY,
65 	ATH11K_QMI_EVENT_COLD_BOOT_CAL_START,
66 	ATH11K_QMI_EVENT_COLD_BOOT_CAL_DONE,
67 	ATH11K_QMI_EVENT_REGISTER_DRIVER,
68 	ATH11K_QMI_EVENT_UNREGISTER_DRIVER,
69 	ATH11K_QMI_EVENT_RECOVERY,
70 	ATH11K_QMI_EVENT_FORCE_FW_ASSERT,
71 	ATH11K_QMI_EVENT_POWER_UP,
72 	ATH11K_QMI_EVENT_POWER_DOWN,
73 	ATH11K_QMI_EVENT_FW_INIT_DONE,
74 	ATH11K_QMI_EVENT_MAX,
75 };
76 
77 struct ath11k_qmi_driver_event {
78 	struct list_head list;
79 	enum ath11k_qmi_event_type type;
80 	void *data;
81 };
82 
83 struct ath11k_qmi_ce_cfg {
84 	const struct ce_pipe_config *tgt_ce;
85 	int tgt_ce_len;
86 	const struct service_to_pipe *svc_to_ce_map;
87 	int svc_to_ce_map_len;
88 	const u8 *shadow_reg;
89 	int shadow_reg_len;
90 	u32 *shadow_reg_v2;
91 	int shadow_reg_v2_len;
92 };
93 
94 struct ath11k_qmi_event_msg {
95 	struct list_head list;
96 	enum ath11k_qmi_event_type type;
97 };
98 
99 struct target_mem_chunk {
100 	u32 size;
101 	u32 type;
102 	u32 prev_size;
103 	u32 prev_type;
104 	dma_addr_t paddr;
105 	u32 *vaddr;
106 	void __iomem *iaddr;
107 };
108 
109 struct target_info {
110 	u32 chip_id;
111 	u32 chip_family;
112 	u32 board_id;
113 	u32 soc_id;
114 	u32 fw_version;
115 	u32 eeprom_caldata;
116 	char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
117 	char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
118 	char bdf_ext[ATH11K_QMI_BDF_EXT_STR_LENGTH];
119 };
120 
121 struct m3_mem_region {
122 	u32 size;
123 	dma_addr_t paddr;
124 	void *vaddr;
125 };
126 
127 struct ath11k_qmi {
128 	struct ath11k_base *ab;
129 	struct qmi_handle handle;
130 	struct sockaddr_qrtr sq;
131 	struct work_struct event_work;
132 	struct workqueue_struct *event_wq;
133 	struct list_head event_list;
134 	spinlock_t event_lock; /* spinlock for qmi event list */
135 	struct ath11k_qmi_ce_cfg ce_cfg;
136 	struct target_mem_chunk target_mem[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
137 	u32 mem_seg_count;
138 	u32 target_mem_mode;
139 	bool target_mem_delayed;
140 	u8 cal_done;
141 	struct target_info target;
142 	struct m3_mem_region m3_mem;
143 	unsigned int service_ins_id;
144 	wait_queue_head_t cold_boot_waitq;
145 };
146 
147 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN		261
148 #define QMI_WLANFW_HOST_CAP_REQ_V01			0x0034
149 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN	7
150 #define QMI_WLFW_HOST_CAP_RESP_V01			0x0034
151 #define QMI_WLFW_MAX_NUM_GPIO_V01			32
152 #define QMI_IPQ8074_FW_MEM_MODE				0xFF
153 #define HOST_DDR_REGION_TYPE				0x1
154 #define BDF_MEM_REGION_TYPE				0x2
155 #define M3_DUMP_REGION_TYPE				0x3
156 #define CALDB_MEM_REGION_TYPE				0x4
157 
158 struct qmi_wlanfw_host_cap_req_msg_v01 {
159 	u8 num_clients_valid;
160 	u32 num_clients;
161 	u8 wake_msi_valid;
162 	u32 wake_msi;
163 	u8 gpios_valid;
164 	u32 gpios_len;
165 	u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01];
166 	u8 nm_modem_valid;
167 	u8 nm_modem;
168 	u8 bdf_support_valid;
169 	u8 bdf_support;
170 	u8 bdf_cache_support_valid;
171 	u8 bdf_cache_support;
172 	u8 m3_support_valid;
173 	u8 m3_support;
174 	u8 m3_cache_support_valid;
175 	u8 m3_cache_support;
176 	u8 cal_filesys_support_valid;
177 	u8 cal_filesys_support;
178 	u8 cal_cache_support_valid;
179 	u8 cal_cache_support;
180 	u8 cal_done_valid;
181 	u8 cal_done;
182 	u8 mem_bucket_valid;
183 	u32 mem_bucket;
184 	u8 mem_cfg_mode_valid;
185 	u8 mem_cfg_mode;
186 };
187 
188 struct qmi_wlanfw_host_cap_resp_msg_v01 {
189 	struct qmi_response_type_v01 resp;
190 };
191 
192 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN		54
193 #define QMI_WLANFW_IND_REGISTER_REQ_V01				0x0020
194 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN		18
195 #define QMI_WLANFW_IND_REGISTER_RESP_V01			0x0020
196 #define QMI_WLANFW_CLIENT_ID					0x4b4e454c
197 
198 struct qmi_wlanfw_ind_register_req_msg_v01 {
199 	u8 fw_ready_enable_valid;
200 	u8 fw_ready_enable;
201 	u8 initiate_cal_download_enable_valid;
202 	u8 initiate_cal_download_enable;
203 	u8 initiate_cal_update_enable_valid;
204 	u8 initiate_cal_update_enable;
205 	u8 msa_ready_enable_valid;
206 	u8 msa_ready_enable;
207 	u8 pin_connect_result_enable_valid;
208 	u8 pin_connect_result_enable;
209 	u8 client_id_valid;
210 	u32 client_id;
211 	u8 request_mem_enable_valid;
212 	u8 request_mem_enable;
213 	u8 fw_mem_ready_enable_valid;
214 	u8 fw_mem_ready_enable;
215 	u8 fw_init_done_enable_valid;
216 	u8 fw_init_done_enable;
217 	u8 rejuvenate_enable_valid;
218 	u32 rejuvenate_enable;
219 	u8 xo_cal_enable_valid;
220 	u8 xo_cal_enable;
221 	u8 cal_done_enable_valid;
222 	u8 cal_done_enable;
223 };
224 
225 struct qmi_wlanfw_ind_register_resp_msg_v01 {
226 	struct qmi_response_type_v01 resp;
227 	u8 fw_status_valid;
228 	u64 fw_status;
229 };
230 
231 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN	1824
232 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN	888
233 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN	7
234 #define QMI_WLANFW_REQUEST_MEM_IND_V01			0x0035
235 #define QMI_WLANFW_RESPOND_MEM_REQ_V01			0x0036
236 #define QMI_WLANFW_RESPOND_MEM_RESP_V01			0x0036
237 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01			2
238 
239 struct qmi_wlanfw_mem_cfg_s_v01 {
240 	u64 offset;
241 	u32 size;
242 	u8 secure_flag;
243 };
244 
245 enum qmi_wlanfw_mem_type_enum_v01 {
246 	WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
247 	QMI_WLANFW_MEM_TYPE_MSA_V01 = 0,
248 	QMI_WLANFW_MEM_TYPE_DDR_V01 = 1,
249 	QMI_WLANFW_MEM_BDF_V01 = 2,
250 	QMI_WLANFW_MEM_M3_V01 = 3,
251 	QMI_WLANFW_MEM_CAL_V01 = 4,
252 	QMI_WLANFW_MEM_DPD_V01 = 5,
253 	WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
254 };
255 
256 struct qmi_wlanfw_mem_seg_s_v01 {
257 	u32 size;
258 	enum qmi_wlanfw_mem_type_enum_v01 type;
259 	u32 mem_cfg_len;
260 	struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01];
261 };
262 
263 struct qmi_wlanfw_request_mem_ind_msg_v01 {
264 	u32 mem_seg_len;
265 	struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
266 };
267 
268 struct qmi_wlanfw_mem_seg_resp_s_v01 {
269 	u64 addr;
270 	u32 size;
271 	enum qmi_wlanfw_mem_type_enum_v01 type;
272 	u8 restore;
273 };
274 
275 struct qmi_wlanfw_respond_mem_req_msg_v01 {
276 	u32 mem_seg_len;
277 	struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
278 };
279 
280 struct qmi_wlanfw_respond_mem_resp_msg_v01 {
281 	struct qmi_response_type_v01 resp;
282 };
283 
284 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 {
285 	char placeholder;
286 };
287 
288 struct qmi_wlanfw_fw_ready_ind_msg_v01 {
289 	char placeholder;
290 };
291 
292 struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 {
293 	char placeholder;
294 };
295 
296 struct qmi_wlfw_fw_init_done_ind_msg_v01 {
297 	char placeholder;
298 };
299 
300 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN		0
301 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN		235
302 #define QMI_WLANFW_CAP_REQ_V01				0x0024
303 #define QMI_WLANFW_CAP_RESP_V01				0x0024
304 #define QMI_WLANFW_DEVICE_INFO_REQ_V01			0x004C
305 #define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01_MAX_LEN	0
306 
307 enum qmi_wlanfw_pipedir_enum_v01 {
308 	QMI_WLFW_PIPEDIR_NONE_V01 = 0,
309 	QMI_WLFW_PIPEDIR_IN_V01 = 1,
310 	QMI_WLFW_PIPEDIR_OUT_V01 = 2,
311 	QMI_WLFW_PIPEDIR_INOUT_V01 = 3,
312 };
313 
314 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 {
315 	__le32 pipe_num;
316 	__le32 pipe_dir;
317 	__le32 nentries;
318 	__le32 nbytes_max;
319 	__le32 flags;
320 };
321 
322 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 {
323 	__le32 service_id;
324 	__le32 pipe_dir;
325 	__le32 pipe_num;
326 };
327 
328 struct qmi_wlanfw_shadow_reg_cfg_s_v01 {
329 	u16 id;
330 	u16 offset;
331 };
332 
333 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 {
334 	u32 addr;
335 };
336 
337 struct qmi_wlanfw_memory_region_info_s_v01 {
338 	u64 region_addr;
339 	u32 size;
340 	u8 secure_flag;
341 };
342 
343 struct qmi_wlanfw_rf_chip_info_s_v01 {
344 	u32 chip_id;
345 	u32 chip_family;
346 };
347 
348 struct qmi_wlanfw_rf_board_info_s_v01 {
349 	u32 board_id;
350 };
351 
352 struct qmi_wlanfw_soc_info_s_v01 {
353 	u32 soc_id;
354 };
355 
356 struct qmi_wlanfw_fw_version_info_s_v01 {
357 	u32 fw_version;
358 	char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
359 };
360 
361 enum qmi_wlanfw_cal_temp_id_enum_v01 {
362 	QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0,
363 	QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1,
364 	QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2,
365 	QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3,
366 	QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4,
367 	QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF,
368 };
369 
370 struct qmi_wlanfw_cap_resp_msg_v01 {
371 	struct qmi_response_type_v01 resp;
372 	u8 chip_info_valid;
373 	struct qmi_wlanfw_rf_chip_info_s_v01 chip_info;
374 	u8 board_info_valid;
375 	struct qmi_wlanfw_rf_board_info_s_v01 board_info;
376 	u8 soc_info_valid;
377 	struct qmi_wlanfw_soc_info_s_v01 soc_info;
378 	u8 fw_version_info_valid;
379 	struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info;
380 	u8 fw_build_id_valid;
381 	char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
382 	u8 num_macs_valid;
383 	u8 num_macs;
384 	u8 voltage_mv_valid;
385 	u32 voltage_mv;
386 	u8 time_freq_hz_valid;
387 	u32 time_freq_hz;
388 	u8 otp_version_valid;
389 	u32 otp_version;
390 	u8 eeprom_read_timeout_valid;
391 	u32 eeprom_read_timeout;
392 };
393 
394 struct qmi_wlanfw_cap_req_msg_v01 {
395 	char placeholder;
396 };
397 
398 struct qmi_wlanfw_device_info_req_msg_v01 {
399 	char placeholder;
400 };
401 
402 struct qmi_wlanfw_device_info_resp_msg_v01 {
403 	struct qmi_response_type_v01 resp;
404 	u64 bar_addr;
405 	u32 bar_size;
406 	u8 bar_addr_valid;
407 	u8 bar_size_valid;
408 };
409 
410 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN	6182
411 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN	7
412 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01		0x0025
413 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01			0x0025
414 /* TODO: Need to check with MCL and FW team that data can be pointer and
415  * can be last element in structure
416  */
417 struct qmi_wlanfw_bdf_download_req_msg_v01 {
418 	u8 valid;
419 	u8 file_id_valid;
420 	enum qmi_wlanfw_cal_temp_id_enum_v01 file_id;
421 	u8 total_size_valid;
422 	u32 total_size;
423 	u8 seg_id_valid;
424 	u32 seg_id;
425 	u8 data_valid;
426 	u32 data_len;
427 	u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01];
428 	u8 end_valid;
429 	u8 end;
430 	u8 bdf_type_valid;
431 	u8 bdf_type;
432 
433 };
434 
435 struct qmi_wlanfw_bdf_download_resp_msg_v01 {
436 	struct qmi_response_type_v01 resp;
437 };
438 
439 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN	18
440 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN	7
441 #define QMI_WLANFW_M3_INFO_RESP_V01		0x003C
442 #define QMI_WLANFW_M3_INFO_REQ_V01		0x003C
443 
444 struct qmi_wlanfw_m3_info_req_msg_v01 {
445 	u64 addr;
446 	u32 size;
447 };
448 
449 struct qmi_wlanfw_m3_info_resp_msg_v01 {
450 	struct qmi_response_type_v01 resp;
451 };
452 
453 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN	11
454 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN	7
455 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN		803
456 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN	7
457 #define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN		4
458 #define QMI_WLANFW_WLAN_MODE_REQ_V01			0x0022
459 #define QMI_WLANFW_WLAN_MODE_RESP_V01			0x0022
460 #define QMI_WLANFW_WLAN_CFG_REQ_V01			0x0023
461 #define QMI_WLANFW_WLAN_CFG_RESP_V01			0x0023
462 #define QMI_WLANFW_WLAN_INI_REQ_V01			0x002F
463 #define QMI_WLANFW_MAX_STR_LEN_V01			16
464 #define QMI_WLANFW_MAX_NUM_CE_V01			12
465 #define QMI_WLANFW_MAX_NUM_SVC_V01			24
466 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01		24
467 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01		36
468 
469 struct qmi_wlanfw_wlan_mode_req_msg_v01 {
470 	u32 mode;
471 	u8 hw_debug_valid;
472 	u8 hw_debug;
473 };
474 
475 struct qmi_wlanfw_wlan_mode_resp_msg_v01 {
476 	struct qmi_response_type_v01 resp;
477 };
478 
479 struct qmi_wlanfw_wlan_cfg_req_msg_v01 {
480 	u8 host_version_valid;
481 	char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1];
482 	u8  tgt_cfg_valid;
483 	u32  tgt_cfg_len;
484 	struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01
485 			tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01];
486 	u8  svc_cfg_valid;
487 	u32 svc_cfg_len;
488 	struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01
489 			svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01];
490 	u8 shadow_reg_valid;
491 	u32 shadow_reg_len;
492 	struct qmi_wlanfw_shadow_reg_cfg_s_v01
493 		shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01];
494 	u8 shadow_reg_v2_valid;
495 	u32 shadow_reg_v2_len;
496 	struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01
497 		shadow_reg_v2[QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01];
498 };
499 
500 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 {
501 	struct qmi_response_type_v01 resp;
502 };
503 
504 struct qmi_wlanfw_wlan_ini_req_msg_v01 {
505 	/* Must be set to true if enablefwlog is being passed */
506 	u8 enablefwlog_valid;
507 	u8 enablefwlog;
508 };
509 
510 struct qmi_wlanfw_wlan_ini_resp_msg_v01 {
511 	struct qmi_response_type_v01 resp;
512 };
513 
514 int ath11k_qmi_firmware_start(struct ath11k_base *ab,
515 			      u32 mode);
516 void ath11k_qmi_firmware_stop(struct ath11k_base *ab);
517 void ath11k_qmi_event_work(struct work_struct *work);
518 void ath11k_qmi_msg_recv_work(struct work_struct *work);
519 void ath11k_qmi_deinit_service(struct ath11k_base *ab);
520 int ath11k_qmi_init_service(struct ath11k_base *ab);
521 void ath11k_qmi_free_resource(struct ath11k_base *ab);
522 
523 #endif
524