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Searched refs:PXA1928_CLK_UART1 (Results 1 – 2 of 2) sorted by relevance

/linux-6.1.9/drivers/clk/mmp/
Dclk-of-pxa1928.c97 …t_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 4, 3, 0…
120 …{PXA1928_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 0x3, 0x3…
/linux-6.1.9/include/dt-bindings/clock/
Dmarvell,pxa1928.h21 #define PXA1928_CLK_UART1 0x0c macro