Searched refs:PRCMU_DSI0CLK (Results 1 – 5 of 5) sorted by relevance
68 #define PRCMU_DSI0CLK 47 macro
1381 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) in db8500_prcmu_request_clock()1382 return request_dsiclk((clock - PRCMU_DSI0CLK), enable); in db8500_prcmu_request_clock()1558 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) in prcmu_clock_rate()1559 return dsiclk_rate(clock - PRCMU_DSI0CLK); in prcmu_clock_rate()1739 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) in prcmu_round_clock_rate()1911 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) in prcmu_set_clock_rate()1912 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); in prcmu_set_clock_rate()
133 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
280 u8500_prcmu_hw_clks.hws[PRCMU_DSI0CLK] = in u8500_clk_init()282 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE); in u8500_clk_init()
1124 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;