Searched refs:PP_SMU_RESULT_OK (Results 1 – 4 of 4) sorted by relevance
560 return PP_SMU_RESULT_OK; in pp_nv_set_wm_ranges()576 return PP_SMU_RESULT_OK; in pp_nv_set_display_count()593 return PP_SMU_RESULT_OK; in pp_nv_set_min_deep_sleep_dcfclk()616 return PP_SMU_RESULT_OK; in pp_nv_set_hard_min_dcefclk_by_freq()639 return PP_SMU_RESULT_OK; in pp_nv_set_hard_min_uclk_by_freq()652 return PP_SMU_RESULT_OK; in pp_nv_set_pstate_handshake_support()687 return PP_SMU_RESULT_OK; in pp_nv_set_voltage_by_freq()704 return PP_SMU_RESULT_OK; in pp_nv_get_maximum_sustainable_clocks()722 return PP_SMU_RESULT_OK; in pp_nv_get_uclk_dpm_states()738 return PP_SMU_RESULT_OK; in pp_rn_get_dpm_clock_table()[all …]
62 PP_SMU_RESULT_OK = 1, enumerator
780 if (status == PP_SMU_RESULT_OK && in rn_clk_mgr_construct()
2352 uclk_states_available = (status == PP_SMU_RESULT_OK); in init_soc_bounding_box()2362 clock_limits_available = (status == PP_SMU_RESULT_OK); in init_soc_bounding_box()