Searched refs:PORT_PLL_M2_INT_MASK (Results 1 – 3 of 3) sorted by relevance
1952 temp &= ~PORT_PLL_M2_INT_MASK; in bxt_ddi_pll_enable()2088 hw_state->pll0 &= PORT_PLL_M2_INT_MASK; in bxt_ddi_pll_get_hw_state()2263 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, pll_state->pll0) << 22; in bxt_ddi_pll_get_freq()
677 #define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0) macro678 #define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
565 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, in bxt_vgpu_get_dp_bitrate()