| /linux-6.1.9/drivers/clk/samsung/ |
| D | clk-exynos5420.c | 293 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
295 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
296 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
297 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
298 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
299 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
300 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
301 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
302 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
303 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
[all …]
|
| D | clk-exynos5260.c | 88 PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
89 PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"};
90 PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"};
169 PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
171 PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
173 PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
175 PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
177 PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
178 PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
179 PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
[all …]
|
| D | clk-exynos7.c | 45 PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
46 PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
47 PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
48 PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
49 PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
51 PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
55 PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
57 PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
59 PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
61 PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
[all …]
|
| D | clk-exynos7885.c | 161 PNAME(mout_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
163 PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
165 PNAME(mout_core_g3d_p) = { "dout_shared0_div2", "dout_shared1_div2",
169 PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
170 PNAME(mout_peri_spi0_p) = { "oscclk", "dout_shared0_div4" };
171 PNAME(mout_peri_spi1_p) = { "oscclk", "dout_shared0_div4" };
172 PNAME(mout_peri_uart0_p) = { "oscclk", "dout_shared0_div4" };
173 PNAME(mout_peri_uart1_p) = { "oscclk", "dout_shared0_div4" };
174 PNAME(mout_peri_uart2_p) = { "oscclk", "dout_shared0_div4" };
175 PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" };
[all …]
|
| D | clk-exynos850.c | 200 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
201 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
202 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
204 PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
206 PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2",
209 PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
211 PNAME(mout_core_cci_p) = { "dout_shared0_div2", "dout_shared1_div2",
213 PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
217 PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
220 PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" };
[all …]
|
| D | clk-exynosautov9.c | 357 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
358 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
359 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
360 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
361 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
363 PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4",
365 PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" };
366 PNAME(mout_clkcmu_acc_bus_p) = { "dout_shared1_div3", "dout_shared2_div3",
368 PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared2_div3", "dout_shared1_div4",
370 PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2",
[all …]
|
| D | clk-exynos5433.c | 190 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
191 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
192 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
193 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
194 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
195 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
196 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
197 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
199 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
200 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
[all …]
|
| D | clk-exynos4.c | 279 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
280 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
281 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
282 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
283 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
284 PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
285 PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
286 PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
287 PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
288 PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
[all …]
|
| D | clk-exynos5250.c | 170 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
171 PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
172 PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
173 PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
174 PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
175 PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
176 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
177 PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
178 PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
179 PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
[all …]
|
| D | clk-exynos5410.c | 67 PNAME(apll_p) = { "fin_pll", "fout_apll", };
68 PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
69 PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
70 PNAME(epll_p) = { "fin_pll", "fout_epll" };
71 PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
72 PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
74 PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
75 PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
77 PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
78 PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
[all …]
|
| D | clk-exynos3250.c | 174 PNAME(mout_vpllsrc_p) = { "fin_pll", };
176 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
177 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
178 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
179 PNAME(mout_upll_p) = { "fin_pll", "fout_upll", };
181 PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
182 PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", };
183 PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
184 PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
186 PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
[all …]
|
| D | clk-s3c2412.c | 75 PNAME(erefclk_p) = { "xti", "xti", "xti", "ext" };
76 PNAME(urefclk_p) = { "xti", "xti", "xti", "ext" };
78 PNAME(camclk_p) = { "usysclk", "hclk" };
79 PNAME(usbclk_p) = { "usysclk", "hclk" };
80 PNAME(i2sclk_p) = { "erefclk", "mpll" };
81 PNAME(uartclk_p) = { "erefclk", "mpll" };
82 PNAME(usysclk_p) = { "urefclk", "upll" };
83 PNAME(msysclk_p) = { "mdivclk", "mpll" };
84 PNAME(mdivclk_p) = { "xti", "div_xti" };
85 PNAME(armclk_p) = { "armdiv", "hclk" };
|
| D | clk-s3c64xx.c | 86 PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
87 PNAME(uart_p) = { "mout_epll", "dout_mpll" };
88 PNAME(audio0_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
90 PNAME(audio1_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
92 PNAME(mfc_p) = { "hclkx2", "mout_epll" };
93 PNAME(apll_p) = { "fin_pll", "fout_apll" };
94 PNAME(mpll_p) = { "fin_pll", "fout_mpll" };
95 PNAME(epll_p) = { "fin_pll", "fout_epll" };
96 PNAME(hclkx2_p) = { "mout_mpll", "mout_apll" };
99 PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" };
[all …]
|
| /linux-6.1.9/drivers/clk/rockchip/ |
| D | clk-rk3568.c | 211 PNAME(mux_pll_p) = { "xin24m" };
212 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" };
213 PNAME(mux_armclk_p) = { "apll", "gpll" };
214 PNAME(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin_os…
215 PNAME(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin_os…
216 PNAME(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin_os…
217 PNAME(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin_os…
218 PNAME(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin_osc0_half …
219 PNAME(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", "i2s3_mclkin", "xin_os…
220 PNAME(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", "i2s3_mclkin", "xin_os…
[all …]
|
| D | clk-rk3308.c | 122 PNAME(mux_pll_p) = { "xin24m" };
123 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
124 PNAME(mux_armclk_p) = { "apll_core", "vpll0_core", "vpll1_core" };
125 PNAME(mux_dpll_vpll0_p) = { "dpll", "vpll0" };
126 PNAME(mux_dpll_vpll0_xin24m_p) = { "dpll", "vpll0", "xin24m" };
127 PNAME(mux_dpll_vpll0_vpll1_p) = { "dpll", "vpll0", "vpll1" };
128 PNAME(mux_dpll_vpll0_vpll1_xin24m_p) = { "dpll", "vpll0", "vpll1", "xin24m" };
129 PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p) = { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" };
130 PNAME(mux_vpll0_vpll1_p) = { "vpll0", "vpll1" };
131 PNAME(mux_vpll0_vpll1_xin24m_p) = { "vpll0", "vpll1", "xin24m" };
[all …]
|
| D | clk-px30.c | 137 PNAME(mux_pll_p) = { "xin24m"};
138 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
139 PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
140 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
141 PNAME(mux_ddrstdby_p) = { "clk_ddrphy1x", "clk_stdby_2wrap" };
142 PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" };
143 PNAME(mux_cpll_npll_p) = { "cpll", "npll" };
144 PNAME(mux_npll_cpll_p) = { "npll", "cpll" };
145 PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" };
146 PNAME(mux_gpll_npll_p) = { "gpll", "npll" };
[all …]
|
| D | clk-rv1126.c | 145 PNAME(mux_pll_p) = { "xin24m" };
146 PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
147 PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
148 PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
149 PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
150 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
151 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
152 PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
153 PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
154 PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
[all …]
|
| D | clk-rk3228.c | 132 PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
134 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
135 PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
136 PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
137 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
138 PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
139 PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
141 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy", "usb480m" };
142 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
143 PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
[all …]
|
| D | clk-rv1108.c | 119 PNAME(mux_pll_p) = { "xin24m", "xin24m"};
120 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
121 PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
122 PNAME(mux_usb480m_pre_p) = { "usbphy", "xin24m" };
123 PNAME(mux_hdmiphy_phy_p) = { "hdmiphy", "xin24m" };
124 PNAME(mux_dclk_hdmiphy_pre_p) = { "dclk_hdmiphy_src_gpll", "dclk_hdmiphy_src_dpll" };
125 PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" };
126 PNAME(mux_pll_src_2plls_p) = { "dpll", "gpll" };
127 PNAME(mux_pll_src_apll_gpll_p) = { "apll", "gpll" };
128 PNAME(mux_aclk_peri_src_p) = { "aclk_peri_src_gpll", "aclk_peri_src_dpll" };
[all …]
|
| D | clk-rk3328.c | 143 PNAME(mux_pll_p) = { "xin24m" };
145 PNAME(mux_2plls_p) = { "cpll", "gpll" };
146 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
147 PNAME(mux_cpll_gpll_apll_p) = { "cpll", "gpll", "apll" };
148 PNAME(mux_2plls_xin24m_p) = { "cpll", "gpll", "xin24m" };
149 PNAME(mux_2plls_hdmiphy_p) = { "cpll", "gpll",
151 PNAME(mux_4plls_p) = { "cpll", "gpll",
154 PNAME(mux_2plls_u480m_p) = { "cpll", "gpll",
156 PNAME(mux_2plls_24m_u480m_p) = { "cpll", "gpll",
159 PNAME(mux_ddrphy_p) = { "dpll", "apll", "cpll" };
[all …]
|
| D | clk-rk3399.c | 109 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
111 PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
115 PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
119 PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
123 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
127 PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
129 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
131 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
134 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
135 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
[all …]
|
| D | clk-rk3368.c | 90 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
91 PNAME(mux_armclkb_p) = { "apllb_core", "gpllb_core" };
92 PNAME(mux_armclkl_p) = { "aplll_core", "gplll_core" };
93 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
94 PNAME(mux_cs_src_p) = { "apllb_cs", "aplll_cs", "gpll_cs"};
95 PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" };
97 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
98 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
99 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
100 PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" };
[all …]
|
| D | clk-rk3036.c | 115 PNAME(mux_pll_p) = { "xin24m", "xin24m" };
117 PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
118 PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" };
119 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
120 PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
121 PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
123 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
124 PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
126 PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
127 PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
[all …]
|
| D | clk-rk3128.c | 130 PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
132 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_div2_ddr" };
133 PNAME(mux_armclk_p) = { "apll_core", "gpll_div2_core" };
134 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
135 PNAME(mux_aclk_cpu_src_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3" };
137 PNAME(mux_pll_src_5plls_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m" };
138 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "gpll_div2", "usb480m" };
139 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "gpll_div2" };
141 PNAME(mux_aclk_peri_src_p) = { "gpll_peri", "cpll_peri", "gpll_div2_peri", "gpll_div3_peri" };
142 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "gpll_div2", "xin24m" };
[all …]
|
| /linux-6.1.9/drivers/clk/pistachio/ |
| D | clk-pistachio.c | 105 PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };
106 PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };
107 PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };
108 PNAME(mux_audio_debug) = { "audio_pll_mux", "debug_mux" };
109 PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };
110 PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };
111 PNAME(mux_rpu_l_mips) = { "rpu_l_pll_mux", "mips_pll_mux" };
112 PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };
113 PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };
114 PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };
[all …]
|