Searched refs:PLL_OUTCTRL (Results 1 – 3 of 3) sorted by relevance
| /linux-6.1.9/drivers/clk/qcom/ |
| D | clk-hfpll.c | 15 #define PLL_OUTCTRL BIT(0) macro
87 regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL); in __clk_hfpll_enable()
101 if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) in clk_hfpll_enable()
118 PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0); in __clk_hfpll_disable()
210 if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { in clk_hfpll_init()
237 return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); in hfpll_is_enabled()
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| D | clk-pll.c | 20 #define PLL_OUTCTRL BIT(0) macro
30 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
62 PLL_OUTCTRL); in clk_pll_enable()
75 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_disable()
147 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_set_rate()
296 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_sr2_enable()
297 PLL_OUTCTRL); in clk_pll_sr2_enable()
307 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_sr2_set_rate()
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| D | clk-alpha-pll.c | 17 # define PLL_OUTCTRL BIT(0) macro
434 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_alpha_pll_enable()
473 PLL_OUTCTRL, PLL_OUTCTRL); in clk_alpha_pll_enable()
496 mask = PLL_OUTCTRL; in clk_alpha_pll_disable()
870 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL)); in trion_pll_is_enabled()
914 PLL_OUTCTRL, PLL_OUTCTRL); in clk_trion_pll_enable()
935 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in clk_trion_pll_disable()
1162 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL)) in alpha_pll_fabia_enable()
1165 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0); in alpha_pll_fabia_enable()
1191 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, in alpha_pll_fabia_enable()
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