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Searched refs:PLL_INT (Results 1 – 3 of 3) sorted by relevance

/linux-6.1.9/sound/pci/ctxfi/
Dcthardware.h202 #define PLL_INT (1 << 10) /* PLL input-clock out-of-range */ macro
/linux-6.1.9/drivers/gpu/drm/bridge/
Dchipone-icn6211.c84 #define PLL_INT(n) (0x69 + ((n) & 0x1)) /* 0..1 */ macro
340 chipone_writeb(icn, PLL_INT(0), best_m); in chipone_configure_pll()
/linux-6.1.9/drivers/net/ieee802154/
Dmcr20a.c79 static const u8 PLL_INT[16] = { variable
501 ret = regmap_write(lp->regmap_dar, DAR_PLL_INT0, PLL_INT[channel - 11]); in mcr20a_set_channel()