Searched refs:PLLE_AUX (Results 1 – 4 of 4) sorted by relevance
| /linux-6.1.9/drivers/clk/tegra/ |
| D | clk-tegra30.c | 84 #define PLLE_AUX 0x48c macro
875 clk_base + PLLE_AUX, 2, 1, 0, NULL); in tegra30_pll_init()
1032 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
1037 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
|
| D | clk-tegra124.c | 62 #define PLLE_AUX 0x48c macro
479 .aux_reg = PLLE_AUX,
1058 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1064 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
|
| D | clk-tegra210.c | 92 #define PLLE_AUX 0x48c macro
504 value = readl_relaxed(clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_is_enabled()
527 value = readl_relaxed(clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
530 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
535 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
1973 .aux_reg = PLLE_AUX,
3144 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3150 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
|
| D | clk-tegra114.c | 93 #define PLLE_AUX 0x48c macro
563 .aux_reg = PLLE_AUX,
|