Searched refs:PLL1 (Results 1 – 16 of 16) sorted by relevance
| /linux-6.1.9/sound/soc/codecs/ |
| D | ak4642.c | 115 #define PLL1 (1 << 5) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
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| /linux-6.1.9/Documentation/devicetree/bindings/clock/ |
| D | microchip,mpfs-ccc.yaml | 25 - description: PLL1's control registers
37 - description: PLL1's refclk0
38 - description: PLL1's refclk1
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| D | ti,cdce925.txt | 30 For all PLL1, PLL2, ... an optional child node can be used to specify spread
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| D | st,nomadik.txt | 30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
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| /linux-6.1.9/Documentation/arm/sunxi/ |
| D | clocks.rst | 20 PLL1
31 PLL1 |
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| /linux-6.1.9/include/dt-bindings/clock/ |
| D | qcom,mmcc-msm8960.h | 126 #define PLL1 117 macro
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| D | stm32mp13-clks.h | 19 #define PLL1 6 macro
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| D | stm32mp1-clks.h | 183 #define PLL1 176 macro
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| /linux-6.1.9/Documentation/devicetree/bindings/clock/ti/davinci/ |
| D | pll.txt | 10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
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| /linux-6.1.9/Documentation/devicetree/bindings/clock/st/ |
| D | st,flexgen.txt | 31 | | |PLL1 | | | | | | | | | |
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| /linux-6.1.9/drivers/media/dvb-frontends/ |
| D | zl10039.c | 40 PLL1, enumerator
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| /linux-6.1.9/arch/arm/boot/dts/ |
| D | ste-nomadik-stn8815.dtsi | 196 * that is parent of TIMCLK, PLL1 and PLL2
218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
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| /linux-6.1.9/arch/mips/boot/dts/ingenic/ |
| D | gcw0.dts | 442 * Put high-speed peripherals under PLL1, such that we can change the
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| /linux-6.1.9/drivers/clk/nxp/ |
| D | clk-lpc18xx-cgu.c | 519 LPC1XX_CGU_CLK_PLL(PLL1, pll1_src_ids, pll1_ops),
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| /linux-6.1.9/drivers/clk/ |
| D | Kconfig | 201 Y2 and Y3 derive from PLL1
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| D | clk-stm32mp1.c | 1773 PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR),
2093 PLL1,
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