Searched refs:PLANE_CTL_YUV422_ORDER_MASK (Results 1 – 2 of 2) sorted by relevance
225 val & PLANE_CTL_YUV422_ORDER_MASK); in intel_vgpu_decode_primary_plane()
4743 #define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) macro4744 #define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)4745 #define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)4746 #define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)4747 #define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)