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Searched refs:PIXEL_RATE_DIV_NA (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn314/
Ddcn314_dccg.c55 uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA; in dccg314_get_pixel_rate_div()
57 *k1 = PIXEL_RATE_DIV_NA; in dccg314_get_pixel_rate_div()
58 *k2 = PIXEL_RATE_DIV_NA; in dccg314_get_pixel_rate_div()
97 enum pixel_rate_div cur_k1 = PIXEL_RATE_DIV_NA, cur_k2 = PIXEL_RATE_DIV_NA; in dccg314_set_pixel_rate_div()
101 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) { in dccg314_set_pixel_rate_div()
107 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA || (k1 == cur_k1 && k2 == cur_k2)) in dccg314_set_pixel_rate_div()
Ddcn314_hwseq.c372 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) in dcn314_calculate_dccg_k1_k2_values()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_dccg.c52 uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA; in dccg32_get_pixel_rate_div()
54 *k1 = PIXEL_RATE_DIV_NA; in dccg32_get_pixel_rate_div()
55 *k2 = PIXEL_RATE_DIV_NA; in dccg32_get_pixel_rate_div()
95 enum pixel_rate_div cur_k1 = PIXEL_RATE_DIV_NA, cur_k2 = PIXEL_RATE_DIV_NA; in dccg32_set_pixel_rate_div()
99 if (k1 == PIXEL_RATE_DIV_NA || k2 == PIXEL_RATE_DIV_NA) { in dccg32_set_pixel_rate_div()
Ddcn32_hwseq.c1195 if ((*k1_div == PIXEL_RATE_DIV_NA) && (*k2_div == PIXEL_RATE_DIV_NA)) in dcn32_calculate_dccg_k1_k2_values()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/hw/
Ddccg.h63 PIXEL_RATE_DIV_NA = 0xF enumerator
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c664 unsigned int k1_div = PIXEL_RATE_DIV_NA; in dcn20_enable_stream_timing()
665 unsigned int k2_div = PIXEL_RATE_DIV_NA; in dcn20_enable_stream_timing()