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Searched refs:PIPE_B (Results 1 – 25 of 38) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c115 MMIO_D(PIPEDSL(PIPE_B)); in iterate_generic_mmio()
119 MMIO_D(PIPECONF(PIPE_B)); in iterate_generic_mmio()
123 MMIO_D(PIPESTAT(PIPE_B)); in iterate_generic_mmio()
127 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B)); in iterate_generic_mmio()
131 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B)); in iterate_generic_mmio()
135 MMIO_D(CURCNTR(PIPE_B)); in iterate_generic_mmio()
138 MMIO_D(CURPOS(PIPE_B)); in iterate_generic_mmio()
141 MMIO_D(CURBASE(PIPE_B)); in iterate_generic_mmio()
144 MMIO_D(CUR_FBC_CTL(PIPE_B)); in iterate_generic_mmio()
162 MMIO_D(DSPCNTR(PIPE_B)); in iterate_generic_mmio()
[all …]
Di915_pci.c110 [PIPE_B] = CURSOR_B_OFFSET, \
116 [PIPE_B] = CURSOR_B_OFFSET, \
123 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
130 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
176 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
241 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
332 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
386 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
417 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
470 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
[all …]
Di915_reg.h2325 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2328 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2331 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2334 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2353 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2356 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2359 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2362 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2378 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
2381 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
[all …]
Dintel_pm.c479 case PIPE_B: in vlv_get_fifo_size()
955 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
956 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
962 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
1005 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
1006 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in vlv_write_wm_values()
1017 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
1018 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
1030 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
1031 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
[all …]
Dintel_device_info.c322 runtime->num_scalers[PIPE_B] = 2; in intel_device_info_runtime_init()
348 runtime->num_sprites[PIPE_B] = 2; in intel_device_info_runtime_init()
395 runtime->pipe_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init()
Di915_irq.c615 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
1462 case PIPE_B: in i9xx_pipestat_irq_ack()
1897 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); in ibx_irq_handler()
2418 pipe = PIPE_B; in gen11_dsi_te_interrupt_handler()
3966 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
4145 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
4266 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/linux-6.1.9/drivers/gpu/drm/i915/display/
Dskl_watermark.c824 .active_pipes = BIT(PIPE_B),
826 [PIPE_B] = BIT(DBUF_S1),
830 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
833 [PIPE_B] = BIT(DBUF_S2),
850 .active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
852 [PIPE_B] = BIT(DBUF_S1),
857 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
860 [PIPE_B] = BIT(DBUF_S1),
887 .active_pipes = BIT(PIPE_B),
889 [PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2),
[all …]
Dintel_display_power_map.c149 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
378 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
452 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
548 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
710 .irq_pipe_mask = BIT(PIPE_B),
876 .irq_pipe_mask = BIT(PIPE_B),
1031 .irq_pipe_mask = BIT(PIPE_B),
1126 .irq_pipe_mask = BIT(PIPE_B),
1290 .irq_pipe_mask = BIT(PIPE_B),
1427 .irq_pipe_mask = BIT(PIPE_B),
Dintel_display_trace.h43 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
70 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
167 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
Dintel_dpio_phy.c816 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
828 if (pipe != PIPE_B) { in chv_phy_pre_pll_enable()
849 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
858 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
871 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
981 if (pipe != PIPE_B) { in chv_phy_post_pll_disable()
Dintel_pipe_crc.c183 case PIPE_B: in vlv_pipe_crc_ctl_reg()
247 case PIPE_B: in vlv_undo_pipe_scramble_reset()
Dintel_fdi.c164 case PIPE_B: in ilk_check_fdi_lanes()
189 other_crtc = intel_crtc_for_pipe(dev_priv, PIPE_B); in ilk_check_fdi_lanes()
291 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & in cpt_set_fdi_bc_bifurcation()
315 case PIPE_B: in ivb_update_fdi_bc_bifurcation()
Dintel_display_power_well.c1037 if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1038 i830_enable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_enable()
1044 i830_disable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_disable()
1052 intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
1352 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1484 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
Dg4x_hdmi.c310 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { in intel_disable_hdmi()
584 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
Dintel_pch_display.c47 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
65 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_hdmi_disabled()
Dintel_display.h91 PIPE_B, enumerator
110 TRANSCODER_B = PIPE_B,
Dintel_pps.c128 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
263 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
966 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
Di9xx_plane.c910 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_primary_plane_create()
1014 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && in i9xx_get_initial_plane_config()
Dicl_dsi.c854 case PIPE_B: in gen11_dsi_configure_transcoder()
1254 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) in icl_apply_kvmr_pipe_a_wa()
1600 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && in gen11_dsi_sync_state()
1743 *pipe = PIPE_B; in gen11_dsi_get_hw_state()
Dintel_sprite.c462 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_sprite_update_arm()
1750 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
1800 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
Dvlv_dsi.c1060 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
1085 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1924 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
/linux-6.1.9/drivers/gpu/drm/i915/gvt/
Dhandlers.c2265 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
2271 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2272 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2280 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write); in init_generic_mmio_info()
2281 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2304 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write); in init_generic_mmio_info()
2307 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
2310 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status); in init_generic_mmio_info()
2463 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2465 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
[all …]
Dreg.h73 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
82 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
Ddisplay.c50 pipe = PIPE_B; in get_edp_pipe()
625 [PIPE_B] = PIPE_B_VBLANK, in emulate_vblank_on_pipe()
/linux-6.1.9/drivers/video/fbdev/intelfb/
Dintelfbhw.h183 #define PIPE_B 1 macro

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