1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 *
5 * Copyright (C) 2008,2009 STMicroelectronics
6 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
7 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
8 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
9 */
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/device.h>
13 #include <linux/platform_device.h>
14 #include <linux/io.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/spinlock.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/of_device.h>
22 #include <linux/of_address.h>
23 #include <linux/bitops.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 #include <linux/pinctrl/pinconf.h>
28 /* Since we request GPIOs from ourself */
29 #include <linux/pinctrl/consumer.h>
30 #include "pinctrl-nomadik.h"
31 #include "../core.h"
32 #include "../pinctrl-utils.h"
33
34 /*
35 * The GPIO module in the Nomadik family of Systems-on-Chip is an
36 * AMBA device, managing 32 pins and alternate functions. The logic block
37 * is currently used in the Nomadik and ux500.
38 *
39 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
40 */
41
42 /*
43 * pin configurations are represented by 32-bit integers:
44 *
45 * bit 0.. 8 - Pin Number (512 Pins Maximum)
46 * bit 9..10 - Alternate Function Selection
47 * bit 11..12 - Pull up/down state
48 * bit 13 - Sleep mode behaviour
49 * bit 14 - Direction
50 * bit 15 - Value (if output)
51 * bit 16..18 - SLPM pull up/down state
52 * bit 19..20 - SLPM direction
53 * bit 21..22 - SLPM Value (if output)
54 * bit 23..25 - PDIS value (if input)
55 * bit 26 - Gpio mode
56 * bit 27 - Sleep mode
57 *
58 * to facilitate the definition, the following macros are provided
59 *
60 * PIN_CFG_DEFAULT - default config (0):
61 * pull up/down = disabled
62 * sleep mode = input/wakeup
63 * direction = input
64 * value = low
65 * SLPM direction = same as normal
66 * SLPM pull = same as normal
67 * SLPM value = same as normal
68 *
69 * PIN_CFG - default config with alternate function
70 */
71
72 typedef unsigned long pin_cfg_t;
73
74 #define PIN_NUM_MASK 0x1ff
75 #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
76
77 #define PIN_ALT_SHIFT 9
78 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
79 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
80 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
81 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
82 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
83 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
84
85 #define PIN_PULL_SHIFT 11
86 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
87 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
88 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
89 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
90 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
91
92 #define PIN_SLPM_SHIFT 13
93 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
94 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
95 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
96 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
97 /* These two replace the above in DB8500v2+ */
98 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
99 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
100 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
101
102 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
103 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
104
105 #define PIN_DIR_SHIFT 14
106 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
107 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
108 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
109 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
110
111 #define PIN_VAL_SHIFT 15
112 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
113 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
114 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
115 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
116
117 #define PIN_SLPM_PULL_SHIFT 16
118 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
119 #define PIN_SLPM_PULL(x) \
120 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
121 #define PIN_SLPM_PULL_NONE \
122 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
123 #define PIN_SLPM_PULL_UP \
124 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
125 #define PIN_SLPM_PULL_DOWN \
126 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
127
128 #define PIN_SLPM_DIR_SHIFT 19
129 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
130 #define PIN_SLPM_DIR(x) \
131 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
132 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
133 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
134
135 #define PIN_SLPM_VAL_SHIFT 21
136 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
137 #define PIN_SLPM_VAL(x) \
138 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
139 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
140 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
141
142 #define PIN_SLPM_PDIS_SHIFT 23
143 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
144 #define PIN_SLPM_PDIS(x) \
145 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
146 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
147 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
148 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
149
150 #define PIN_LOWEMI_SHIFT 25
151 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
152 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
153 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
154 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
155
156 #define PIN_GPIOMODE_SHIFT 26
157 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
158 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
159 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
160 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
161
162 #define PIN_SLEEPMODE_SHIFT 27
163 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
164 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
165 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
166 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
167
168
169 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
170 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
171 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
172 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
173 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
174 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
175
176 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
177 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
178 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
179 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
180 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
181
182 #define PIN_CFG_DEFAULT (0)
183
184 #define PIN_CFG(num, alt) \
185 (PIN_CFG_DEFAULT |\
186 (PIN_NUM(num) | PIN_##alt))
187
188 #define PIN_CFG_INPUT(num, alt, pull) \
189 (PIN_CFG_DEFAULT |\
190 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
191
192 #define PIN_CFG_OUTPUT(num, alt, val) \
193 (PIN_CFG_DEFAULT |\
194 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
195
196 /*
197 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
198 * the "gpio" namespace for generic and cross-machine functions
199 */
200
201 #define GPIO_BLOCK_SHIFT 5
202 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
203 #define NMK_MAX_BANKS DIV_ROUND_UP(512, NMK_GPIO_PER_CHIP)
204
205 /* Register in the logic block */
206 #define NMK_GPIO_DAT 0x00
207 #define NMK_GPIO_DATS 0x04
208 #define NMK_GPIO_DATC 0x08
209 #define NMK_GPIO_PDIS 0x0c
210 #define NMK_GPIO_DIR 0x10
211 #define NMK_GPIO_DIRS 0x14
212 #define NMK_GPIO_DIRC 0x18
213 #define NMK_GPIO_SLPC 0x1c
214 #define NMK_GPIO_AFSLA 0x20
215 #define NMK_GPIO_AFSLB 0x24
216 #define NMK_GPIO_LOWEMI 0x28
217
218 #define NMK_GPIO_RIMSC 0x40
219 #define NMK_GPIO_FIMSC 0x44
220 #define NMK_GPIO_IS 0x48
221 #define NMK_GPIO_IC 0x4c
222 #define NMK_GPIO_RWIMSC 0x50
223 #define NMK_GPIO_FWIMSC 0x54
224 #define NMK_GPIO_WKS 0x58
225 /* These appear in DB8540 and later ASICs */
226 #define NMK_GPIO_EDGELEVEL 0x5C
227 #define NMK_GPIO_LEVEL 0x60
228
229
230 /* Pull up/down values */
231 enum nmk_gpio_pull {
232 NMK_GPIO_PULL_NONE,
233 NMK_GPIO_PULL_UP,
234 NMK_GPIO_PULL_DOWN,
235 };
236
237 /* Sleep mode */
238 enum nmk_gpio_slpm {
239 NMK_GPIO_SLPM_INPUT,
240 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
241 NMK_GPIO_SLPM_NOCHANGE,
242 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
243 };
244
245 struct nmk_gpio_chip {
246 struct gpio_chip chip;
247 void __iomem *addr;
248 struct clk *clk;
249 unsigned int bank;
250 void (*set_ioforce)(bool enable);
251 spinlock_t lock;
252 bool sleepmode;
253 /* Keep track of configured edges */
254 u32 edge_rising;
255 u32 edge_falling;
256 u32 real_wake;
257 u32 rwimsc;
258 u32 fwimsc;
259 u32 rimsc;
260 u32 fimsc;
261 u32 pull_up;
262 u32 lowemi;
263 };
264
265 /**
266 * struct nmk_pinctrl - state container for the Nomadik pin controller
267 * @dev: containing device pointer
268 * @pctl: corresponding pin controller device
269 * @soc: SoC data for this specific chip
270 * @prcm_base: PRCM register range virtual base
271 */
272 struct nmk_pinctrl {
273 struct device *dev;
274 struct pinctrl_dev *pctl;
275 const struct nmk_pinctrl_soc_data *soc;
276 void __iomem *prcm_base;
277 };
278
279 static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
280
281 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
282
283 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
284
__nmk_gpio_set_mode(struct nmk_gpio_chip * nmk_chip,unsigned offset,int gpio_mode)285 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
286 unsigned offset, int gpio_mode)
287 {
288 u32 afunc, bfunc;
289
290 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
291 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
292 if (gpio_mode & NMK_GPIO_ALT_A)
293 afunc |= BIT(offset);
294 if (gpio_mode & NMK_GPIO_ALT_B)
295 bfunc |= BIT(offset);
296 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
297 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
298 }
299
__nmk_gpio_set_slpm(struct nmk_gpio_chip * nmk_chip,unsigned offset,enum nmk_gpio_slpm mode)300 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
301 unsigned offset, enum nmk_gpio_slpm mode)
302 {
303 u32 slpm;
304
305 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
306 if (mode == NMK_GPIO_SLPM_NOCHANGE)
307 slpm |= BIT(offset);
308 else
309 slpm &= ~BIT(offset);
310 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
311 }
312
__nmk_gpio_set_pull(struct nmk_gpio_chip * nmk_chip,unsigned offset,enum nmk_gpio_pull pull)313 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
314 unsigned offset, enum nmk_gpio_pull pull)
315 {
316 u32 pdis;
317
318 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
319 if (pull == NMK_GPIO_PULL_NONE) {
320 pdis |= BIT(offset);
321 nmk_chip->pull_up &= ~BIT(offset);
322 } else {
323 pdis &= ~BIT(offset);
324 }
325
326 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
327
328 if (pull == NMK_GPIO_PULL_UP) {
329 nmk_chip->pull_up |= BIT(offset);
330 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
331 } else if (pull == NMK_GPIO_PULL_DOWN) {
332 nmk_chip->pull_up &= ~BIT(offset);
333 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
334 }
335 }
336
__nmk_gpio_set_lowemi(struct nmk_gpio_chip * nmk_chip,unsigned offset,bool lowemi)337 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
338 unsigned offset, bool lowemi)
339 {
340 bool enabled = nmk_chip->lowemi & BIT(offset);
341
342 if (lowemi == enabled)
343 return;
344
345 if (lowemi)
346 nmk_chip->lowemi |= BIT(offset);
347 else
348 nmk_chip->lowemi &= ~BIT(offset);
349
350 writel_relaxed(nmk_chip->lowemi,
351 nmk_chip->addr + NMK_GPIO_LOWEMI);
352 }
353
__nmk_gpio_make_input(struct nmk_gpio_chip * nmk_chip,unsigned offset)354 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
355 unsigned offset)
356 {
357 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
358 }
359
__nmk_gpio_set_output(struct nmk_gpio_chip * nmk_chip,unsigned offset,int val)360 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
361 unsigned offset, int val)
362 {
363 if (val)
364 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
365 else
366 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
367 }
368
__nmk_gpio_make_output(struct nmk_gpio_chip * nmk_chip,unsigned offset,int val)369 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
370 unsigned offset, int val)
371 {
372 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
373 __nmk_gpio_set_output(nmk_chip, offset, val);
374 }
375
__nmk_gpio_set_mode_safe(struct nmk_gpio_chip * nmk_chip,unsigned offset,int gpio_mode,bool glitch)376 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
377 unsigned offset, int gpio_mode,
378 bool glitch)
379 {
380 u32 rwimsc = nmk_chip->rwimsc;
381 u32 fwimsc = nmk_chip->fwimsc;
382
383 if (glitch && nmk_chip->set_ioforce) {
384 u32 bit = BIT(offset);
385
386 /* Prevent spurious wakeups */
387 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
388 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
389
390 nmk_chip->set_ioforce(true);
391 }
392
393 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
394
395 if (glitch && nmk_chip->set_ioforce) {
396 nmk_chip->set_ioforce(false);
397
398 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
399 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
400 }
401 }
402
403 static void
nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip * nmk_chip,unsigned offset)404 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
405 {
406 u32 falling = nmk_chip->fimsc & BIT(offset);
407 u32 rising = nmk_chip->rimsc & BIT(offset);
408 int gpio = nmk_chip->chip.base + offset;
409 int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
410 struct irq_data *d = irq_get_irq_data(irq);
411
412 if (!rising && !falling)
413 return;
414
415 if (!d || !irqd_irq_disabled(d))
416 return;
417
418 if (rising) {
419 nmk_chip->rimsc &= ~BIT(offset);
420 writel_relaxed(nmk_chip->rimsc,
421 nmk_chip->addr + NMK_GPIO_RIMSC);
422 }
423
424 if (falling) {
425 nmk_chip->fimsc &= ~BIT(offset);
426 writel_relaxed(nmk_chip->fimsc,
427 nmk_chip->addr + NMK_GPIO_FIMSC);
428 }
429
430 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
431 }
432
nmk_write_masked(void __iomem * reg,u32 mask,u32 value)433 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
434 {
435 u32 val;
436
437 val = readl(reg);
438 val = ((val & ~mask) | (value & mask));
439 writel(val, reg);
440 }
441
nmk_prcm_altcx_set_mode(struct nmk_pinctrl * npct,unsigned offset,unsigned alt_num)442 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
443 unsigned offset, unsigned alt_num)
444 {
445 int i;
446 u16 reg;
447 u8 bit;
448 u8 alt_index;
449 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
450 const u16 *gpiocr_regs;
451
452 if (!npct->prcm_base)
453 return;
454
455 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
456 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
457 alt_num);
458 return;
459 }
460
461 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
462 if (npct->soc->altcx_pins[i].pin == offset)
463 break;
464 }
465 if (i == npct->soc->npins_altcx) {
466 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
467 offset);
468 return;
469 }
470
471 pin_desc = npct->soc->altcx_pins + i;
472 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
473
474 /*
475 * If alt_num is NULL, just clear current ALTCx selection
476 * to make sure we come back to a pure ALTC selection
477 */
478 if (!alt_num) {
479 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
480 if (pin_desc->altcx[i].used == true) {
481 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
482 bit = pin_desc->altcx[i].control_bit;
483 if (readl(npct->prcm_base + reg) & BIT(bit)) {
484 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
485 dev_dbg(npct->dev,
486 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
487 offset, i+1);
488 }
489 }
490 }
491 return;
492 }
493
494 alt_index = alt_num - 1;
495 if (pin_desc->altcx[alt_index].used == false) {
496 dev_warn(npct->dev,
497 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
498 offset, alt_num);
499 return;
500 }
501
502 /*
503 * Check if any other ALTCx functions are activated on this pin
504 * and disable it first.
505 */
506 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
507 if (i == alt_index)
508 continue;
509 if (pin_desc->altcx[i].used == true) {
510 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
511 bit = pin_desc->altcx[i].control_bit;
512 if (readl(npct->prcm_base + reg) & BIT(bit)) {
513 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
514 dev_dbg(npct->dev,
515 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
516 offset, i+1);
517 }
518 }
519 }
520
521 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
522 bit = pin_desc->altcx[alt_index].control_bit;
523 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
524 offset, alt_index+1);
525 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
526 }
527
528 /*
529 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
530 * - Save SLPM registers
531 * - Set SLPM=0 for the IOs you want to switch and others to 1
532 * - Configure the GPIO registers for the IOs that are being switched
533 * - Set IOFORCE=1
534 * - Modify the AFLSA/B registers for the IOs that are being switched
535 * - Set IOFORCE=0
536 * - Restore SLPM registers
537 * - Any spurious wake up event during switch sequence to be ignored and
538 * cleared
539 */
nmk_gpio_glitch_slpm_init(unsigned int * slpm)540 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
541 {
542 int i;
543
544 for (i = 0; i < NUM_BANKS; i++) {
545 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
546 unsigned int temp = slpm[i];
547
548 if (!chip)
549 break;
550
551 clk_enable(chip->clk);
552
553 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
554 writel(temp, chip->addr + NMK_GPIO_SLPC);
555 }
556 }
557
nmk_gpio_glitch_slpm_restore(unsigned int * slpm)558 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
559 {
560 int i;
561
562 for (i = 0; i < NUM_BANKS; i++) {
563 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
564
565 if (!chip)
566 break;
567
568 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
569
570 clk_disable(chip->clk);
571 }
572 }
573
nmk_prcm_gpiocr_get_mode(struct pinctrl_dev * pctldev,int gpio)574 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
575 {
576 int i;
577 u16 reg;
578 u8 bit;
579 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
580 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
581 const u16 *gpiocr_regs;
582
583 if (!npct->prcm_base)
584 return NMK_GPIO_ALT_C;
585
586 for (i = 0; i < npct->soc->npins_altcx; i++) {
587 if (npct->soc->altcx_pins[i].pin == gpio)
588 break;
589 }
590 if (i == npct->soc->npins_altcx)
591 return NMK_GPIO_ALT_C;
592
593 pin_desc = npct->soc->altcx_pins + i;
594 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
595 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
596 if (pin_desc->altcx[i].used == true) {
597 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
598 bit = pin_desc->altcx[i].control_bit;
599 if (readl(npct->prcm_base + reg) & BIT(bit))
600 return NMK_GPIO_ALT_C+i+1;
601 }
602 }
603 return NMK_GPIO_ALT_C;
604 }
605
606 /* IRQ functions */
607
nmk_gpio_irq_ack(struct irq_data * d)608 static void nmk_gpio_irq_ack(struct irq_data *d)
609 {
610 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
611 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
612
613 clk_enable(nmk_chip->clk);
614 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
615 clk_disable(nmk_chip->clk);
616 }
617
618 enum nmk_gpio_irq_type {
619 NORMAL,
620 WAKE,
621 };
622
__nmk_gpio_irq_modify(struct nmk_gpio_chip * nmk_chip,int offset,enum nmk_gpio_irq_type which,bool enable)623 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
624 int offset, enum nmk_gpio_irq_type which,
625 bool enable)
626 {
627 u32 *rimscval;
628 u32 *fimscval;
629 u32 rimscreg;
630 u32 fimscreg;
631
632 if (which == NORMAL) {
633 rimscreg = NMK_GPIO_RIMSC;
634 fimscreg = NMK_GPIO_FIMSC;
635 rimscval = &nmk_chip->rimsc;
636 fimscval = &nmk_chip->fimsc;
637 } else {
638 rimscreg = NMK_GPIO_RWIMSC;
639 fimscreg = NMK_GPIO_FWIMSC;
640 rimscval = &nmk_chip->rwimsc;
641 fimscval = &nmk_chip->fwimsc;
642 }
643
644 /* we must individually set/clear the two edges */
645 if (nmk_chip->edge_rising & BIT(offset)) {
646 if (enable)
647 *rimscval |= BIT(offset);
648 else
649 *rimscval &= ~BIT(offset);
650 writel(*rimscval, nmk_chip->addr + rimscreg);
651 }
652 if (nmk_chip->edge_falling & BIT(offset)) {
653 if (enable)
654 *fimscval |= BIT(offset);
655 else
656 *fimscval &= ~BIT(offset);
657 writel(*fimscval, nmk_chip->addr + fimscreg);
658 }
659 }
660
__nmk_gpio_set_wake(struct nmk_gpio_chip * nmk_chip,int offset,bool on)661 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
662 int offset, bool on)
663 {
664 /*
665 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
666 * disabled, since setting SLPM to 1 increases power consumption, and
667 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
668 */
669 if (nmk_chip->sleepmode && on) {
670 __nmk_gpio_set_slpm(nmk_chip, offset,
671 NMK_GPIO_SLPM_WAKEUP_ENABLE);
672 }
673
674 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
675 }
676
nmk_gpio_irq_maskunmask(struct nmk_gpio_chip * nmk_chip,struct irq_data * d,bool enable)677 static void nmk_gpio_irq_maskunmask(struct nmk_gpio_chip *nmk_chip,
678 struct irq_data *d, bool enable)
679 {
680 unsigned long flags;
681
682 clk_enable(nmk_chip->clk);
683 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
684 spin_lock(&nmk_chip->lock);
685
686 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
687
688 if (!(nmk_chip->real_wake & BIT(d->hwirq)))
689 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
690
691 spin_unlock(&nmk_chip->lock);
692 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
693 clk_disable(nmk_chip->clk);
694 }
695
nmk_gpio_irq_mask(struct irq_data * d)696 static void nmk_gpio_irq_mask(struct irq_data *d)
697 {
698 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
699 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
700
701 nmk_gpio_irq_maskunmask(nmk_chip, d, false);
702 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
703 }
704
nmk_gpio_irq_unmask(struct irq_data * d)705 static void nmk_gpio_irq_unmask(struct irq_data *d)
706 {
707 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
708 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
709
710 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
711 nmk_gpio_irq_maskunmask(nmk_chip, d, true);
712 }
713
nmk_gpio_irq_set_wake(struct irq_data * d,unsigned int on)714 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
715 {
716 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
717 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
718 unsigned long flags;
719
720 clk_enable(nmk_chip->clk);
721 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
722 spin_lock(&nmk_chip->lock);
723
724 if (irqd_irq_disabled(d))
725 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
726
727 if (on)
728 nmk_chip->real_wake |= BIT(d->hwirq);
729 else
730 nmk_chip->real_wake &= ~BIT(d->hwirq);
731
732 spin_unlock(&nmk_chip->lock);
733 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
734 clk_disable(nmk_chip->clk);
735
736 return 0;
737 }
738
nmk_gpio_irq_set_type(struct irq_data * d,unsigned int type)739 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
740 {
741 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
742 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
743 bool enabled = !irqd_irq_disabled(d);
744 bool wake = irqd_is_wakeup_set(d);
745 unsigned long flags;
746
747 if (type & IRQ_TYPE_LEVEL_HIGH)
748 return -EINVAL;
749 if (type & IRQ_TYPE_LEVEL_LOW)
750 return -EINVAL;
751
752 clk_enable(nmk_chip->clk);
753 spin_lock_irqsave(&nmk_chip->lock, flags);
754
755 if (enabled)
756 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
757
758 if (enabled || wake)
759 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
760
761 nmk_chip->edge_rising &= ~BIT(d->hwirq);
762 if (type & IRQ_TYPE_EDGE_RISING)
763 nmk_chip->edge_rising |= BIT(d->hwirq);
764
765 nmk_chip->edge_falling &= ~BIT(d->hwirq);
766 if (type & IRQ_TYPE_EDGE_FALLING)
767 nmk_chip->edge_falling |= BIT(d->hwirq);
768
769 if (enabled)
770 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
771
772 if (enabled || wake)
773 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
774
775 spin_unlock_irqrestore(&nmk_chip->lock, flags);
776 clk_disable(nmk_chip->clk);
777
778 return 0;
779 }
780
nmk_gpio_irq_startup(struct irq_data * d)781 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
782 {
783 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
784 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
785
786 clk_enable(nmk_chip->clk);
787 nmk_gpio_irq_unmask(d);
788 return 0;
789 }
790
nmk_gpio_irq_shutdown(struct irq_data * d)791 static void nmk_gpio_irq_shutdown(struct irq_data *d)
792 {
793 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
794 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
795
796 nmk_gpio_irq_mask(d);
797 clk_disable(nmk_chip->clk);
798 }
799
nmk_gpio_irq_handler(struct irq_desc * desc)800 static void nmk_gpio_irq_handler(struct irq_desc *desc)
801 {
802 struct irq_chip *host_chip = irq_desc_get_chip(desc);
803 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
804 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
805 u32 status;
806
807 chained_irq_enter(host_chip, desc);
808
809 clk_enable(nmk_chip->clk);
810 status = readl(nmk_chip->addr + NMK_GPIO_IS);
811 clk_disable(nmk_chip->clk);
812
813 while (status) {
814 int bit = __ffs(status);
815
816 generic_handle_domain_irq(chip->irq.domain, bit);
817 status &= ~BIT(bit);
818 }
819
820 chained_irq_exit(host_chip, desc);
821 }
822
823 /* I/O Functions */
824
nmk_gpio_get_dir(struct gpio_chip * chip,unsigned offset)825 static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset)
826 {
827 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
828 int dir;
829
830 clk_enable(nmk_chip->clk);
831
832 dir = readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset);
833
834 clk_disable(nmk_chip->clk);
835
836 if (dir)
837 return GPIO_LINE_DIRECTION_OUT;
838
839 return GPIO_LINE_DIRECTION_IN;
840 }
841
nmk_gpio_make_input(struct gpio_chip * chip,unsigned offset)842 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
843 {
844 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
845
846 clk_enable(nmk_chip->clk);
847
848 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
849
850 clk_disable(nmk_chip->clk);
851
852 return 0;
853 }
854
nmk_gpio_get_input(struct gpio_chip * chip,unsigned offset)855 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
856 {
857 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
858 int value;
859
860 clk_enable(nmk_chip->clk);
861
862 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
863
864 clk_disable(nmk_chip->clk);
865
866 return value;
867 }
868
nmk_gpio_set_output(struct gpio_chip * chip,unsigned offset,int val)869 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
870 int val)
871 {
872 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
873
874 clk_enable(nmk_chip->clk);
875
876 __nmk_gpio_set_output(nmk_chip, offset, val);
877
878 clk_disable(nmk_chip->clk);
879 }
880
nmk_gpio_make_output(struct gpio_chip * chip,unsigned offset,int val)881 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
882 int val)
883 {
884 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
885
886 clk_enable(nmk_chip->clk);
887
888 __nmk_gpio_make_output(nmk_chip, offset, val);
889
890 clk_disable(nmk_chip->clk);
891
892 return 0;
893 }
894
895 #ifdef CONFIG_DEBUG_FS
nmk_gpio_get_mode(struct nmk_gpio_chip * nmk_chip,int offset)896 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
897 {
898 u32 afunc, bfunc;
899
900 clk_enable(nmk_chip->clk);
901
902 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
903 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
904
905 clk_disable(nmk_chip->clk);
906
907 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
908 }
909
910 #include <linux/seq_file.h>
911
nmk_gpio_dbg_show_one(struct seq_file * s,struct pinctrl_dev * pctldev,struct gpio_chip * chip,unsigned offset,unsigned gpio)912 static void nmk_gpio_dbg_show_one(struct seq_file *s,
913 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
914 unsigned offset, unsigned gpio)
915 {
916 const char *label = gpiochip_is_requested(chip, offset);
917 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
918 int mode;
919 bool is_out;
920 bool data_out;
921 bool pull;
922 const char *modes[] = {
923 [NMK_GPIO_ALT_GPIO] = "gpio",
924 [NMK_GPIO_ALT_A] = "altA",
925 [NMK_GPIO_ALT_B] = "altB",
926 [NMK_GPIO_ALT_C] = "altC",
927 [NMK_GPIO_ALT_C+1] = "altC1",
928 [NMK_GPIO_ALT_C+2] = "altC2",
929 [NMK_GPIO_ALT_C+3] = "altC3",
930 [NMK_GPIO_ALT_C+4] = "altC4",
931 };
932
933 clk_enable(nmk_chip->clk);
934 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
935 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
936 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
937 mode = nmk_gpio_get_mode(nmk_chip, offset);
938 if ((mode == NMK_GPIO_ALT_C) && pctldev)
939 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
940
941 if (is_out) {
942 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
943 gpio,
944 label ?: "(none)",
945 data_out ? "hi" : "lo",
946 (mode < 0) ? "unknown" : modes[mode]);
947 } else {
948 int irq = chip->to_irq(chip, offset);
949 const int pullidx = pull ? 1 : 0;
950 int val;
951 static const char * const pulls[] = {
952 "none ",
953 "pull enabled",
954 };
955
956 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
957 gpio,
958 label ?: "(none)",
959 pulls[pullidx],
960 (mode < 0) ? "unknown" : modes[mode]);
961
962 val = nmk_gpio_get_input(chip, offset);
963 seq_printf(s, " VAL %d", val);
964
965 /*
966 * This races with request_irq(), set_irq_type(),
967 * and set_irq_wake() ... but those are "rare".
968 */
969 if (irq > 0 && irq_has_action(irq)) {
970 char *trigger;
971 bool wake;
972
973 if (nmk_chip->edge_rising & BIT(offset))
974 trigger = "edge-rising";
975 else if (nmk_chip->edge_falling & BIT(offset))
976 trigger = "edge-falling";
977 else
978 trigger = "edge-undefined";
979
980 wake = !!(nmk_chip->real_wake & BIT(offset));
981
982 seq_printf(s, " irq-%d %s%s",
983 irq, trigger, wake ? " wakeup" : "");
984 }
985 }
986 clk_disable(nmk_chip->clk);
987 }
988
nmk_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)989 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
990 {
991 unsigned i;
992 unsigned gpio = chip->base;
993
994 for (i = 0; i < chip->ngpio; i++, gpio++) {
995 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
996 seq_printf(s, "\n");
997 }
998 }
999
1000 #else
nmk_gpio_dbg_show_one(struct seq_file * s,struct pinctrl_dev * pctldev,struct gpio_chip * chip,unsigned offset,unsigned gpio)1001 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1002 struct pinctrl_dev *pctldev,
1003 struct gpio_chip *chip,
1004 unsigned offset, unsigned gpio)
1005 {
1006 }
1007 #define nmk_gpio_dbg_show NULL
1008 #endif
1009
1010 /*
1011 * We will allocate memory for the state container using devm* allocators
1012 * binding to the first device reaching this point, it doesn't matter if
1013 * it is the pin controller or GPIO driver. However we need to use the right
1014 * platform device when looking up resources so pay attention to pdev.
1015 */
nmk_gpio_populate_chip(struct device_node * np,struct platform_device * pdev)1016 static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
1017 struct platform_device *pdev)
1018 {
1019 struct nmk_gpio_chip *nmk_chip;
1020 struct platform_device *gpio_pdev;
1021 struct gpio_chip *chip;
1022 struct resource *res;
1023 struct clk *clk;
1024 void __iomem *base;
1025 u32 id;
1026
1027 gpio_pdev = of_find_device_by_node(np);
1028 if (!gpio_pdev) {
1029 pr_err("populate \"%pOFn\": device not found\n", np);
1030 return ERR_PTR(-ENODEV);
1031 }
1032 if (of_property_read_u32(np, "gpio-bank", &id)) {
1033 dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
1034 platform_device_put(gpio_pdev);
1035 return ERR_PTR(-EINVAL);
1036 }
1037
1038 /* Already populated? */
1039 nmk_chip = nmk_gpio_chips[id];
1040 if (nmk_chip) {
1041 platform_device_put(gpio_pdev);
1042 return nmk_chip;
1043 }
1044
1045 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1046 if (!nmk_chip) {
1047 platform_device_put(gpio_pdev);
1048 return ERR_PTR(-ENOMEM);
1049 }
1050
1051 nmk_chip->bank = id;
1052 chip = &nmk_chip->chip;
1053 chip->base = id * NMK_GPIO_PER_CHIP;
1054 chip->ngpio = NMK_GPIO_PER_CHIP;
1055 chip->label = dev_name(&gpio_pdev->dev);
1056 chip->parent = &gpio_pdev->dev;
1057
1058 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
1059 base = devm_ioremap_resource(&pdev->dev, res);
1060 if (IS_ERR(base)) {
1061 platform_device_put(gpio_pdev);
1062 return ERR_CAST(base);
1063 }
1064 nmk_chip->addr = base;
1065
1066 clk = clk_get(&gpio_pdev->dev, NULL);
1067 if (IS_ERR(clk)) {
1068 platform_device_put(gpio_pdev);
1069 return (void *) clk;
1070 }
1071 clk_prepare(clk);
1072 nmk_chip->clk = clk;
1073
1074 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1075 nmk_gpio_chips[id] = nmk_chip;
1076 return nmk_chip;
1077 }
1078
nmk_gpio_irq_print_chip(struct irq_data * d,struct seq_file * p)1079 static void nmk_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p)
1080 {
1081 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1082 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc);
1083
1084 seq_printf(p, "nmk%u-%u-%u", nmk_chip->bank,
1085 gc->base, gc->base + gc->ngpio - 1);
1086 }
1087
1088 static const struct irq_chip nmk_irq_chip = {
1089 .irq_ack = nmk_gpio_irq_ack,
1090 .irq_mask = nmk_gpio_irq_mask,
1091 .irq_unmask = nmk_gpio_irq_unmask,
1092 .irq_set_type = nmk_gpio_irq_set_type,
1093 .irq_set_wake = nmk_gpio_irq_set_wake,
1094 .irq_startup = nmk_gpio_irq_startup,
1095 .irq_shutdown = nmk_gpio_irq_shutdown,
1096 .irq_print_chip = nmk_gpio_irq_print_chip,
1097 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
1098 GPIOCHIP_IRQ_RESOURCE_HELPERS,
1099 };
1100
nmk_gpio_probe(struct platform_device * dev)1101 static int nmk_gpio_probe(struct platform_device *dev)
1102 {
1103 struct device_node *np = dev->dev.of_node;
1104 struct nmk_gpio_chip *nmk_chip;
1105 struct gpio_chip *chip;
1106 struct gpio_irq_chip *girq;
1107 bool supports_sleepmode;
1108 int irq;
1109 int ret;
1110
1111 nmk_chip = nmk_gpio_populate_chip(np, dev);
1112 if (IS_ERR(nmk_chip)) {
1113 dev_err(&dev->dev, "could not populate nmk chip struct\n");
1114 return PTR_ERR(nmk_chip);
1115 }
1116
1117 supports_sleepmode =
1118 of_property_read_bool(np, "st,supports-sleepmode");
1119
1120 /* Correct platform device ID */
1121 dev->id = nmk_chip->bank;
1122
1123 irq = platform_get_irq(dev, 0);
1124 if (irq < 0)
1125 return irq;
1126
1127 /*
1128 * The virt address in nmk_chip->addr is in the nomadik register space,
1129 * so we can simply convert the resource address, without remapping
1130 */
1131 nmk_chip->sleepmode = supports_sleepmode;
1132 spin_lock_init(&nmk_chip->lock);
1133
1134 chip = &nmk_chip->chip;
1135 chip->parent = &dev->dev;
1136 chip->request = gpiochip_generic_request;
1137 chip->free = gpiochip_generic_free;
1138 chip->get_direction = nmk_gpio_get_dir;
1139 chip->direction_input = nmk_gpio_make_input;
1140 chip->get = nmk_gpio_get_input;
1141 chip->direction_output = nmk_gpio_make_output;
1142 chip->set = nmk_gpio_set_output;
1143 chip->dbg_show = nmk_gpio_dbg_show;
1144 chip->can_sleep = false;
1145 chip->owner = THIS_MODULE;
1146
1147 girq = &chip->irq;
1148 gpio_irq_chip_set_chip(girq, &nmk_irq_chip);
1149 girq->parent_handler = nmk_gpio_irq_handler;
1150 girq->num_parents = 1;
1151 girq->parents = devm_kcalloc(&dev->dev, 1,
1152 sizeof(*girq->parents),
1153 GFP_KERNEL);
1154 if (!girq->parents)
1155 return -ENOMEM;
1156 girq->parents[0] = irq;
1157 girq->default_type = IRQ_TYPE_NONE;
1158 girq->handler = handle_edge_irq;
1159
1160 clk_enable(nmk_chip->clk);
1161 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1162 clk_disable(nmk_chip->clk);
1163
1164 ret = gpiochip_add_data(chip, nmk_chip);
1165 if (ret)
1166 return ret;
1167
1168 platform_set_drvdata(dev, nmk_chip);
1169
1170 dev_info(&dev->dev, "chip registered\n");
1171
1172 return 0;
1173 }
1174
nmk_get_groups_cnt(struct pinctrl_dev * pctldev)1175 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1176 {
1177 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1178
1179 return npct->soc->ngroups;
1180 }
1181
nmk_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)1182 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1183 unsigned selector)
1184 {
1185 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1186
1187 return npct->soc->groups[selector].grp.name;
1188 }
1189
nmk_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * npins)1190 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1191 const unsigned **pins,
1192 unsigned *npins)
1193 {
1194 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1195
1196 *pins = npct->soc->groups[selector].grp.pins;
1197 *npins = npct->soc->groups[selector].grp.npins;
1198 return 0;
1199 }
1200
find_nmk_gpio_from_pin(unsigned pin)1201 static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin)
1202 {
1203 int i;
1204 struct nmk_gpio_chip *nmk_gpio;
1205
1206 for(i = 0; i < NMK_MAX_BANKS; i++) {
1207 nmk_gpio = nmk_gpio_chips[i];
1208 if (!nmk_gpio)
1209 continue;
1210 if (pin >= nmk_gpio->chip.base &&
1211 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio)
1212 return nmk_gpio;
1213 }
1214 return NULL;
1215 }
1216
find_gc_from_pin(unsigned pin)1217 static struct gpio_chip *find_gc_from_pin(unsigned pin)
1218 {
1219 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin);
1220
1221 if (nmk_gpio)
1222 return &nmk_gpio->chip;
1223 return NULL;
1224 }
1225
nmk_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned offset)1226 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1227 unsigned offset)
1228 {
1229 struct gpio_chip *chip = find_gc_from_pin(offset);
1230
1231 if (!chip) {
1232 seq_printf(s, "invalid pin offset");
1233 return;
1234 }
1235 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1236 }
1237
nmk_dt_add_map_mux(struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps,const char * group,const char * function)1238 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1239 unsigned *num_maps, const char *group,
1240 const char *function)
1241 {
1242 if (*num_maps == *reserved_maps)
1243 return -ENOSPC;
1244
1245 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1246 (*map)[*num_maps].data.mux.group = group;
1247 (*map)[*num_maps].data.mux.function = function;
1248 (*num_maps)++;
1249
1250 return 0;
1251 }
1252
nmk_dt_add_map_configs(struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps,const char * group,unsigned long * configs,unsigned num_configs)1253 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1254 unsigned *reserved_maps,
1255 unsigned *num_maps, const char *group,
1256 unsigned long *configs, unsigned num_configs)
1257 {
1258 unsigned long *dup_configs;
1259
1260 if (*num_maps == *reserved_maps)
1261 return -ENOSPC;
1262
1263 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1264 GFP_KERNEL);
1265 if (!dup_configs)
1266 return -ENOMEM;
1267
1268 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1269
1270 (*map)[*num_maps].data.configs.group_or_pin = group;
1271 (*map)[*num_maps].data.configs.configs = dup_configs;
1272 (*map)[*num_maps].data.configs.num_configs = num_configs;
1273 (*num_maps)++;
1274
1275 return 0;
1276 }
1277
1278 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1279 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1280 .size = ARRAY_SIZE(y), }
1281
1282 static const unsigned long nmk_pin_input_modes[] = {
1283 PIN_INPUT_NOPULL,
1284 PIN_INPUT_PULLUP,
1285 PIN_INPUT_PULLDOWN,
1286 };
1287
1288 static const unsigned long nmk_pin_output_modes[] = {
1289 PIN_OUTPUT_LOW,
1290 PIN_OUTPUT_HIGH,
1291 PIN_DIR_OUTPUT,
1292 };
1293
1294 static const unsigned long nmk_pin_sleep_modes[] = {
1295 PIN_SLEEPMODE_DISABLED,
1296 PIN_SLEEPMODE_ENABLED,
1297 };
1298
1299 static const unsigned long nmk_pin_sleep_input_modes[] = {
1300 PIN_SLPM_INPUT_NOPULL,
1301 PIN_SLPM_INPUT_PULLUP,
1302 PIN_SLPM_INPUT_PULLDOWN,
1303 PIN_SLPM_DIR_INPUT,
1304 };
1305
1306 static const unsigned long nmk_pin_sleep_output_modes[] = {
1307 PIN_SLPM_OUTPUT_LOW,
1308 PIN_SLPM_OUTPUT_HIGH,
1309 PIN_SLPM_DIR_OUTPUT,
1310 };
1311
1312 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1313 PIN_SLPM_WAKEUP_DISABLE,
1314 PIN_SLPM_WAKEUP_ENABLE,
1315 };
1316
1317 static const unsigned long nmk_pin_gpio_modes[] = {
1318 PIN_GPIOMODE_DISABLED,
1319 PIN_GPIOMODE_ENABLED,
1320 };
1321
1322 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1323 PIN_SLPM_PDIS_DISABLED,
1324 PIN_SLPM_PDIS_ENABLED,
1325 };
1326
1327 struct nmk_cfg_param {
1328 const char *property;
1329 unsigned long config;
1330 const unsigned long *choice;
1331 int size;
1332 };
1333
1334 static const struct nmk_cfg_param nmk_cfg_params[] = {
1335 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1336 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1337 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1338 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1339 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1340 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1341 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1342 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1343 };
1344
nmk_dt_pin_config(int index,int val,unsigned long * config)1345 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1346 {
1347 if (nmk_cfg_params[index].choice == NULL)
1348 *config = nmk_cfg_params[index].config;
1349 else {
1350 /* test if out of range */
1351 if (val < nmk_cfg_params[index].size) {
1352 *config = nmk_cfg_params[index].config |
1353 nmk_cfg_params[index].choice[val];
1354 }
1355 }
1356 return 0;
1357 }
1358
nmk_find_pin_name(struct pinctrl_dev * pctldev,const char * pin_name)1359 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1360 {
1361 int i, pin_number;
1362 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1363
1364 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1365 for (i = 0; i < npct->soc->npins; i++)
1366 if (npct->soc->pins[i].number == pin_number)
1367 return npct->soc->pins[i].name;
1368 return NULL;
1369 }
1370
nmk_pinctrl_dt_get_config(struct device_node * np,unsigned long * configs)1371 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1372 unsigned long *configs)
1373 {
1374 bool has_config = 0;
1375 unsigned long cfg = 0;
1376 int i, val, ret;
1377
1378 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1379 ret = of_property_read_u32(np,
1380 nmk_cfg_params[i].property, &val);
1381 if (ret != -EINVAL) {
1382 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1383 *configs |= cfg;
1384 has_config = 1;
1385 }
1386 }
1387 }
1388
1389 return has_config;
1390 }
1391
nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps)1392 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1393 struct device_node *np,
1394 struct pinctrl_map **map,
1395 unsigned *reserved_maps,
1396 unsigned *num_maps)
1397 {
1398 int ret;
1399 const char *function = NULL;
1400 unsigned long configs = 0;
1401 bool has_config = 0;
1402 struct property *prop;
1403 struct device_node *np_config;
1404
1405 ret = of_property_read_string(np, "function", &function);
1406 if (ret >= 0) {
1407 const char *group;
1408
1409 ret = of_property_count_strings(np, "groups");
1410 if (ret < 0)
1411 goto exit;
1412
1413 ret = pinctrl_utils_reserve_map(pctldev, map,
1414 reserved_maps,
1415 num_maps, ret);
1416 if (ret < 0)
1417 goto exit;
1418
1419 of_property_for_each_string(np, "groups", prop, group) {
1420 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1421 group, function);
1422 if (ret < 0)
1423 goto exit;
1424 }
1425 }
1426
1427 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1428 np_config = of_parse_phandle(np, "ste,config", 0);
1429 if (np_config) {
1430 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1431 of_node_put(np_config);
1432 }
1433 if (has_config) {
1434 const char *gpio_name;
1435 const char *pin;
1436
1437 ret = of_property_count_strings(np, "pins");
1438 if (ret < 0)
1439 goto exit;
1440 ret = pinctrl_utils_reserve_map(pctldev, map,
1441 reserved_maps,
1442 num_maps, ret);
1443 if (ret < 0)
1444 goto exit;
1445
1446 of_property_for_each_string(np, "pins", prop, pin) {
1447 gpio_name = nmk_find_pin_name(pctldev, pin);
1448
1449 ret = nmk_dt_add_map_configs(map, reserved_maps,
1450 num_maps,
1451 gpio_name, &configs, 1);
1452 if (ret < 0)
1453 goto exit;
1454 }
1455 }
1456
1457 exit:
1458 return ret;
1459 }
1460
nmk_pinctrl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np_config,struct pinctrl_map ** map,unsigned * num_maps)1461 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1462 struct device_node *np_config,
1463 struct pinctrl_map **map, unsigned *num_maps)
1464 {
1465 unsigned reserved_maps;
1466 struct device_node *np;
1467 int ret;
1468
1469 reserved_maps = 0;
1470 *map = NULL;
1471 *num_maps = 0;
1472
1473 for_each_child_of_node(np_config, np) {
1474 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1475 &reserved_maps, num_maps);
1476 if (ret < 0) {
1477 pinctrl_utils_free_map(pctldev, *map, *num_maps);
1478 of_node_put(np);
1479 return ret;
1480 }
1481 }
1482
1483 return 0;
1484 }
1485
1486 static const struct pinctrl_ops nmk_pinctrl_ops = {
1487 .get_groups_count = nmk_get_groups_cnt,
1488 .get_group_name = nmk_get_group_name,
1489 .get_group_pins = nmk_get_group_pins,
1490 .pin_dbg_show = nmk_pin_dbg_show,
1491 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1492 .dt_free_map = pinctrl_utils_free_map,
1493 };
1494
nmk_pmx_get_funcs_cnt(struct pinctrl_dev * pctldev)1495 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1496 {
1497 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1498
1499 return npct->soc->nfunctions;
1500 }
1501
nmk_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned function)1502 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1503 unsigned function)
1504 {
1505 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1506
1507 return npct->soc->functions[function].name;
1508 }
1509
nmk_pmx_get_func_groups(struct pinctrl_dev * pctldev,unsigned function,const char * const ** groups,unsigned * const num_groups)1510 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1511 unsigned function,
1512 const char * const **groups,
1513 unsigned * const num_groups)
1514 {
1515 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1516
1517 *groups = npct->soc->functions[function].groups;
1518 *num_groups = npct->soc->functions[function].ngroups;
1519
1520 return 0;
1521 }
1522
nmk_pmx_set(struct pinctrl_dev * pctldev,unsigned function,unsigned group)1523 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1524 unsigned group)
1525 {
1526 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1527 const struct nmk_pingroup *g;
1528 static unsigned int slpm[NUM_BANKS];
1529 unsigned long flags = 0;
1530 bool glitch;
1531 int ret = -EINVAL;
1532 int i;
1533
1534 g = &npct->soc->groups[group];
1535
1536 if (g->altsetting < 0)
1537 return -EINVAL;
1538
1539 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->grp.name, g->grp.npins);
1540
1541 /*
1542 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1543 * we may pass through an undesired state. In this case we take
1544 * some extra care.
1545 *
1546 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1547 * - Save SLPM registers (since we have a shadow register in the
1548 * nmk_chip we're using that as backup)
1549 * - Set SLPM=0 for the IOs you want to switch and others to 1
1550 * - Configure the GPIO registers for the IOs that are being switched
1551 * - Set IOFORCE=1
1552 * - Modify the AFLSA/B registers for the IOs that are being switched
1553 * - Set IOFORCE=0
1554 * - Restore SLPM registers
1555 * - Any spurious wake up event during switch sequence to be ignored
1556 * and cleared
1557 *
1558 * We REALLY need to save ALL slpm registers, because the external
1559 * IOFORCE will switch *all* ports to their sleepmode setting to as
1560 * to avoid glitches. (Not just one port!)
1561 */
1562 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1563
1564 if (glitch) {
1565 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1566
1567 /* Initially don't put any pins to sleep when switching */
1568 memset(slpm, 0xff, sizeof(slpm));
1569
1570 /*
1571 * Then mask the pins that need to be sleeping now when we're
1572 * switching to the ALT C function.
1573 */
1574 for (i = 0; i < g->grp.npins; i++)
1575 slpm[g->grp.pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->grp.pins[i]);
1576 nmk_gpio_glitch_slpm_init(slpm);
1577 }
1578
1579 for (i = 0; i < g->grp.npins; i++) {
1580 struct nmk_gpio_chip *nmk_chip;
1581 unsigned bit;
1582
1583 nmk_chip = find_nmk_gpio_from_pin(g->grp.pins[i]);
1584 if (!nmk_chip) {
1585 dev_err(npct->dev,
1586 "invalid pin offset %d in group %s at index %d\n",
1587 g->grp.pins[i], g->grp.name, i);
1588 goto out_glitch;
1589 }
1590 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->grp.pins[i], g->altsetting);
1591
1592 clk_enable(nmk_chip->clk);
1593 bit = g->grp.pins[i] % NMK_GPIO_PER_CHIP;
1594 /*
1595 * If the pin is switching to altfunc, and there was an
1596 * interrupt installed on it which has been lazy disabled,
1597 * actually mask the interrupt to prevent spurious interrupts
1598 * that would occur while the pin is under control of the
1599 * peripheral. Only SKE does this.
1600 */
1601 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1602
1603 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1604 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1605 clk_disable(nmk_chip->clk);
1606
1607 /*
1608 * Call PRCM GPIOCR config function in case ALTC
1609 * has been selected:
1610 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1611 * must be set.
1612 * - If selection is pure ALTC and previous selection was ALTCx,
1613 * then some bits in PRCM GPIOCR registers must be cleared.
1614 */
1615 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1616 nmk_prcm_altcx_set_mode(npct, g->grp.pins[i],
1617 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1618 }
1619
1620 /* When all pins are successfully reconfigured we get here */
1621 ret = 0;
1622
1623 out_glitch:
1624 if (glitch) {
1625 nmk_gpio_glitch_slpm_restore(slpm);
1626 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1627 }
1628
1629 return ret;
1630 }
1631
nmk_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)1632 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1633 struct pinctrl_gpio_range *range,
1634 unsigned offset)
1635 {
1636 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1637 struct nmk_gpio_chip *nmk_chip;
1638 struct gpio_chip *chip;
1639 unsigned bit;
1640
1641 if (!range) {
1642 dev_err(npct->dev, "invalid range\n");
1643 return -EINVAL;
1644 }
1645 if (!range->gc) {
1646 dev_err(npct->dev, "missing GPIO chip in range\n");
1647 return -EINVAL;
1648 }
1649 chip = range->gc;
1650 nmk_chip = gpiochip_get_data(chip);
1651
1652 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1653
1654 clk_enable(nmk_chip->clk);
1655 bit = offset % NMK_GPIO_PER_CHIP;
1656 /* There is no glitch when converting any pin to GPIO */
1657 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1658 clk_disable(nmk_chip->clk);
1659
1660 return 0;
1661 }
1662
nmk_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)1663 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1664 struct pinctrl_gpio_range *range,
1665 unsigned offset)
1666 {
1667 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1668
1669 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1670 /* Set the pin to some default state, GPIO is usually default */
1671 }
1672
1673 static const struct pinmux_ops nmk_pinmux_ops = {
1674 .get_functions_count = nmk_pmx_get_funcs_cnt,
1675 .get_function_name = nmk_pmx_get_func_name,
1676 .get_function_groups = nmk_pmx_get_func_groups,
1677 .set_mux = nmk_pmx_set,
1678 .gpio_request_enable = nmk_gpio_request_enable,
1679 .gpio_disable_free = nmk_gpio_disable_free,
1680 .strict = true,
1681 };
1682
nmk_pin_config_get(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * config)1683 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1684 unsigned long *config)
1685 {
1686 /* Not implemented */
1687 return -EINVAL;
1688 }
1689
nmk_pin_config_set(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * configs,unsigned num_configs)1690 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1691 unsigned long *configs, unsigned num_configs)
1692 {
1693 static const char *pullnames[] = {
1694 [NMK_GPIO_PULL_NONE] = "none",
1695 [NMK_GPIO_PULL_UP] = "up",
1696 [NMK_GPIO_PULL_DOWN] = "down",
1697 [3] /* illegal */ = "??"
1698 };
1699 static const char *slpmnames[] = {
1700 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1701 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1702 };
1703 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1704 struct nmk_gpio_chip *nmk_chip;
1705 unsigned bit;
1706 pin_cfg_t cfg;
1707 int pull, slpm, output, val, i;
1708 bool lowemi, gpiomode, sleep;
1709
1710 nmk_chip = find_nmk_gpio_from_pin(pin);
1711 if (!nmk_chip) {
1712 dev_err(npct->dev,
1713 "invalid pin offset %d\n", pin);
1714 return -EINVAL;
1715 }
1716
1717 for (i = 0; i < num_configs; i++) {
1718 /*
1719 * The pin config contains pin number and altfunction fields,
1720 * here we just ignore that part. It's being handled by the
1721 * framework and pinmux callback respectively.
1722 */
1723 cfg = (pin_cfg_t) configs[i];
1724 pull = PIN_PULL(cfg);
1725 slpm = PIN_SLPM(cfg);
1726 output = PIN_DIR(cfg);
1727 val = PIN_VAL(cfg);
1728 lowemi = PIN_LOWEMI(cfg);
1729 gpiomode = PIN_GPIOMODE(cfg);
1730 sleep = PIN_SLEEPMODE(cfg);
1731
1732 if (sleep) {
1733 int slpm_pull = PIN_SLPM_PULL(cfg);
1734 int slpm_output = PIN_SLPM_DIR(cfg);
1735 int slpm_val = PIN_SLPM_VAL(cfg);
1736
1737 /* All pins go into GPIO mode at sleep */
1738 gpiomode = true;
1739
1740 /*
1741 * The SLPM_* values are normal values + 1 to allow zero
1742 * to mean "same as normal".
1743 */
1744 if (slpm_pull)
1745 pull = slpm_pull - 1;
1746 if (slpm_output)
1747 output = slpm_output - 1;
1748 if (slpm_val)
1749 val = slpm_val - 1;
1750
1751 dev_dbg(nmk_chip->chip.parent,
1752 "pin %d: sleep pull %s, dir %s, val %s\n",
1753 pin,
1754 slpm_pull ? pullnames[pull] : "same",
1755 slpm_output ? (output ? "output" : "input")
1756 : "same",
1757 slpm_val ? (val ? "high" : "low") : "same");
1758 }
1759
1760 dev_dbg(nmk_chip->chip.parent,
1761 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1762 pin, cfg, pullnames[pull], slpmnames[slpm],
1763 output ? "output " : "input",
1764 output ? (val ? "high" : "low") : "",
1765 lowemi ? "on" : "off");
1766
1767 clk_enable(nmk_chip->clk);
1768 bit = pin % NMK_GPIO_PER_CHIP;
1769 if (gpiomode)
1770 /* No glitch when going to GPIO mode */
1771 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1772 if (output)
1773 __nmk_gpio_make_output(nmk_chip, bit, val);
1774 else {
1775 __nmk_gpio_make_input(nmk_chip, bit);
1776 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1777 }
1778 /* TODO: isn't this only applicable on output pins? */
1779 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1780
1781 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1782 clk_disable(nmk_chip->clk);
1783 } /* for each config */
1784
1785 return 0;
1786 }
1787
1788 static const struct pinconf_ops nmk_pinconf_ops = {
1789 .pin_config_get = nmk_pin_config_get,
1790 .pin_config_set = nmk_pin_config_set,
1791 };
1792
1793 static struct pinctrl_desc nmk_pinctrl_desc = {
1794 .name = "pinctrl-nomadik",
1795 .pctlops = &nmk_pinctrl_ops,
1796 .pmxops = &nmk_pinmux_ops,
1797 .confops = &nmk_pinconf_ops,
1798 .owner = THIS_MODULE,
1799 };
1800
1801 static const struct of_device_id nmk_pinctrl_match[] = {
1802 {
1803 .compatible = "stericsson,stn8815-pinctrl",
1804 .data = (void *)PINCTRL_NMK_STN8815,
1805 },
1806 {
1807 .compatible = "stericsson,db8500-pinctrl",
1808 .data = (void *)PINCTRL_NMK_DB8500,
1809 },
1810 {},
1811 };
1812
1813 #ifdef CONFIG_PM_SLEEP
nmk_pinctrl_suspend(struct device * dev)1814 static int nmk_pinctrl_suspend(struct device *dev)
1815 {
1816 struct nmk_pinctrl *npct;
1817
1818 npct = dev_get_drvdata(dev);
1819 if (!npct)
1820 return -EINVAL;
1821
1822 return pinctrl_force_sleep(npct->pctl);
1823 }
1824
nmk_pinctrl_resume(struct device * dev)1825 static int nmk_pinctrl_resume(struct device *dev)
1826 {
1827 struct nmk_pinctrl *npct;
1828
1829 npct = dev_get_drvdata(dev);
1830 if (!npct)
1831 return -EINVAL;
1832
1833 return pinctrl_force_default(npct->pctl);
1834 }
1835 #endif
1836
nmk_pinctrl_probe(struct platform_device * pdev)1837 static int nmk_pinctrl_probe(struct platform_device *pdev)
1838 {
1839 const struct of_device_id *match;
1840 struct device_node *np = pdev->dev.of_node;
1841 struct device_node *prcm_np;
1842 struct nmk_pinctrl *npct;
1843 unsigned int version = 0;
1844 int i;
1845
1846 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1847 if (!npct)
1848 return -ENOMEM;
1849
1850 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1851 if (!match)
1852 return -ENODEV;
1853 version = (unsigned int) match->data;
1854
1855 /* Poke in other ASIC variants here */
1856 if (version == PINCTRL_NMK_STN8815)
1857 nmk_pinctrl_stn8815_init(&npct->soc);
1858 if (version == PINCTRL_NMK_DB8500)
1859 nmk_pinctrl_db8500_init(&npct->soc);
1860
1861 /*
1862 * Since we depend on the GPIO chips to provide clock and register base
1863 * for the pin control operations, make sure that we have these
1864 * populated before we continue. Follow the phandles to instantiate
1865 * them. The GPIO portion of the actual hardware may be probed before
1866 * or after this point: it shouldn't matter as the APIs are orthogonal.
1867 */
1868 for (i = 0; i < NMK_MAX_BANKS; i++) {
1869 struct device_node *gpio_np;
1870 struct nmk_gpio_chip *nmk_chip;
1871
1872 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i);
1873 if (gpio_np) {
1874 dev_info(&pdev->dev,
1875 "populate NMK GPIO %d \"%pOFn\"\n",
1876 i, gpio_np);
1877 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
1878 if (IS_ERR(nmk_chip))
1879 dev_err(&pdev->dev,
1880 "could not populate nmk chip struct "
1881 "- continue anyway\n");
1882 of_node_put(gpio_np);
1883 }
1884 }
1885
1886 prcm_np = of_parse_phandle(np, "prcm", 0);
1887 if (prcm_np) {
1888 npct->prcm_base = of_iomap(prcm_np, 0);
1889 of_node_put(prcm_np);
1890 }
1891 if (!npct->prcm_base) {
1892 if (version == PINCTRL_NMK_STN8815) {
1893 dev_info(&pdev->dev,
1894 "No PRCM base, "
1895 "assuming no ALT-Cx control is available\n");
1896 } else {
1897 dev_err(&pdev->dev, "missing PRCM base address\n");
1898 return -EINVAL;
1899 }
1900 }
1901
1902 nmk_pinctrl_desc.pins = npct->soc->pins;
1903 nmk_pinctrl_desc.npins = npct->soc->npins;
1904 npct->dev = &pdev->dev;
1905
1906 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);
1907 if (IS_ERR(npct->pctl)) {
1908 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1909 return PTR_ERR(npct->pctl);
1910 }
1911
1912 platform_set_drvdata(pdev, npct);
1913 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1914
1915 return 0;
1916 }
1917
1918 static const struct of_device_id nmk_gpio_match[] = {
1919 { .compatible = "st,nomadik-gpio", },
1920 {}
1921 };
1922
1923 static struct platform_driver nmk_gpio_driver = {
1924 .driver = {
1925 .name = "gpio",
1926 .of_match_table = nmk_gpio_match,
1927 },
1928 .probe = nmk_gpio_probe,
1929 };
1930
1931 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
1932 nmk_pinctrl_suspend,
1933 nmk_pinctrl_resume);
1934
1935 static struct platform_driver nmk_pinctrl_driver = {
1936 .driver = {
1937 .name = "pinctrl-nomadik",
1938 .of_match_table = nmk_pinctrl_match,
1939 .pm = &nmk_pinctrl_pm_ops,
1940 },
1941 .probe = nmk_pinctrl_probe,
1942 };
1943
nmk_gpio_init(void)1944 static int __init nmk_gpio_init(void)
1945 {
1946 return platform_driver_register(&nmk_gpio_driver);
1947 }
1948 subsys_initcall(nmk_gpio_init);
1949
nmk_pinctrl_init(void)1950 static int __init nmk_pinctrl_init(void)
1951 {
1952 return platform_driver_register(&nmk_pinctrl_driver);
1953 }
1954 core_initcall(nmk_pinctrl_init);
1955