Searched refs:PHYRegDef (Results 1 – 12 of 12) sorted by relevance
131 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath]; in rtl8192_phy_RFSerialRead()215 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath]; in rtl8192_phy_RFSerialWrite()549 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; in rtl8192_InitBBRFRegDef()551 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; in rtl8192_InitBBRFRegDef()553 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; in rtl8192_InitBBRFRegDef()555 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; in rtl8192_InitBBRFRegDef()559 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; in rtl8192_InitBBRFRegDef()561 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; in rtl8192_InitBBRFRegDef()563 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; in rtl8192_InitBBRFRegDef()565 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; in rtl8192_InitBBRFRegDef()[all …]
128 pPhyReg = &priv->PHYRegDef[eRFPath]; in phy_rf8256_config_para_file()
933 BB_REGISTER_DEFINITION_T PHYRegDef[4]; /* Radio A/B/C/D */ member
97 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; in _rtl92e_phy_rf_read()152 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; in _rtl92e_phy_rf_write()364 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; in _rtl92e_init_bb_rf_reg_def()365 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; in _rtl92e_init_bb_rf_reg_def()366 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; in _rtl92e_init_bb_rf_reg_def()367 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; in _rtl92e_init_bb_rf_reg_def()369 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; in _rtl92e_init_bb_rf_reg_def()370 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; in _rtl92e_init_bb_rf_reg_def()371 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; in _rtl92e_init_bb_rf_reg_def()372 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; in _rtl92e_init_bb_rf_reg_def()[all …]
73 pPhyReg = &priv->PHYRegDef[eRFPath]; in rtl92e_config_rf()
341 struct bb_reg_definition PHYRegDef[4]; member
120 struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef; in phy_RFSerialRead()212 struct bb_reg_def *pPhyReg = &pHalData->PHYRegDef; in phy_RFSerialWrite()355 pHalData->PHYRegDef.rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */ in phy_InitBBRFRegisterDefinition()358 pHalData->PHYRegDef.rfintfi = rFPGA0_XAB_RFInterfaceRB; /* 16 LSBs if read 32-bit from 0x8E0 */ in phy_InitBBRFRegisterDefinition()361 pHalData->PHYRegDef.rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */ in phy_InitBBRFRegisterDefinition()364 …pHalData->PHYRegDef.rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-b… in phy_InitBBRFRegisterDefinition()367 pHalData->PHYRegDef.rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */ in phy_InitBBRFRegisterDefinition()370 pHalData->PHYRegDef.rfLSSI_Select = rFPGA0_XAB_RFParameter; /* BB Band Select */ in phy_InitBBRFRegisterDefinition()373 pHalData->PHYRegDef.rfTxGainStage = rFPGA0_TxGainStage; /* Tx gain stage */ in phy_InitBBRFRegisterDefinition()376 pHalData->PHYRegDef.rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; /* wire control parameter1 */ in phy_InitBBRFRegisterDefinition()[all …]
378 pPhyReg = &pHalData->PHYRegDef; in phy_RF6052_Config_ParaFile()
98 struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath]; in phy_RFSerialRead_8723B()194 struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath]; in phy_RFSerialWrite_8723B()311 …pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from… in phy_InitBBRFRegisterDefinition()312 …pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from… in phy_InitBBRFRegisterDefinition()315 …pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from … in phy_InitBBRFRegisterDefinition()316 …pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from … in phy_InitBBRFRegisterDefinition()319 …pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from … in phy_InitBBRFRegisterDefinition()320 …pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from … in phy_InitBBRFRegisterDefinition()322 pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */ in phy_InitBBRFRegisterDefinition()323 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; in phy_InitBBRFRegisterDefinition()[all …]
95 pPhyReg = &pHalData->PHYRegDef[eRFPath]; in phy_RF6052_Config_ParaFile()
131 struct bb_reg_def PHYRegDef; member
309 struct bb_register_def PHYRegDef[4]; /* Radio A/B/C/D */ member