| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.h | 60 SRII(PHASE, DP_DTO, 0),\
61 SRII(PHASE, DP_DTO, 1),\
62 SRII(PHASE, DP_DTO, 2),\
63 SRII(PHASE, DP_DTO, 3),\
64 SRII(PHASE, DP_DTO, 4),\
65 SRII(PHASE, DP_DTO, 5),\
81 SRII(PHASE, DP_DTO, 0),\
82 SRII(PHASE, DP_DTO, 1),\
90 SRII(PHASE, DP_DTO, 0),\
91 SRII(PHASE, DP_DTO, 1),\
[all …]
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| D | dce_clock_source.c | 929 REG_WRITE(PHASE[inst], clock_100hz); in dce112_program_pix_clk()
991 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); in dcn31_program_pix_clk()
995 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); in dcn31_program_pix_clk()
1022 REG_WRITE(PHASE[inst], clock_100hz); in dcn31_program_pix_clk()
1131 clock_hz = REG_READ(PHASE[inst]); in get_pixel_clk_frequency_100hz()
1240 REG_WRITE(PHASE[inst], pixel_clk); in dcn20_override_dp_pix_clk()
1270 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); in dcn3_program_pix_clk()
1274 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); in dcn3_program_pix_clk()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_dccg.h | 59 DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
60 DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
61 DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
62 DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
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| D | dcn32_resource.h | 151 SRII_ARR_2(PHASE, DP_DTO, 0, index), \
152 SRII_ARR_2(PHASE, DP_DTO, 1, index), \
153 SRII_ARR_2(PHASE, DP_DTO, 2, index), \
154 SRII_ARR_2(PHASE, DP_DTO, 3, index), \
1265 DCCG_SRII(PHASE, DTBCLK_DTO, 0), DCCG_SRII(PHASE, DTBCLK_DTO, 1), \
1266 DCCG_SRII(PHASE, DTBCLK_DTO, 2), DCCG_SRII(PHASE, DTBCLK_DTO, 3), \
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_dccg.h | 60 DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
61 DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
62 DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
63 DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_dccg.h | 53 DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
54 DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
55 DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
56 DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
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| /linux-6.1.9/sound/firewire/ |
| D | Kconfig | 121 * TerraTec PHASE 24 FW/PHASE X24 FW/PHASE 88 Rack FW
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| /linux-6.1.9/drivers/gpu/drm/nouveau/dispnv50/ |
| D | head917d.c | 44 NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in head917d_dither()
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| D | headc37d.c | 100 NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in headc37d_dither()
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| D | head507d.c | 62 NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in head507d_dither()
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| D | head907d.c | 91 NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); in head907d_dither()
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| /linux-6.1.9/drivers/scsi/ |
| D | FlashPoint.c | 499 #define PHASE BIT(13) macro
1806 && !((RDW_HARPOON((ioport + hp_intstat)) & PHASE) in FlashPoint_HandleInterrupt()
1833 (PROG_HLT | RSEL | PHASE | BUS_FREE)); in FlashPoint_HandleInterrupt()
1869 (PHASE | IUNKWN | PROG_HLT)); in FlashPoint_HandleInterrupt()
2057 (PROG_HLT | TIMEOUT | SEL | BUS_FREE | PHASE | in FPT_SccbMgr_bad_isr()
2645 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2650 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_sres()
2723 (PHASE | RESET)) in FPT_sres()
2805 while (!(RDW_HARPOON((port + hp_intstat)) & (PHASE | RESET)) && in FPT_sres()
2815 WRW_HARPOON((port + hp_intstat), PHASE); in FPT_SendMsg()
[all …]
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| /linux-6.1.9/Documentation/networking/ |
| D | can.rst | 1209 [ tq TQ prop-seg PROP_SEG phase-seg1 PHASE-SEG1
1210 phase-seg2 PHASE-SEG2 [ sjw SJW ] ]
1213 [ dtq TQ dprop-seg PROP_SEG dphase-seg1 PHASE-SEG1
1214 dphase-seg2 PHASE-SEG2 [ dsjw SJW ] ]
1233 PHASE-SEG1 := { 1..8 }
1234 PHASE-SEG2 := { 1..8 }
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| /linux-6.1.9/Documentation/scsi/ |
| D | ChangeLog.sym53c8xx | 341 to testing for a PHASE. SYMBIOS say this feature is working fine.
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| D | sym53c8xx_2.rst | 141 LOAD/STORE and handles PHASE MISMATCH from SCRIPTS for devices that
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| D | ncr53c8xx.rst | 1233 have detected an expected disconnection (BUS FREE PHASE). For this process
|