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Searched refs:OUT_RING (Results 1 – 16 of 16) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/r128/
Dr128_state.c56 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); in r128_emit_clip_rects()
57 OUT_RING(boxes[0].x1); in r128_emit_clip_rects()
58 OUT_RING(boxes[0].x2 - 1); in r128_emit_clip_rects()
59 OUT_RING(boxes[0].y1); in r128_emit_clip_rects()
60 OUT_RING(boxes[0].y2 - 1); in r128_emit_clip_rects()
65 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); in r128_emit_clip_rects()
66 OUT_RING(boxes[1].x1); in r128_emit_clip_rects()
67 OUT_RING(boxes[1].x2 - 1); in r128_emit_clip_rects()
68 OUT_RING(boxes[1].y1); in r128_emit_clip_rects()
69 OUT_RING(boxes[1].y2 - 1); in r128_emit_clip_rects()
[all …]
Dr128_drv.h477 OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0)); \
478 OUT_RING(R128_EVENT_CRTC_OFFSET); \
536 #define OUT_RING(x) do { \ macro
/linux-6.1.9/drivers/gpu/drm/i810/
Di810_dma.c468 OUT_RING(GFX_OP_COLOR_FACTOR); in i810EmitContextVerified()
469 OUT_RING(code[I810_CTXREG_CF1]); in i810EmitContextVerified()
471 OUT_RING(GFX_OP_STIPPLE); in i810EmitContextVerified()
472 OUT_RING(code[I810_CTXREG_ST1]); in i810EmitContextVerified()
479 OUT_RING(tmp); in i810EmitContextVerified()
486 OUT_RING(0); in i810EmitContextVerified()
500 OUT_RING(GFX_OP_MAP_INFO); in i810EmitTexVerified()
501 OUT_RING(code[I810_TEXREG_MI1]); in i810EmitTexVerified()
502 OUT_RING(code[I810_TEXREG_MI2]); in i810EmitTexVerified()
503 OUT_RING(code[I810_TEXREG_MI3]); in i810EmitTexVerified()
[all …]
Di810_drv.h166 #define OUT_RING(n) do { \ macro
/linux-6.1.9/drivers/gpu/drm/msm/adreno/
Da2xx_gpu.c30 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); in a2xx_submit()
31 OUT_RING(ring, submit->cmd[i].size); in a2xx_submit()
38 OUT_RING(ring, submit->seqno); in a2xx_submit()
42 OUT_RING(ring, 0x00000000); in a2xx_submit()
45 OUT_RING(ring, CACHE_FLUSH_TS); in a2xx_submit()
46 OUT_RING(ring, rbmemptr(ring, fence)); in a2xx_submit()
47 OUT_RING(ring, submit->seqno); in a2xx_submit()
49 OUT_RING(ring, 0x80000000); in a2xx_submit()
61 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
63 OUT_RING(ring, 0x00000000); in a2xx_me_init()
[all …]
Da3xx_gpu.c48 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); in a3xx_submit()
49 OUT_RING(ring, submit->cmd[i].size); in a3xx_submit()
56 OUT_RING(ring, submit->seqno); in a3xx_submit()
63 OUT_RING(ring, HLSQ_FLUSH); in a3xx_submit()
67 OUT_RING(ring, 0x00000000); in a3xx_submit()
71 OUT_RING(ring, CACHE_FLUSH_TS | CP_EVENT_WRITE_0_IRQ); in a3xx_submit()
72 OUT_RING(ring, rbmemptr(ring, fence)); in a3xx_submit()
73 OUT_RING(ring, submit->seqno); in a3xx_submit()
78 OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG)); in a3xx_submit()
79 OUT_RING(ring, 0x00000000); in a3xx_submit()
[all …]
Da4xx_gpu.c42 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova)); in a4xx_submit()
43 OUT_RING(ring, submit->cmd[i].size); in a4xx_submit()
50 OUT_RING(ring, submit->seqno); in a4xx_submit()
57 OUT_RING(ring, HLSQ_FLUSH); in a4xx_submit()
61 OUT_RING(ring, 0x00000000); in a4xx_submit()
65 OUT_RING(ring, CACHE_FLUSH_TS | CP_EVENT_WRITE_0_IRQ); in a4xx_submit()
66 OUT_RING(ring, rbmemptr(ring, fence)); in a4xx_submit()
67 OUT_RING(ring, submit->seqno); in a4xx_submit()
161 OUT_RING(ring, 0x000003f7); in a4xx_me_init()
162 OUT_RING(ring, 0x00000000); in a4xx_me_init()
[all …]
Da5xx_gpu.c28 OUT_RING(ring, lower_32_bits(shadowptr(a5xx_gpu, ring))); in update_shadow_rptr()
29 OUT_RING(ring, upper_32_bits(shadowptr(a5xx_gpu, ring))); in update_shadow_rptr()
103 OUT_RING(ring, ptr[i]); in a5xx_submit_in_rb()
138 OUT_RING(ring, 0x02); in a5xx_submit()
142 OUT_RING(ring, 0); in a5xx_submit()
146 OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring->id])); in a5xx_submit()
147 OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id])); in a5xx_submit()
151 OUT_RING(ring, 1); in a5xx_submit()
155 OUT_RING(ring, 0x02); in a5xx_submit()
159 OUT_RING(ring, 0x02); in a5xx_submit()
[all …]
Da6xx_gpu.c63 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring))); in update_shadow_rptr()
64 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring))); in update_shadow_rptr()
95 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | in get_stats_counter()
98 OUT_RING(ring, lower_32_bits(iova)); in get_stats_counter()
99 OUT_RING(ring, upper_32_bits(iova)); in get_stats_counter()
119 OUT_RING(ring, 0); in a6xx_set_pagetable()
122 OUT_RING(ring, 1); in a6xx_set_pagetable()
127 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); in a6xx_set_pagetable()
129 OUT_RING(ring, in a6xx_set_pagetable()
132 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0)); in a6xx_set_pagetable()
[all …]
Da5xx_power.c231 OUT_RING(ring, 0); in a5xx_gpmu_init()
235 OUT_RING(ring, lower_32_bits(a5xx_gpu->gpmu_iova)); in a5xx_gpmu_init()
236 OUT_RING(ring, upper_32_bits(a5xx_gpu->gpmu_iova)); in a5xx_gpmu_init()
237 OUT_RING(ring, a5xx_gpu->gpmu_dwords); in a5xx_gpmu_init()
241 OUT_RING(ring, 1); in a5xx_gpmu_init()
Dadreno_gpu.h355 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF)); in OUT_PKT0()
363 OUT_RING(ring, CP_TYPE2_PKT); in OUT_PKT2()
370 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8)); in OUT_PKT3()
392 OUT_RING(ring, PKT4(regindx, cnt)); in OUT_PKT4()
399 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) | in OUT_PKT7()
/linux-6.1.9/drivers/video/fbdev/intelfb/
Dintelfbhw.c1547 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE); in do_flush()
1548 OUT_RING(MI_NOOP); in do_flush()
1685 OUT_RING(br00); in intelfbhw_do_fillrect()
1686 OUT_RING(br13); in intelfbhw_do_fillrect()
1687 OUT_RING(br14); in intelfbhw_do_fillrect()
1688 OUT_RING(br09); in intelfbhw_do_fillrect()
1689 OUT_RING(br16); in intelfbhw_do_fillrect()
1690 OUT_RING(MI_NOOP); in intelfbhw_do_fillrect()
1734 OUT_RING(br00); in intelfbhw_do_bitblt()
1735 OUT_RING(br13); in intelfbhw_do_bitblt()
[all …]
Dintelfbhw.h534 #define OUT_RING(n) do { \ macro
/linux-6.1.9/drivers/gpu/drm/msm/
Dmsm_ringbuffer.h81 OUT_RING(struct msm_ringbuffer *ring, uint32_t data) in OUT_RING() function
/linux-6.1.9/drivers/gpu/drm/nouveau/
Dnouveau_dma.h72 OUT_RING(struct nouveau_channel *chan, int data) in OUT_RING() function
Dnouveau_dma.c212 OUT_RING(chan, chan->push.addr | 0x20000000); in nouveau_dma_wait()