Searched refs:OTG_H_TOTAL (Results 1 – 13 of 13) sorted by relevance
| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/ ! |
| D | dcn20_optc.c | 283 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total); in optc2_align_vblanks()
301 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total); in optc2_align_vblanks()
563 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn20_timing_generator_init()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/ ! |
| D | dcn10_optc.c | 173 REG_SET(OTG_H_TOTAL, 0, in optc1_program_timing()
174 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); in optc1_program_timing()
1360 REG_GET(OTG_H_TOTAL, in optc1_read_otg_state()
1361 OTG_H_TOTAL, &s->h_total); in optc1_read_otg_state()
1582 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn10_timing_generator_init()
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| D | dcn10_optc.h | 42 SRI(OTG_H_TOTAL, OTG, inst),\
114 uint32_t OTG_H_TOTAL; member
201 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
342 type OTG_H_TOTAL;\
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn201/ ! |
| D | dcn201_optc.c | 195 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn201_timing_generator_init()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn314/ ! |
| D | dcn314_optc.c | 266 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn314_timing_generator_init()
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| D | dcn314_optc.h | 42 SRI(OTG_H_TOTAL, OTG, inst),\
119 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/ ! |
| D | dcn31_optc.h | 41 SRI(OTG_H_TOTAL, OTG, inst),\
120 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
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| D | dcn31_optc.c | 301 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn31_timing_generator_init()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/ ! |
| D | dcn32_optc.h | 41 SRI(OTG_H_TOTAL, OTG, inst),\
118 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
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| D | dcn32_optc.c | 319 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn32_timing_generator_init()
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| D | dcn32_resource.h | 1011 SRI_ARR(OTG_H_TOTAL, OTG, inst), \
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/ ! |
| D | dcn30_optc.h | 43 SRI(OTG_H_TOTAL, OTG, inst),\
132 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
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| D | dcn30_optc.c | 360 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn30_timing_generator_init()
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