1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_MACH_REGS_OST_H
3 #define __ASM_MACH_REGS_OST_H
4 
5 #include "pxa-regs.h"
6 
7 /*
8  * OS Timer & Match Registers
9  */
10 #define OST_PHYS	0x40A00000
11 #define OST_LEN		0x00000020
12 
13 #define OSMR0		io_p2v(0x40A00000)  /* */
14 #define OSMR1		io_p2v(0x40A00004)  /* */
15 #define OSMR2		io_p2v(0x40A00008)  /* */
16 #define OSMR3		io_p2v(0x40A0000C)  /* */
17 #define OSMR4		io_p2v(0x40A00080)  /* */
18 #define OSCR		io_p2v(0x40A00010)  /* OS Timer Counter Register */
19 #define OSCR4		io_p2v(0x40A00040)  /* OS Timer Counter Register */
20 #define OMCR4		io_p2v(0x40A000C0)  /* */
21 #define OSSR		io_p2v(0x40A00014)  /* OS Timer Status Register */
22 #define OWER		io_p2v(0x40A00018)  /* OS Timer Watchdog Enable Register */
23 #define OIER		io_p2v(0x40A0001C)  /* OS Timer Interrupt Enable Register */
24 
25 #define OSSR_M3		(1 << 3)	/* Match status channel 3 */
26 #define OSSR_M2		(1 << 2)	/* Match status channel 2 */
27 #define OSSR_M1		(1 << 1)	/* Match status channel 1 */
28 #define OSSR_M0		(1 << 0)	/* Match status channel 0 */
29 
30 #define OWER_WME	(1 << 0)	/* Watchdog Match Enable */
31 
32 #define OIER_E3		(1 << 3)	/* Interrupt enable channel 3 */
33 #define OIER_E2		(1 << 2)	/* Interrupt enable channel 2 */
34 #define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
35 #define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */
36 
37 #endif /* __ASM_MACH_REGS_OST_H */
38