1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Definitions for the NVM Express interface
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #ifndef _LINUX_NVME_H
8 #define _LINUX_NVME_H
9
10 #include <linux/bits.h>
11 #include <linux/types.h>
12 #include <linux/uuid.h>
13
14 /* NQN names in commands fields specified one size */
15 #define NVMF_NQN_FIELD_LEN 256
16
17 /* However the max length of a qualified name is another size */
18 #define NVMF_NQN_SIZE 223
19
20 #define NVMF_TRSVCID_SIZE 32
21 #define NVMF_TRADDR_SIZE 256
22 #define NVMF_TSAS_SIZE 256
23 #define NVMF_AUTH_HASH_LEN 64
24
25 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
26
27 #define NVME_RDMA_IP_PORT 4420
28
29 #define NVME_NSID_ALL 0xffffffff
30
31 enum nvme_subsys_type {
32 /* Referral to another discovery type target subsystem */
33 NVME_NQN_DISC = 1,
34
35 /* NVME type target subsystem */
36 NVME_NQN_NVME = 2,
37
38 /* Current discovery type target subsystem */
39 NVME_NQN_CURR = 3,
40 };
41
42 enum nvme_ctrl_type {
43 NVME_CTRL_IO = 1, /* I/O controller */
44 NVME_CTRL_DISC = 2, /* Discovery controller */
45 NVME_CTRL_ADMIN = 3, /* Administrative controller */
46 };
47
48 enum nvme_dctype {
49 NVME_DCTYPE_NOT_REPORTED = 0,
50 NVME_DCTYPE_DDC = 1, /* Direct Discovery Controller */
51 NVME_DCTYPE_CDC = 2, /* Central Discovery Controller */
52 };
53
54 /* Address Family codes for Discovery Log Page entry ADRFAM field */
55 enum {
56 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
57 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
58 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
59 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
60 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
61 NVMF_ADDR_FAMILY_LOOP = 254, /* Reserved for host usage */
62 NVMF_ADDR_FAMILY_MAX,
63 };
64
65 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
66 enum {
67 NVMF_TRTYPE_RDMA = 1, /* RDMA */
68 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
69 NVMF_TRTYPE_TCP = 3, /* TCP/IP */
70 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
71 NVMF_TRTYPE_MAX,
72 };
73
74 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
75 enum {
76 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
77 NVMF_TREQ_REQUIRED = 1, /* Required */
78 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
79 #define NVME_TREQ_SECURE_CHANNEL_MASK \
80 (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
81
82 NVMF_TREQ_DISABLE_SQFLOW = (1 << 2), /* Supports SQ flow control disable */
83 };
84
85 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
86 * RDMA_QPTYPE field
87 */
88 enum {
89 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
90 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
91 };
92
93 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
94 * RDMA_QPTYPE field
95 */
96 enum {
97 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
98 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
99 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
100 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
101 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
102 };
103
104 /* RDMA Connection Management Service Type codes for Discovery Log Page
105 * entry TSAS RDMA_CMS field
106 */
107 enum {
108 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
109 };
110
111 #define NVME_AQ_DEPTH 32
112 #define NVME_NR_AEN_COMMANDS 1
113 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
114
115 /*
116 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
117 * NVM-Express 1.2 specification, section 4.1.2.
118 */
119 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
120
121 enum {
122 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
123 NVME_REG_VS = 0x0008, /* Version */
124 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
125 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
126 NVME_REG_CC = 0x0014, /* Controller Configuration */
127 NVME_REG_CSTS = 0x001c, /* Controller Status */
128 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
129 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
130 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
131 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
132 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
133 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
134 NVME_REG_BPINFO = 0x0040, /* Boot Partition Information */
135 NVME_REG_BPRSEL = 0x0044, /* Boot Partition Read Select */
136 NVME_REG_BPMBL = 0x0048, /* Boot Partition Memory Buffer
137 * Location
138 */
139 NVME_REG_CMBMSC = 0x0050, /* Controller Memory Buffer Memory
140 * Space Control
141 */
142 NVME_REG_CRTO = 0x0068, /* Controller Ready Timeouts */
143 NVME_REG_PMRCAP = 0x0e00, /* Persistent Memory Capabilities */
144 NVME_REG_PMRCTL = 0x0e04, /* Persistent Memory Region Control */
145 NVME_REG_PMRSTS = 0x0e08, /* Persistent Memory Region Status */
146 NVME_REG_PMREBS = 0x0e0c, /* Persistent Memory Region Elasticity
147 * Buffer Size
148 */
149 NVME_REG_PMRSWTP = 0x0e10, /* Persistent Memory Region Sustained
150 * Write Throughput
151 */
152 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
153 };
154
155 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
156 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
157 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
158 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
159 #define NVME_CAP_CSS(cap) (((cap) >> 37) & 0xff)
160 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
161 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
162 #define NVME_CAP_CMBS(cap) (((cap) >> 57) & 0x1)
163
164 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
165 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
166
167 #define NVME_CRTO_CRIMT(crto) ((crto) >> 16)
168 #define NVME_CRTO_CRWMT(crto) ((crto) & 0xffff)
169
170 enum {
171 NVME_CMBSZ_SQS = 1 << 0,
172 NVME_CMBSZ_CQS = 1 << 1,
173 NVME_CMBSZ_LISTS = 1 << 2,
174 NVME_CMBSZ_RDS = 1 << 3,
175 NVME_CMBSZ_WDS = 1 << 4,
176
177 NVME_CMBSZ_SZ_SHIFT = 12,
178 NVME_CMBSZ_SZ_MASK = 0xfffff,
179
180 NVME_CMBSZ_SZU_SHIFT = 8,
181 NVME_CMBSZ_SZU_MASK = 0xf,
182 };
183
184 /*
185 * Submission and Completion Queue Entry Sizes for the NVM command set.
186 * (In bytes and specified as a power of two (2^n)).
187 */
188 #define NVME_ADM_SQES 6
189 #define NVME_NVM_IOSQES 6
190 #define NVME_NVM_IOCQES 4
191
192 enum {
193 NVME_CC_ENABLE = 1 << 0,
194 NVME_CC_EN_SHIFT = 0,
195 NVME_CC_CSS_SHIFT = 4,
196 NVME_CC_MPS_SHIFT = 7,
197 NVME_CC_AMS_SHIFT = 11,
198 NVME_CC_SHN_SHIFT = 14,
199 NVME_CC_IOSQES_SHIFT = 16,
200 NVME_CC_IOCQES_SHIFT = 20,
201 NVME_CC_CSS_NVM = 0 << NVME_CC_CSS_SHIFT,
202 NVME_CC_CSS_CSI = 6 << NVME_CC_CSS_SHIFT,
203 NVME_CC_CSS_MASK = 7 << NVME_CC_CSS_SHIFT,
204 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
205 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
206 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
207 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
208 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
209 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
210 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
211 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
212 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
213 NVME_CC_CRIME = 1 << 24,
214 };
215
216 enum {
217 NVME_CSTS_RDY = 1 << 0,
218 NVME_CSTS_CFS = 1 << 1,
219 NVME_CSTS_NSSRO = 1 << 4,
220 NVME_CSTS_PP = 1 << 5,
221 NVME_CSTS_SHST_NORMAL = 0 << 2,
222 NVME_CSTS_SHST_OCCUR = 1 << 2,
223 NVME_CSTS_SHST_CMPLT = 2 << 2,
224 NVME_CSTS_SHST_MASK = 3 << 2,
225 };
226
227 enum {
228 NVME_CMBMSC_CRE = 1 << 0,
229 NVME_CMBMSC_CMSE = 1 << 1,
230 };
231
232 enum {
233 NVME_CAP_CSS_NVM = 1 << 0,
234 NVME_CAP_CSS_CSI = 1 << 6,
235 };
236
237 enum {
238 NVME_CAP_CRMS_CRWMS = 1ULL << 59,
239 NVME_CAP_CRMS_CRIMS = 1ULL << 60,
240 };
241
242 struct nvme_id_power_state {
243 __le16 max_power; /* centiwatts */
244 __u8 rsvd2;
245 __u8 flags;
246 __le32 entry_lat; /* microseconds */
247 __le32 exit_lat; /* microseconds */
248 __u8 read_tput;
249 __u8 read_lat;
250 __u8 write_tput;
251 __u8 write_lat;
252 __le16 idle_power;
253 __u8 idle_scale;
254 __u8 rsvd19;
255 __le16 active_power;
256 __u8 active_work_scale;
257 __u8 rsvd23[9];
258 };
259
260 enum {
261 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
262 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
263 };
264
265 enum nvme_ctrl_attr {
266 NVME_CTRL_ATTR_HID_128_BIT = (1 << 0),
267 NVME_CTRL_ATTR_TBKAS = (1 << 6),
268 NVME_CTRL_ATTR_ELBAS = (1 << 15),
269 };
270
271 struct nvme_id_ctrl {
272 __le16 vid;
273 __le16 ssvid;
274 char sn[20];
275 char mn[40];
276 char fr[8];
277 __u8 rab;
278 __u8 ieee[3];
279 __u8 cmic;
280 __u8 mdts;
281 __le16 cntlid;
282 __le32 ver;
283 __le32 rtd3r;
284 __le32 rtd3e;
285 __le32 oaes;
286 __le32 ctratt;
287 __u8 rsvd100[11];
288 __u8 cntrltype;
289 __u8 fguid[16];
290 __le16 crdt1;
291 __le16 crdt2;
292 __le16 crdt3;
293 __u8 rsvd134[122];
294 __le16 oacs;
295 __u8 acl;
296 __u8 aerl;
297 __u8 frmw;
298 __u8 lpa;
299 __u8 elpe;
300 __u8 npss;
301 __u8 avscc;
302 __u8 apsta;
303 __le16 wctemp;
304 __le16 cctemp;
305 __le16 mtfa;
306 __le32 hmpre;
307 __le32 hmmin;
308 __u8 tnvmcap[16];
309 __u8 unvmcap[16];
310 __le32 rpmbs;
311 __le16 edstt;
312 __u8 dsto;
313 __u8 fwug;
314 __le16 kas;
315 __le16 hctma;
316 __le16 mntmt;
317 __le16 mxtmt;
318 __le32 sanicap;
319 __le32 hmminds;
320 __le16 hmmaxd;
321 __u8 rsvd338[4];
322 __u8 anatt;
323 __u8 anacap;
324 __le32 anagrpmax;
325 __le32 nanagrpid;
326 __u8 rsvd352[160];
327 __u8 sqes;
328 __u8 cqes;
329 __le16 maxcmd;
330 __le32 nn;
331 __le16 oncs;
332 __le16 fuses;
333 __u8 fna;
334 __u8 vwc;
335 __le16 awun;
336 __le16 awupf;
337 __u8 nvscc;
338 __u8 nwpc;
339 __le16 acwu;
340 __u8 rsvd534[2];
341 __le32 sgls;
342 __le32 mnan;
343 __u8 rsvd544[224];
344 char subnqn[256];
345 __u8 rsvd1024[768];
346 __le32 ioccsz;
347 __le32 iorcsz;
348 __le16 icdoff;
349 __u8 ctrattr;
350 __u8 msdbd;
351 __u8 rsvd1804[2];
352 __u8 dctype;
353 __u8 rsvd1807[241];
354 struct nvme_id_power_state psd[32];
355 __u8 vs[1024];
356 };
357
358 enum {
359 NVME_CTRL_CMIC_MULTI_PORT = 1 << 0,
360 NVME_CTRL_CMIC_MULTI_CTRL = 1 << 1,
361 NVME_CTRL_CMIC_ANA = 1 << 3,
362 NVME_CTRL_ONCS_COMPARE = 1 << 0,
363 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
364 NVME_CTRL_ONCS_DSM = 1 << 2,
365 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
366 NVME_CTRL_ONCS_RESERVATIONS = 1 << 5,
367 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
368 NVME_CTRL_VWC_PRESENT = 1 << 0,
369 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
370 NVME_CTRL_OACS_NS_MNGT_SUPP = 1 << 3,
371 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
372 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
373 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
374 NVME_CTRL_CTRATT_128_ID = 1 << 0,
375 NVME_CTRL_CTRATT_NON_OP_PSP = 1 << 1,
376 NVME_CTRL_CTRATT_NVM_SETS = 1 << 2,
377 NVME_CTRL_CTRATT_READ_RECV_LVLS = 1 << 3,
378 NVME_CTRL_CTRATT_ENDURANCE_GROUPS = 1 << 4,
379 NVME_CTRL_CTRATT_PREDICTABLE_LAT = 1 << 5,
380 NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY = 1 << 7,
381 NVME_CTRL_CTRATT_UUID_LIST = 1 << 9,
382 };
383
384 struct nvme_lbaf {
385 __le16 ms;
386 __u8 ds;
387 __u8 rp;
388 };
389
390 struct nvme_id_ns {
391 __le64 nsze;
392 __le64 ncap;
393 __le64 nuse;
394 __u8 nsfeat;
395 __u8 nlbaf;
396 __u8 flbas;
397 __u8 mc;
398 __u8 dpc;
399 __u8 dps;
400 __u8 nmic;
401 __u8 rescap;
402 __u8 fpi;
403 __u8 dlfeat;
404 __le16 nawun;
405 __le16 nawupf;
406 __le16 nacwu;
407 __le16 nabsn;
408 __le16 nabo;
409 __le16 nabspf;
410 __le16 noiob;
411 __u8 nvmcap[16];
412 __le16 npwg;
413 __le16 npwa;
414 __le16 npdg;
415 __le16 npda;
416 __le16 nows;
417 __u8 rsvd74[18];
418 __le32 anagrpid;
419 __u8 rsvd96[3];
420 __u8 nsattr;
421 __le16 nvmsetid;
422 __le16 endgid;
423 __u8 nguid[16];
424 __u8 eui64[8];
425 struct nvme_lbaf lbaf[64];
426 __u8 vs[3712];
427 };
428
429 /* I/O Command Set Independent Identify Namespace Data Structure */
430 struct nvme_id_ns_cs_indep {
431 __u8 nsfeat;
432 __u8 nmic;
433 __u8 rescap;
434 __u8 fpi;
435 __le32 anagrpid;
436 __u8 nsattr;
437 __u8 rsvd9;
438 __le16 nvmsetid;
439 __le16 endgid;
440 __u8 nstat;
441 __u8 rsvd15[4081];
442 };
443
444 struct nvme_zns_lbafe {
445 __le64 zsze;
446 __u8 zdes;
447 __u8 rsvd9[7];
448 };
449
450 struct nvme_id_ns_zns {
451 __le16 zoc;
452 __le16 ozcs;
453 __le32 mar;
454 __le32 mor;
455 __le32 rrl;
456 __le32 frl;
457 __u8 rsvd20[2796];
458 struct nvme_zns_lbafe lbafe[64];
459 __u8 vs[256];
460 };
461
462 struct nvme_id_ctrl_zns {
463 __u8 zasl;
464 __u8 rsvd1[4095];
465 };
466
467 struct nvme_id_ns_nvm {
468 __le64 lbstm;
469 __u8 pic;
470 __u8 rsvd9[3];
471 __le32 elbaf[64];
472 __u8 rsvd268[3828];
473 };
474
475 enum {
476 NVME_ID_NS_NVM_STS_MASK = 0x3f,
477 NVME_ID_NS_NVM_GUARD_SHIFT = 7,
478 NVME_ID_NS_NVM_GUARD_MASK = 0x3,
479 };
480
nvme_elbaf_sts(__u32 elbaf)481 static inline __u8 nvme_elbaf_sts(__u32 elbaf)
482 {
483 return elbaf & NVME_ID_NS_NVM_STS_MASK;
484 }
485
nvme_elbaf_guard_type(__u32 elbaf)486 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
487 {
488 return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
489 }
490
491 struct nvme_id_ctrl_nvm {
492 __u8 vsl;
493 __u8 wzsl;
494 __u8 wusl;
495 __u8 dmrl;
496 __le32 dmrsl;
497 __le64 dmsl;
498 __u8 rsvd16[4080];
499 };
500
501 enum {
502 NVME_ID_CNS_NS = 0x00,
503 NVME_ID_CNS_CTRL = 0x01,
504 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
505 NVME_ID_CNS_NS_DESC_LIST = 0x03,
506 NVME_ID_CNS_CS_NS = 0x05,
507 NVME_ID_CNS_CS_CTRL = 0x06,
508 NVME_ID_CNS_NS_CS_INDEP = 0x08,
509 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
510 NVME_ID_CNS_NS_PRESENT = 0x11,
511 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
512 NVME_ID_CNS_CTRL_LIST = 0x13,
513 NVME_ID_CNS_SCNDRY_CTRL_LIST = 0x15,
514 NVME_ID_CNS_NS_GRANULARITY = 0x16,
515 NVME_ID_CNS_UUID_LIST = 0x17,
516 };
517
518 enum {
519 NVME_CSI_NVM = 0,
520 NVME_CSI_ZNS = 2,
521 };
522
523 enum {
524 NVME_DIR_IDENTIFY = 0x00,
525 NVME_DIR_STREAMS = 0x01,
526 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
527 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
528 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
529 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
530 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
531 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
532 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
533 NVME_DIR_ENDIR = 0x01,
534 };
535
536 enum {
537 NVME_NS_FEAT_THIN = 1 << 0,
538 NVME_NS_FEAT_ATOMICS = 1 << 1,
539 NVME_NS_FEAT_IO_OPT = 1 << 4,
540 NVME_NS_ATTR_RO = 1 << 0,
541 NVME_NS_FLBAS_LBA_MASK = 0xf,
542 NVME_NS_FLBAS_LBA_UMASK = 0x60,
543 NVME_NS_FLBAS_LBA_SHIFT = 1,
544 NVME_NS_FLBAS_META_EXT = 0x10,
545 NVME_NS_NMIC_SHARED = 1 << 0,
546 NVME_LBAF_RP_BEST = 0,
547 NVME_LBAF_RP_BETTER = 1,
548 NVME_LBAF_RP_GOOD = 2,
549 NVME_LBAF_RP_DEGRADED = 3,
550 NVME_NS_DPC_PI_LAST = 1 << 4,
551 NVME_NS_DPC_PI_FIRST = 1 << 3,
552 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
553 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
554 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
555 NVME_NS_DPS_PI_FIRST = 1 << 3,
556 NVME_NS_DPS_PI_MASK = 0x7,
557 NVME_NS_DPS_PI_TYPE1 = 1,
558 NVME_NS_DPS_PI_TYPE2 = 2,
559 NVME_NS_DPS_PI_TYPE3 = 3,
560 };
561
562 enum {
563 NVME_NSTAT_NRDY = 1 << 0,
564 };
565
566 enum {
567 NVME_NVM_NS_16B_GUARD = 0,
568 NVME_NVM_NS_32B_GUARD = 1,
569 NVME_NVM_NS_64B_GUARD = 2,
570 };
571
nvme_lbaf_index(__u8 flbas)572 static inline __u8 nvme_lbaf_index(__u8 flbas)
573 {
574 return (flbas & NVME_NS_FLBAS_LBA_MASK) |
575 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
576 }
577
578 /* Identify Namespace Metadata Capabilities (MC): */
579 enum {
580 NVME_MC_EXTENDED_LBA = (1 << 0),
581 NVME_MC_METADATA_PTR = (1 << 1),
582 };
583
584 struct nvme_ns_id_desc {
585 __u8 nidt;
586 __u8 nidl;
587 __le16 reserved;
588 };
589
590 #define NVME_NIDT_EUI64_LEN 8
591 #define NVME_NIDT_NGUID_LEN 16
592 #define NVME_NIDT_UUID_LEN 16
593 #define NVME_NIDT_CSI_LEN 1
594
595 enum {
596 NVME_NIDT_EUI64 = 0x01,
597 NVME_NIDT_NGUID = 0x02,
598 NVME_NIDT_UUID = 0x03,
599 NVME_NIDT_CSI = 0x04,
600 };
601
602 struct nvme_smart_log {
603 __u8 critical_warning;
604 __u8 temperature[2];
605 __u8 avail_spare;
606 __u8 spare_thresh;
607 __u8 percent_used;
608 __u8 endu_grp_crit_warn_sumry;
609 __u8 rsvd7[25];
610 __u8 data_units_read[16];
611 __u8 data_units_written[16];
612 __u8 host_reads[16];
613 __u8 host_writes[16];
614 __u8 ctrl_busy_time[16];
615 __u8 power_cycles[16];
616 __u8 power_on_hours[16];
617 __u8 unsafe_shutdowns[16];
618 __u8 media_errors[16];
619 __u8 num_err_log_entries[16];
620 __le32 warning_temp_time;
621 __le32 critical_comp_time;
622 __le16 temp_sensor[8];
623 __le32 thm_temp1_trans_count;
624 __le32 thm_temp2_trans_count;
625 __le32 thm_temp1_total_time;
626 __le32 thm_temp2_total_time;
627 __u8 rsvd232[280];
628 };
629
630 struct nvme_fw_slot_info_log {
631 __u8 afi;
632 __u8 rsvd1[7];
633 __le64 frs[7];
634 __u8 rsvd64[448];
635 };
636
637 enum {
638 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
639 NVME_CMD_EFFECTS_LBCC = 1 << 1,
640 NVME_CMD_EFFECTS_NCC = 1 << 2,
641 NVME_CMD_EFFECTS_NIC = 1 << 3,
642 NVME_CMD_EFFECTS_CCC = 1 << 4,
643 NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16),
644 NVME_CMD_EFFECTS_UUID_SEL = 1 << 19,
645 };
646
647 struct nvme_effects_log {
648 __le32 acs[256];
649 __le32 iocs[256];
650 __u8 resv[2048];
651 };
652
653 enum nvme_ana_state {
654 NVME_ANA_OPTIMIZED = 0x01,
655 NVME_ANA_NONOPTIMIZED = 0x02,
656 NVME_ANA_INACCESSIBLE = 0x03,
657 NVME_ANA_PERSISTENT_LOSS = 0x04,
658 NVME_ANA_CHANGE = 0x0f,
659 };
660
661 struct nvme_ana_group_desc {
662 __le32 grpid;
663 __le32 nnsids;
664 __le64 chgcnt;
665 __u8 state;
666 __u8 rsvd17[15];
667 __le32 nsids[];
668 };
669
670 /* flag for the log specific field of the ANA log */
671 #define NVME_ANA_LOG_RGO (1 << 0)
672
673 struct nvme_ana_rsp_hdr {
674 __le64 chgcnt;
675 __le16 ngrps;
676 __le16 rsvd10[3];
677 };
678
679 struct nvme_zone_descriptor {
680 __u8 zt;
681 __u8 zs;
682 __u8 za;
683 __u8 rsvd3[5];
684 __le64 zcap;
685 __le64 zslba;
686 __le64 wp;
687 __u8 rsvd32[32];
688 };
689
690 enum {
691 NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
692 };
693
694 struct nvme_zone_report {
695 __le64 nr_zones;
696 __u8 resv8[56];
697 struct nvme_zone_descriptor entries[];
698 };
699
700 enum {
701 NVME_SMART_CRIT_SPARE = 1 << 0,
702 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
703 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
704 NVME_SMART_CRIT_MEDIA = 1 << 3,
705 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
706 };
707
708 enum {
709 NVME_AER_ERROR = 0,
710 NVME_AER_SMART = 1,
711 NVME_AER_NOTICE = 2,
712 NVME_AER_CSS = 6,
713 NVME_AER_VS = 7,
714 };
715
716 enum {
717 NVME_AER_ERROR_PERSIST_INT_ERR = 0x03,
718 };
719
720 enum {
721 NVME_AER_NOTICE_NS_CHANGED = 0x00,
722 NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
723 NVME_AER_NOTICE_ANA = 0x03,
724 NVME_AER_NOTICE_DISC_CHANGED = 0xf0,
725 };
726
727 enum {
728 NVME_AEN_BIT_NS_ATTR = 8,
729 NVME_AEN_BIT_FW_ACT = 9,
730 NVME_AEN_BIT_ANA_CHANGE = 11,
731 NVME_AEN_BIT_DISC_CHANGE = 31,
732 };
733
734 enum {
735 NVME_AEN_CFG_NS_ATTR = 1 << NVME_AEN_BIT_NS_ATTR,
736 NVME_AEN_CFG_FW_ACT = 1 << NVME_AEN_BIT_FW_ACT,
737 NVME_AEN_CFG_ANA_CHANGE = 1 << NVME_AEN_BIT_ANA_CHANGE,
738 NVME_AEN_CFG_DISC_CHANGE = 1 << NVME_AEN_BIT_DISC_CHANGE,
739 };
740
741 struct nvme_lba_range_type {
742 __u8 type;
743 __u8 attributes;
744 __u8 rsvd2[14];
745 __le64 slba;
746 __le64 nlb;
747 __u8 guid[16];
748 __u8 rsvd48[16];
749 };
750
751 enum {
752 NVME_LBART_TYPE_FS = 0x01,
753 NVME_LBART_TYPE_RAID = 0x02,
754 NVME_LBART_TYPE_CACHE = 0x03,
755 NVME_LBART_TYPE_SWAP = 0x04,
756
757 NVME_LBART_ATTRIB_TEMP = 1 << 0,
758 NVME_LBART_ATTRIB_HIDE = 1 << 1,
759 };
760
761 struct nvme_reservation_status {
762 __le32 gen;
763 __u8 rtype;
764 __u8 regctl[2];
765 __u8 resv5[2];
766 __u8 ptpls;
767 __u8 resv10[13];
768 struct {
769 __le16 cntlid;
770 __u8 rcsts;
771 __u8 resv3[5];
772 __le64 hostid;
773 __le64 rkey;
774 } regctl_ds[];
775 };
776
777 enum nvme_async_event_type {
778 NVME_AER_TYPE_ERROR = 0,
779 NVME_AER_TYPE_SMART = 1,
780 NVME_AER_TYPE_NOTICE = 2,
781 };
782
783 /* I/O commands */
784
785 enum nvme_opcode {
786 nvme_cmd_flush = 0x00,
787 nvme_cmd_write = 0x01,
788 nvme_cmd_read = 0x02,
789 nvme_cmd_write_uncor = 0x04,
790 nvme_cmd_compare = 0x05,
791 nvme_cmd_write_zeroes = 0x08,
792 nvme_cmd_dsm = 0x09,
793 nvme_cmd_verify = 0x0c,
794 nvme_cmd_resv_register = 0x0d,
795 nvme_cmd_resv_report = 0x0e,
796 nvme_cmd_resv_acquire = 0x11,
797 nvme_cmd_resv_release = 0x15,
798 nvme_cmd_zone_mgmt_send = 0x79,
799 nvme_cmd_zone_mgmt_recv = 0x7a,
800 nvme_cmd_zone_append = 0x7d,
801 };
802
803 #define nvme_opcode_name(opcode) { opcode, #opcode }
804 #define show_nvm_opcode_name(val) \
805 __print_symbolic(val, \
806 nvme_opcode_name(nvme_cmd_flush), \
807 nvme_opcode_name(nvme_cmd_write), \
808 nvme_opcode_name(nvme_cmd_read), \
809 nvme_opcode_name(nvme_cmd_write_uncor), \
810 nvme_opcode_name(nvme_cmd_compare), \
811 nvme_opcode_name(nvme_cmd_write_zeroes), \
812 nvme_opcode_name(nvme_cmd_dsm), \
813 nvme_opcode_name(nvme_cmd_resv_register), \
814 nvme_opcode_name(nvme_cmd_resv_report), \
815 nvme_opcode_name(nvme_cmd_resv_acquire), \
816 nvme_opcode_name(nvme_cmd_resv_release), \
817 nvme_opcode_name(nvme_cmd_zone_mgmt_send), \
818 nvme_opcode_name(nvme_cmd_zone_mgmt_recv), \
819 nvme_opcode_name(nvme_cmd_zone_append))
820
821
822
823 /*
824 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
825 *
826 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
827 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
828 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
829 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
830 * request subtype
831 */
832 enum {
833 NVME_SGL_FMT_ADDRESS = 0x00,
834 NVME_SGL_FMT_OFFSET = 0x01,
835 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
836 NVME_SGL_FMT_INVALIDATE = 0x0f,
837 };
838
839 /*
840 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
841 *
842 * For struct nvme_sgl_desc:
843 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
844 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
845 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
846 *
847 * For struct nvme_keyed_sgl_desc:
848 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
849 *
850 * Transport-specific SGL types:
851 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
852 */
853 enum {
854 NVME_SGL_FMT_DATA_DESC = 0x00,
855 NVME_SGL_FMT_SEG_DESC = 0x02,
856 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
857 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
858 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
859 };
860
861 struct nvme_sgl_desc {
862 __le64 addr;
863 __le32 length;
864 __u8 rsvd[3];
865 __u8 type;
866 };
867
868 struct nvme_keyed_sgl_desc {
869 __le64 addr;
870 __u8 length[3];
871 __u8 key[4];
872 __u8 type;
873 };
874
875 union nvme_data_ptr {
876 struct {
877 __le64 prp1;
878 __le64 prp2;
879 };
880 struct nvme_sgl_desc sgl;
881 struct nvme_keyed_sgl_desc ksgl;
882 };
883
884 /*
885 * Lowest two bits of our flags field (FUSE field in the spec):
886 *
887 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
888 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
889 *
890 * Highest two bits in our flags field (PSDT field in the spec):
891 *
892 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
893 * If used, MPTR contains addr of single physical buffer (byte aligned).
894 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
895 * If used, MPTR contains an address of an SGL segment containing
896 * exactly 1 SGL descriptor (qword aligned).
897 */
898 enum {
899 NVME_CMD_FUSE_FIRST = (1 << 0),
900 NVME_CMD_FUSE_SECOND = (1 << 1),
901
902 NVME_CMD_SGL_METABUF = (1 << 6),
903 NVME_CMD_SGL_METASEG = (1 << 7),
904 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
905 };
906
907 struct nvme_common_command {
908 __u8 opcode;
909 __u8 flags;
910 __u16 command_id;
911 __le32 nsid;
912 __le32 cdw2[2];
913 __le64 metadata;
914 union nvme_data_ptr dptr;
915 struct_group(cdws,
916 __le32 cdw10;
917 __le32 cdw11;
918 __le32 cdw12;
919 __le32 cdw13;
920 __le32 cdw14;
921 __le32 cdw15;
922 );
923 };
924
925 struct nvme_rw_command {
926 __u8 opcode;
927 __u8 flags;
928 __u16 command_id;
929 __le32 nsid;
930 __le32 cdw2;
931 __le32 cdw3;
932 __le64 metadata;
933 union nvme_data_ptr dptr;
934 __le64 slba;
935 __le16 length;
936 __le16 control;
937 __le32 dsmgmt;
938 __le32 reftag;
939 __le16 apptag;
940 __le16 appmask;
941 };
942
943 enum {
944 NVME_RW_LR = 1 << 15,
945 NVME_RW_FUA = 1 << 14,
946 NVME_RW_APPEND_PIREMAP = 1 << 9,
947 NVME_RW_DSM_FREQ_UNSPEC = 0,
948 NVME_RW_DSM_FREQ_TYPICAL = 1,
949 NVME_RW_DSM_FREQ_RARE = 2,
950 NVME_RW_DSM_FREQ_READS = 3,
951 NVME_RW_DSM_FREQ_WRITES = 4,
952 NVME_RW_DSM_FREQ_RW = 5,
953 NVME_RW_DSM_FREQ_ONCE = 6,
954 NVME_RW_DSM_FREQ_PREFETCH = 7,
955 NVME_RW_DSM_FREQ_TEMP = 8,
956 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
957 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
958 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
959 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
960 NVME_RW_DSM_SEQ_REQ = 1 << 6,
961 NVME_RW_DSM_COMPRESSED = 1 << 7,
962 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
963 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
964 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
965 NVME_RW_PRINFO_PRACT = 1 << 13,
966 NVME_RW_DTYPE_STREAMS = 1 << 4,
967 };
968
969 struct nvme_dsm_cmd {
970 __u8 opcode;
971 __u8 flags;
972 __u16 command_id;
973 __le32 nsid;
974 __u64 rsvd2[2];
975 union nvme_data_ptr dptr;
976 __le32 nr;
977 __le32 attributes;
978 __u32 rsvd12[4];
979 };
980
981 enum {
982 NVME_DSMGMT_IDR = 1 << 0,
983 NVME_DSMGMT_IDW = 1 << 1,
984 NVME_DSMGMT_AD = 1 << 2,
985 };
986
987 #define NVME_DSM_MAX_RANGES 256
988
989 struct nvme_dsm_range {
990 __le32 cattr;
991 __le32 nlb;
992 __le64 slba;
993 };
994
995 struct nvme_write_zeroes_cmd {
996 __u8 opcode;
997 __u8 flags;
998 __u16 command_id;
999 __le32 nsid;
1000 __u64 rsvd2;
1001 __le64 metadata;
1002 union nvme_data_ptr dptr;
1003 __le64 slba;
1004 __le16 length;
1005 __le16 control;
1006 __le32 dsmgmt;
1007 __le32 reftag;
1008 __le16 apptag;
1009 __le16 appmask;
1010 };
1011
1012 enum nvme_zone_mgmt_action {
1013 NVME_ZONE_CLOSE = 0x1,
1014 NVME_ZONE_FINISH = 0x2,
1015 NVME_ZONE_OPEN = 0x3,
1016 NVME_ZONE_RESET = 0x4,
1017 NVME_ZONE_OFFLINE = 0x5,
1018 NVME_ZONE_SET_DESC_EXT = 0x10,
1019 };
1020
1021 struct nvme_zone_mgmt_send_cmd {
1022 __u8 opcode;
1023 __u8 flags;
1024 __u16 command_id;
1025 __le32 nsid;
1026 __le32 cdw2[2];
1027 __le64 metadata;
1028 union nvme_data_ptr dptr;
1029 __le64 slba;
1030 __le32 cdw12;
1031 __u8 zsa;
1032 __u8 select_all;
1033 __u8 rsvd13[2];
1034 __le32 cdw14[2];
1035 };
1036
1037 struct nvme_zone_mgmt_recv_cmd {
1038 __u8 opcode;
1039 __u8 flags;
1040 __u16 command_id;
1041 __le32 nsid;
1042 __le64 rsvd2[2];
1043 union nvme_data_ptr dptr;
1044 __le64 slba;
1045 __le32 numd;
1046 __u8 zra;
1047 __u8 zrasf;
1048 __u8 pr;
1049 __u8 rsvd13;
1050 __le32 cdw14[2];
1051 };
1052
1053 enum {
1054 NVME_ZRA_ZONE_REPORT = 0,
1055 NVME_ZRASF_ZONE_REPORT_ALL = 0,
1056 NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
1057 NVME_ZRASF_ZONE_STATE_IMP_OPEN = 0x02,
1058 NVME_ZRASF_ZONE_STATE_EXP_OPEN = 0x03,
1059 NVME_ZRASF_ZONE_STATE_CLOSED = 0x04,
1060 NVME_ZRASF_ZONE_STATE_READONLY = 0x05,
1061 NVME_ZRASF_ZONE_STATE_FULL = 0x06,
1062 NVME_ZRASF_ZONE_STATE_OFFLINE = 0x07,
1063 NVME_REPORT_ZONE_PARTIAL = 1,
1064 };
1065
1066 /* Features */
1067
1068 enum {
1069 NVME_TEMP_THRESH_MASK = 0xffff,
1070 NVME_TEMP_THRESH_SELECT_SHIFT = 16,
1071 NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
1072 };
1073
1074 struct nvme_feat_auto_pst {
1075 __le64 entries[32];
1076 };
1077
1078 enum {
1079 NVME_HOST_MEM_ENABLE = (1 << 0),
1080 NVME_HOST_MEM_RETURN = (1 << 1),
1081 };
1082
1083 struct nvme_feat_host_behavior {
1084 __u8 acre;
1085 __u8 etdas;
1086 __u8 lbafee;
1087 __u8 resv1[509];
1088 };
1089
1090 enum {
1091 NVME_ENABLE_ACRE = 1,
1092 NVME_ENABLE_LBAFEE = 1,
1093 };
1094
1095 /* Admin commands */
1096
1097 enum nvme_admin_opcode {
1098 nvme_admin_delete_sq = 0x00,
1099 nvme_admin_create_sq = 0x01,
1100 nvme_admin_get_log_page = 0x02,
1101 nvme_admin_delete_cq = 0x04,
1102 nvme_admin_create_cq = 0x05,
1103 nvme_admin_identify = 0x06,
1104 nvme_admin_abort_cmd = 0x08,
1105 nvme_admin_set_features = 0x09,
1106 nvme_admin_get_features = 0x0a,
1107 nvme_admin_async_event = 0x0c,
1108 nvme_admin_ns_mgmt = 0x0d,
1109 nvme_admin_activate_fw = 0x10,
1110 nvme_admin_download_fw = 0x11,
1111 nvme_admin_dev_self_test = 0x14,
1112 nvme_admin_ns_attach = 0x15,
1113 nvme_admin_keep_alive = 0x18,
1114 nvme_admin_directive_send = 0x19,
1115 nvme_admin_directive_recv = 0x1a,
1116 nvme_admin_virtual_mgmt = 0x1c,
1117 nvme_admin_nvme_mi_send = 0x1d,
1118 nvme_admin_nvme_mi_recv = 0x1e,
1119 nvme_admin_dbbuf = 0x7C,
1120 nvme_admin_format_nvm = 0x80,
1121 nvme_admin_security_send = 0x81,
1122 nvme_admin_security_recv = 0x82,
1123 nvme_admin_sanitize_nvm = 0x84,
1124 nvme_admin_get_lba_status = 0x86,
1125 nvme_admin_vendor_start = 0xC0,
1126 };
1127
1128 #define nvme_admin_opcode_name(opcode) { opcode, #opcode }
1129 #define show_admin_opcode_name(val) \
1130 __print_symbolic(val, \
1131 nvme_admin_opcode_name(nvme_admin_delete_sq), \
1132 nvme_admin_opcode_name(nvme_admin_create_sq), \
1133 nvme_admin_opcode_name(nvme_admin_get_log_page), \
1134 nvme_admin_opcode_name(nvme_admin_delete_cq), \
1135 nvme_admin_opcode_name(nvme_admin_create_cq), \
1136 nvme_admin_opcode_name(nvme_admin_identify), \
1137 nvme_admin_opcode_name(nvme_admin_abort_cmd), \
1138 nvme_admin_opcode_name(nvme_admin_set_features), \
1139 nvme_admin_opcode_name(nvme_admin_get_features), \
1140 nvme_admin_opcode_name(nvme_admin_async_event), \
1141 nvme_admin_opcode_name(nvme_admin_ns_mgmt), \
1142 nvme_admin_opcode_name(nvme_admin_activate_fw), \
1143 nvme_admin_opcode_name(nvme_admin_download_fw), \
1144 nvme_admin_opcode_name(nvme_admin_ns_attach), \
1145 nvme_admin_opcode_name(nvme_admin_keep_alive), \
1146 nvme_admin_opcode_name(nvme_admin_directive_send), \
1147 nvme_admin_opcode_name(nvme_admin_directive_recv), \
1148 nvme_admin_opcode_name(nvme_admin_dbbuf), \
1149 nvme_admin_opcode_name(nvme_admin_format_nvm), \
1150 nvme_admin_opcode_name(nvme_admin_security_send), \
1151 nvme_admin_opcode_name(nvme_admin_security_recv), \
1152 nvme_admin_opcode_name(nvme_admin_sanitize_nvm), \
1153 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1154
1155 enum {
1156 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
1157 NVME_CQ_IRQ_ENABLED = (1 << 1),
1158 NVME_SQ_PRIO_URGENT = (0 << 1),
1159 NVME_SQ_PRIO_HIGH = (1 << 1),
1160 NVME_SQ_PRIO_MEDIUM = (2 << 1),
1161 NVME_SQ_PRIO_LOW = (3 << 1),
1162 NVME_FEAT_ARBITRATION = 0x01,
1163 NVME_FEAT_POWER_MGMT = 0x02,
1164 NVME_FEAT_LBA_RANGE = 0x03,
1165 NVME_FEAT_TEMP_THRESH = 0x04,
1166 NVME_FEAT_ERR_RECOVERY = 0x05,
1167 NVME_FEAT_VOLATILE_WC = 0x06,
1168 NVME_FEAT_NUM_QUEUES = 0x07,
1169 NVME_FEAT_IRQ_COALESCE = 0x08,
1170 NVME_FEAT_IRQ_CONFIG = 0x09,
1171 NVME_FEAT_WRITE_ATOMIC = 0x0a,
1172 NVME_FEAT_ASYNC_EVENT = 0x0b,
1173 NVME_FEAT_AUTO_PST = 0x0c,
1174 NVME_FEAT_HOST_MEM_BUF = 0x0d,
1175 NVME_FEAT_TIMESTAMP = 0x0e,
1176 NVME_FEAT_KATO = 0x0f,
1177 NVME_FEAT_HCTM = 0x10,
1178 NVME_FEAT_NOPSC = 0x11,
1179 NVME_FEAT_RRL = 0x12,
1180 NVME_FEAT_PLM_CONFIG = 0x13,
1181 NVME_FEAT_PLM_WINDOW = 0x14,
1182 NVME_FEAT_HOST_BEHAVIOR = 0x16,
1183 NVME_FEAT_SANITIZE = 0x17,
1184 NVME_FEAT_SW_PROGRESS = 0x80,
1185 NVME_FEAT_HOST_ID = 0x81,
1186 NVME_FEAT_RESV_MASK = 0x82,
1187 NVME_FEAT_RESV_PERSIST = 0x83,
1188 NVME_FEAT_WRITE_PROTECT = 0x84,
1189 NVME_FEAT_VENDOR_START = 0xC0,
1190 NVME_FEAT_VENDOR_END = 0xFF,
1191 NVME_LOG_ERROR = 0x01,
1192 NVME_LOG_SMART = 0x02,
1193 NVME_LOG_FW_SLOT = 0x03,
1194 NVME_LOG_CHANGED_NS = 0x04,
1195 NVME_LOG_CMD_EFFECTS = 0x05,
1196 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1197 NVME_LOG_TELEMETRY_HOST = 0x07,
1198 NVME_LOG_TELEMETRY_CTRL = 0x08,
1199 NVME_LOG_ENDURANCE_GROUP = 0x09,
1200 NVME_LOG_ANA = 0x0c,
1201 NVME_LOG_DISC = 0x70,
1202 NVME_LOG_RESERVATION = 0x80,
1203 NVME_FWACT_REPL = (0 << 3),
1204 NVME_FWACT_REPL_ACTV = (1 << 3),
1205 NVME_FWACT_ACTV = (2 << 3),
1206 };
1207
1208 /* NVMe Namespace Write Protect State */
1209 enum {
1210 NVME_NS_NO_WRITE_PROTECT = 0,
1211 NVME_NS_WRITE_PROTECT,
1212 NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1213 NVME_NS_WRITE_PROTECT_PERMANENT,
1214 };
1215
1216 #define NVME_MAX_CHANGED_NAMESPACES 1024
1217
1218 struct nvme_identify {
1219 __u8 opcode;
1220 __u8 flags;
1221 __u16 command_id;
1222 __le32 nsid;
1223 __u64 rsvd2[2];
1224 union nvme_data_ptr dptr;
1225 __u8 cns;
1226 __u8 rsvd3;
1227 __le16 ctrlid;
1228 __u8 rsvd11[3];
1229 __u8 csi;
1230 __u32 rsvd12[4];
1231 };
1232
1233 #define NVME_IDENTIFY_DATA_SIZE 4096
1234
1235 struct nvme_features {
1236 __u8 opcode;
1237 __u8 flags;
1238 __u16 command_id;
1239 __le32 nsid;
1240 __u64 rsvd2[2];
1241 union nvme_data_ptr dptr;
1242 __le32 fid;
1243 __le32 dword11;
1244 __le32 dword12;
1245 __le32 dword13;
1246 __le32 dword14;
1247 __le32 dword15;
1248 };
1249
1250 struct nvme_host_mem_buf_desc {
1251 __le64 addr;
1252 __le32 size;
1253 __u32 rsvd;
1254 };
1255
1256 struct nvme_create_cq {
1257 __u8 opcode;
1258 __u8 flags;
1259 __u16 command_id;
1260 __u32 rsvd1[5];
1261 __le64 prp1;
1262 __u64 rsvd8;
1263 __le16 cqid;
1264 __le16 qsize;
1265 __le16 cq_flags;
1266 __le16 irq_vector;
1267 __u32 rsvd12[4];
1268 };
1269
1270 struct nvme_create_sq {
1271 __u8 opcode;
1272 __u8 flags;
1273 __u16 command_id;
1274 __u32 rsvd1[5];
1275 __le64 prp1;
1276 __u64 rsvd8;
1277 __le16 sqid;
1278 __le16 qsize;
1279 __le16 sq_flags;
1280 __le16 cqid;
1281 __u32 rsvd12[4];
1282 };
1283
1284 struct nvme_delete_queue {
1285 __u8 opcode;
1286 __u8 flags;
1287 __u16 command_id;
1288 __u32 rsvd1[9];
1289 __le16 qid;
1290 __u16 rsvd10;
1291 __u32 rsvd11[5];
1292 };
1293
1294 struct nvme_abort_cmd {
1295 __u8 opcode;
1296 __u8 flags;
1297 __u16 command_id;
1298 __u32 rsvd1[9];
1299 __le16 sqid;
1300 __u16 cid;
1301 __u32 rsvd11[5];
1302 };
1303
1304 struct nvme_download_firmware {
1305 __u8 opcode;
1306 __u8 flags;
1307 __u16 command_id;
1308 __u32 rsvd1[5];
1309 union nvme_data_ptr dptr;
1310 __le32 numd;
1311 __le32 offset;
1312 __u32 rsvd12[4];
1313 };
1314
1315 struct nvme_format_cmd {
1316 __u8 opcode;
1317 __u8 flags;
1318 __u16 command_id;
1319 __le32 nsid;
1320 __u64 rsvd2[4];
1321 __le32 cdw10;
1322 __u32 rsvd11[5];
1323 };
1324
1325 struct nvme_get_log_page_command {
1326 __u8 opcode;
1327 __u8 flags;
1328 __u16 command_id;
1329 __le32 nsid;
1330 __u64 rsvd2[2];
1331 union nvme_data_ptr dptr;
1332 __u8 lid;
1333 __u8 lsp; /* upper 4 bits reserved */
1334 __le16 numdl;
1335 __le16 numdu;
1336 __u16 rsvd11;
1337 union {
1338 struct {
1339 __le32 lpol;
1340 __le32 lpou;
1341 };
1342 __le64 lpo;
1343 };
1344 __u8 rsvd14[3];
1345 __u8 csi;
1346 __u32 rsvd15;
1347 };
1348
1349 struct nvme_directive_cmd {
1350 __u8 opcode;
1351 __u8 flags;
1352 __u16 command_id;
1353 __le32 nsid;
1354 __u64 rsvd2[2];
1355 union nvme_data_ptr dptr;
1356 __le32 numd;
1357 __u8 doper;
1358 __u8 dtype;
1359 __le16 dspec;
1360 __u8 endir;
1361 __u8 tdtype;
1362 __u16 rsvd15;
1363
1364 __u32 rsvd16[3];
1365 };
1366
1367 /*
1368 * Fabrics subcommands.
1369 */
1370 enum nvmf_fabrics_opcode {
1371 nvme_fabrics_command = 0x7f,
1372 };
1373
1374 enum nvmf_capsule_command {
1375 nvme_fabrics_type_property_set = 0x00,
1376 nvme_fabrics_type_connect = 0x01,
1377 nvme_fabrics_type_property_get = 0x04,
1378 nvme_fabrics_type_auth_send = 0x05,
1379 nvme_fabrics_type_auth_receive = 0x06,
1380 };
1381
1382 #define nvme_fabrics_type_name(type) { type, #type }
1383 #define show_fabrics_type_name(type) \
1384 __print_symbolic(type, \
1385 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1386 nvme_fabrics_type_name(nvme_fabrics_type_connect), \
1387 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1388 nvme_fabrics_type_name(nvme_fabrics_type_auth_send), \
1389 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
1390
1391 /*
1392 * If not fabrics command, fctype will be ignored.
1393 */
1394 #define show_opcode_name(qid, opcode, fctype) \
1395 ((opcode) == nvme_fabrics_command ? \
1396 show_fabrics_type_name(fctype) : \
1397 ((qid) ? \
1398 show_nvm_opcode_name(opcode) : \
1399 show_admin_opcode_name(opcode)))
1400
1401 struct nvmf_common_command {
1402 __u8 opcode;
1403 __u8 resv1;
1404 __u16 command_id;
1405 __u8 fctype;
1406 __u8 resv2[35];
1407 __u8 ts[24];
1408 };
1409
1410 /*
1411 * The legal cntlid range a NVMe Target will provide.
1412 * Note that cntlid of value 0 is considered illegal in the fabrics world.
1413 * Devices based on earlier specs did not have the subsystem concept;
1414 * therefore, those devices had their cntlid value set to 0 as a result.
1415 */
1416 #define NVME_CNTLID_MIN 1
1417 #define NVME_CNTLID_MAX 0xffef
1418 #define NVME_CNTLID_DYNAMIC 0xffff
1419
1420 #define MAX_DISC_LOGS 255
1421
1422 /* Discovery log page entry flags (EFLAGS): */
1423 enum {
1424 NVME_DISC_EFLAGS_EPCSD = (1 << 1),
1425 NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
1426 };
1427
1428 /* Discovery log page entry */
1429 struct nvmf_disc_rsp_page_entry {
1430 __u8 trtype;
1431 __u8 adrfam;
1432 __u8 subtype;
1433 __u8 treq;
1434 __le16 portid;
1435 __le16 cntlid;
1436 __le16 asqsz;
1437 __le16 eflags;
1438 __u8 resv10[20];
1439 char trsvcid[NVMF_TRSVCID_SIZE];
1440 __u8 resv64[192];
1441 char subnqn[NVMF_NQN_FIELD_LEN];
1442 char traddr[NVMF_TRADDR_SIZE];
1443 union tsas {
1444 char common[NVMF_TSAS_SIZE];
1445 struct rdma {
1446 __u8 qptype;
1447 __u8 prtype;
1448 __u8 cms;
1449 __u8 resv3[5];
1450 __u16 pkey;
1451 __u8 resv10[246];
1452 } rdma;
1453 } tsas;
1454 };
1455
1456 /* Discovery log page header */
1457 struct nvmf_disc_rsp_page_hdr {
1458 __le64 genctr;
1459 __le64 numrec;
1460 __le16 recfmt;
1461 __u8 resv14[1006];
1462 struct nvmf_disc_rsp_page_entry entries[];
1463 };
1464
1465 enum {
1466 NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1467 };
1468
1469 struct nvmf_connect_command {
1470 __u8 opcode;
1471 __u8 resv1;
1472 __u16 command_id;
1473 __u8 fctype;
1474 __u8 resv2[19];
1475 union nvme_data_ptr dptr;
1476 __le16 recfmt;
1477 __le16 qid;
1478 __le16 sqsize;
1479 __u8 cattr;
1480 __u8 resv3;
1481 __le32 kato;
1482 __u8 resv4[12];
1483 };
1484
1485 enum {
1486 NVME_CONNECT_AUTHREQ_ASCR = (1U << 18),
1487 NVME_CONNECT_AUTHREQ_ATR = (1U << 17),
1488 };
1489
1490 struct nvmf_connect_data {
1491 uuid_t hostid;
1492 __le16 cntlid;
1493 char resv4[238];
1494 char subsysnqn[NVMF_NQN_FIELD_LEN];
1495 char hostnqn[NVMF_NQN_FIELD_LEN];
1496 char resv5[256];
1497 };
1498
1499 struct nvmf_property_set_command {
1500 __u8 opcode;
1501 __u8 resv1;
1502 __u16 command_id;
1503 __u8 fctype;
1504 __u8 resv2[35];
1505 __u8 attrib;
1506 __u8 resv3[3];
1507 __le32 offset;
1508 __le64 value;
1509 __u8 resv4[8];
1510 };
1511
1512 struct nvmf_property_get_command {
1513 __u8 opcode;
1514 __u8 resv1;
1515 __u16 command_id;
1516 __u8 fctype;
1517 __u8 resv2[35];
1518 __u8 attrib;
1519 __u8 resv3[3];
1520 __le32 offset;
1521 __u8 resv4[16];
1522 };
1523
1524 struct nvmf_auth_common_command {
1525 __u8 opcode;
1526 __u8 resv1;
1527 __u16 command_id;
1528 __u8 fctype;
1529 __u8 resv2[19];
1530 union nvme_data_ptr dptr;
1531 __u8 resv3;
1532 __u8 spsp0;
1533 __u8 spsp1;
1534 __u8 secp;
1535 __le32 al_tl;
1536 __u8 resv4[16];
1537 };
1538
1539 struct nvmf_auth_send_command {
1540 __u8 opcode;
1541 __u8 resv1;
1542 __u16 command_id;
1543 __u8 fctype;
1544 __u8 resv2[19];
1545 union nvme_data_ptr dptr;
1546 __u8 resv3;
1547 __u8 spsp0;
1548 __u8 spsp1;
1549 __u8 secp;
1550 __le32 tl;
1551 __u8 resv4[16];
1552 };
1553
1554 struct nvmf_auth_receive_command {
1555 __u8 opcode;
1556 __u8 resv1;
1557 __u16 command_id;
1558 __u8 fctype;
1559 __u8 resv2[19];
1560 union nvme_data_ptr dptr;
1561 __u8 resv3;
1562 __u8 spsp0;
1563 __u8 spsp1;
1564 __u8 secp;
1565 __le32 al;
1566 __u8 resv4[16];
1567 };
1568
1569 /* Value for secp */
1570 enum {
1571 NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER = 0xe9,
1572 };
1573
1574 /* Defined value for auth_type */
1575 enum {
1576 NVME_AUTH_COMMON_MESSAGES = 0x00,
1577 NVME_AUTH_DHCHAP_MESSAGES = 0x01,
1578 };
1579
1580 /* Defined messages for auth_id */
1581 enum {
1582 NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE = 0x00,
1583 NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE = 0x01,
1584 NVME_AUTH_DHCHAP_MESSAGE_REPLY = 0x02,
1585 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1 = 0x03,
1586 NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2 = 0x04,
1587 NVME_AUTH_DHCHAP_MESSAGE_FAILURE2 = 0xf0,
1588 NVME_AUTH_DHCHAP_MESSAGE_FAILURE1 = 0xf1,
1589 };
1590
1591 struct nvmf_auth_dhchap_protocol_descriptor {
1592 __u8 authid;
1593 __u8 rsvd;
1594 __u8 halen;
1595 __u8 dhlen;
1596 __u8 idlist[60];
1597 };
1598
1599 enum {
1600 NVME_AUTH_DHCHAP_AUTH_ID = 0x01,
1601 };
1602
1603 /* Defined hash functions for DH-HMAC-CHAP authentication */
1604 enum {
1605 NVME_AUTH_HASH_SHA256 = 0x01,
1606 NVME_AUTH_HASH_SHA384 = 0x02,
1607 NVME_AUTH_HASH_SHA512 = 0x03,
1608 NVME_AUTH_HASH_INVALID = 0xff,
1609 };
1610
1611 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1612 enum {
1613 NVME_AUTH_DHGROUP_NULL = 0x00,
1614 NVME_AUTH_DHGROUP_2048 = 0x01,
1615 NVME_AUTH_DHGROUP_3072 = 0x02,
1616 NVME_AUTH_DHGROUP_4096 = 0x03,
1617 NVME_AUTH_DHGROUP_6144 = 0x04,
1618 NVME_AUTH_DHGROUP_8192 = 0x05,
1619 NVME_AUTH_DHGROUP_INVALID = 0xff,
1620 };
1621
1622 union nvmf_auth_protocol {
1623 struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1624 };
1625
1626 struct nvmf_auth_dhchap_negotiate_data {
1627 __u8 auth_type;
1628 __u8 auth_id;
1629 __le16 rsvd;
1630 __le16 t_id;
1631 __u8 sc_c;
1632 __u8 napd;
1633 union nvmf_auth_protocol auth_protocol[];
1634 };
1635
1636 struct nvmf_auth_dhchap_challenge_data {
1637 __u8 auth_type;
1638 __u8 auth_id;
1639 __u16 rsvd1;
1640 __le16 t_id;
1641 __u8 hl;
1642 __u8 rsvd2;
1643 __u8 hashid;
1644 __u8 dhgid;
1645 __le16 dhvlen;
1646 __le32 seqnum;
1647 /* 'hl' bytes of challenge value */
1648 __u8 cval[];
1649 /* followed by 'dhvlen' bytes of DH value */
1650 };
1651
1652 struct nvmf_auth_dhchap_reply_data {
1653 __u8 auth_type;
1654 __u8 auth_id;
1655 __le16 rsvd1;
1656 __le16 t_id;
1657 __u8 hl;
1658 __u8 rsvd2;
1659 __u8 cvalid;
1660 __u8 rsvd3;
1661 __le16 dhvlen;
1662 __le32 seqnum;
1663 /* 'hl' bytes of response data */
1664 __u8 rval[];
1665 /* followed by 'hl' bytes of Challenge value */
1666 /* followed by 'dhvlen' bytes of DH value */
1667 };
1668
1669 enum {
1670 NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1671 };
1672
1673 struct nvmf_auth_dhchap_success1_data {
1674 __u8 auth_type;
1675 __u8 auth_id;
1676 __le16 rsvd1;
1677 __le16 t_id;
1678 __u8 hl;
1679 __u8 rsvd2;
1680 __u8 rvalid;
1681 __u8 rsvd3[7];
1682 /* 'hl' bytes of response value if 'rvalid' is set */
1683 __u8 rval[];
1684 };
1685
1686 struct nvmf_auth_dhchap_success2_data {
1687 __u8 auth_type;
1688 __u8 auth_id;
1689 __le16 rsvd1;
1690 __le16 t_id;
1691 __u8 rsvd2[10];
1692 };
1693
1694 struct nvmf_auth_dhchap_failure_data {
1695 __u8 auth_type;
1696 __u8 auth_id;
1697 __le16 rsvd1;
1698 __le16 t_id;
1699 __u8 rescode;
1700 __u8 rescode_exp;
1701 };
1702
1703 enum {
1704 NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED = 0x01,
1705 };
1706
1707 enum {
1708 NVME_AUTH_DHCHAP_FAILURE_FAILED = 0x01,
1709 NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE = 0x02,
1710 NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH = 0x03,
1711 NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE = 0x04,
1712 NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE = 0x05,
1713 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD = 0x06,
1714 NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE = 0x07,
1715 };
1716
1717
1718 struct nvme_dbbuf {
1719 __u8 opcode;
1720 __u8 flags;
1721 __u16 command_id;
1722 __u32 rsvd1[5];
1723 __le64 prp1;
1724 __le64 prp2;
1725 __u32 rsvd12[6];
1726 };
1727
1728 struct streams_directive_params {
1729 __le16 msl;
1730 __le16 nssa;
1731 __le16 nsso;
1732 __u8 rsvd[10];
1733 __le32 sws;
1734 __le16 sgs;
1735 __le16 nsa;
1736 __le16 nso;
1737 __u8 rsvd2[6];
1738 };
1739
1740 struct nvme_command {
1741 union {
1742 struct nvme_common_command common;
1743 struct nvme_rw_command rw;
1744 struct nvme_identify identify;
1745 struct nvme_features features;
1746 struct nvme_create_cq create_cq;
1747 struct nvme_create_sq create_sq;
1748 struct nvme_delete_queue delete_queue;
1749 struct nvme_download_firmware dlfw;
1750 struct nvme_format_cmd format;
1751 struct nvme_dsm_cmd dsm;
1752 struct nvme_write_zeroes_cmd write_zeroes;
1753 struct nvme_zone_mgmt_send_cmd zms;
1754 struct nvme_zone_mgmt_recv_cmd zmr;
1755 struct nvme_abort_cmd abort;
1756 struct nvme_get_log_page_command get_log_page;
1757 struct nvmf_common_command fabrics;
1758 struct nvmf_connect_command connect;
1759 struct nvmf_property_set_command prop_set;
1760 struct nvmf_property_get_command prop_get;
1761 struct nvmf_auth_common_command auth_common;
1762 struct nvmf_auth_send_command auth_send;
1763 struct nvmf_auth_receive_command auth_receive;
1764 struct nvme_dbbuf dbbuf;
1765 struct nvme_directive_cmd directive;
1766 };
1767 };
1768
nvme_is_fabrics(struct nvme_command * cmd)1769 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1770 {
1771 return cmd->common.opcode == nvme_fabrics_command;
1772 }
1773
1774 struct nvme_error_slot {
1775 __le64 error_count;
1776 __le16 sqid;
1777 __le16 cmdid;
1778 __le16 status_field;
1779 __le16 param_error_location;
1780 __le64 lba;
1781 __le32 nsid;
1782 __u8 vs;
1783 __u8 resv[3];
1784 __le64 cs;
1785 __u8 resv2[24];
1786 };
1787
nvme_is_write(struct nvme_command * cmd)1788 static inline bool nvme_is_write(struct nvme_command *cmd)
1789 {
1790 /*
1791 * What a mess...
1792 *
1793 * Why can't we simply have a Fabrics In and Fabrics out command?
1794 */
1795 if (unlikely(nvme_is_fabrics(cmd)))
1796 return cmd->fabrics.fctype & 1;
1797 return cmd->common.opcode & 1;
1798 }
1799
1800 enum {
1801 /*
1802 * Generic Command Status:
1803 */
1804 NVME_SC_SUCCESS = 0x0,
1805 NVME_SC_INVALID_OPCODE = 0x1,
1806 NVME_SC_INVALID_FIELD = 0x2,
1807 NVME_SC_CMDID_CONFLICT = 0x3,
1808 NVME_SC_DATA_XFER_ERROR = 0x4,
1809 NVME_SC_POWER_LOSS = 0x5,
1810 NVME_SC_INTERNAL = 0x6,
1811 NVME_SC_ABORT_REQ = 0x7,
1812 NVME_SC_ABORT_QUEUE = 0x8,
1813 NVME_SC_FUSED_FAIL = 0x9,
1814 NVME_SC_FUSED_MISSING = 0xa,
1815 NVME_SC_INVALID_NS = 0xb,
1816 NVME_SC_CMD_SEQ_ERROR = 0xc,
1817 NVME_SC_SGL_INVALID_LAST = 0xd,
1818 NVME_SC_SGL_INVALID_COUNT = 0xe,
1819 NVME_SC_SGL_INVALID_DATA = 0xf,
1820 NVME_SC_SGL_INVALID_METADATA = 0x10,
1821 NVME_SC_SGL_INVALID_TYPE = 0x11,
1822 NVME_SC_CMB_INVALID_USE = 0x12,
1823 NVME_SC_PRP_INVALID_OFFSET = 0x13,
1824 NVME_SC_ATOMIC_WU_EXCEEDED = 0x14,
1825 NVME_SC_OP_DENIED = 0x15,
1826 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1827 NVME_SC_RESERVED = 0x17,
1828 NVME_SC_HOST_ID_INCONSIST = 0x18,
1829 NVME_SC_KA_TIMEOUT_EXPIRED = 0x19,
1830 NVME_SC_KA_TIMEOUT_INVALID = 0x1A,
1831 NVME_SC_ABORTED_PREEMPT_ABORT = 0x1B,
1832 NVME_SC_SANITIZE_FAILED = 0x1C,
1833 NVME_SC_SANITIZE_IN_PROGRESS = 0x1D,
1834 NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1835 NVME_SC_CMD_NOT_SUP_CMB_QUEUE = 0x1F,
1836 NVME_SC_NS_WRITE_PROTECTED = 0x20,
1837 NVME_SC_CMD_INTERRUPTED = 0x21,
1838 NVME_SC_TRANSIENT_TR_ERR = 0x22,
1839 NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
1840 NVME_SC_INVALID_IO_CMD_SET = 0x2C,
1841
1842 NVME_SC_LBA_RANGE = 0x80,
1843 NVME_SC_CAP_EXCEEDED = 0x81,
1844 NVME_SC_NS_NOT_READY = 0x82,
1845 NVME_SC_RESERVATION_CONFLICT = 0x83,
1846 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
1847
1848 /*
1849 * Command Specific Status:
1850 */
1851 NVME_SC_CQ_INVALID = 0x100,
1852 NVME_SC_QID_INVALID = 0x101,
1853 NVME_SC_QUEUE_SIZE = 0x102,
1854 NVME_SC_ABORT_LIMIT = 0x103,
1855 NVME_SC_ABORT_MISSING = 0x104,
1856 NVME_SC_ASYNC_LIMIT = 0x105,
1857 NVME_SC_FIRMWARE_SLOT = 0x106,
1858 NVME_SC_FIRMWARE_IMAGE = 0x107,
1859 NVME_SC_INVALID_VECTOR = 0x108,
1860 NVME_SC_INVALID_LOG_PAGE = 0x109,
1861 NVME_SC_INVALID_FORMAT = 0x10a,
1862 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1863 NVME_SC_INVALID_QUEUE = 0x10c,
1864 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1865 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1866 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1867 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1868 NVME_SC_FW_NEEDS_RESET = 0x111,
1869 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1870 NVME_SC_FW_ACTIVATE_PROHIBITED = 0x113,
1871 NVME_SC_OVERLAPPING_RANGE = 0x114,
1872 NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1873 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1874 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1875 NVME_SC_NS_IS_PRIVATE = 0x119,
1876 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1877 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1878 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1879 NVME_SC_SELT_TEST_IN_PROGRESS = 0x11d,
1880 NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1881 NVME_SC_CTRL_ID_INVALID = 0x11f,
1882 NVME_SC_SEC_CTRL_STATE_INVALID = 0x120,
1883 NVME_SC_CTRL_RES_NUM_INVALID = 0x121,
1884 NVME_SC_RES_ID_INVALID = 0x122,
1885 NVME_SC_PMR_SAN_PROHIBITED = 0x123,
1886 NVME_SC_ANA_GROUP_ID_INVALID = 0x124,
1887 NVME_SC_ANA_ATTACH_FAILED = 0x125,
1888
1889 /*
1890 * I/O Command Set Specific - NVM commands:
1891 */
1892 NVME_SC_BAD_ATTRIBUTES = 0x180,
1893 NVME_SC_INVALID_PI = 0x181,
1894 NVME_SC_READ_ONLY = 0x182,
1895 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1896
1897 /*
1898 * I/O Command Set Specific - Fabrics commands:
1899 */
1900 NVME_SC_CONNECT_FORMAT = 0x180,
1901 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1902 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1903 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1904 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1905
1906 NVME_SC_DISCOVERY_RESTART = 0x190,
1907 NVME_SC_AUTH_REQUIRED = 0x191,
1908
1909 /*
1910 * I/O Command Set Specific - Zoned commands:
1911 */
1912 NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1913 NVME_SC_ZONE_FULL = 0x1b9,
1914 NVME_SC_ZONE_READ_ONLY = 0x1ba,
1915 NVME_SC_ZONE_OFFLINE = 0x1bb,
1916 NVME_SC_ZONE_INVALID_WRITE = 0x1bc,
1917 NVME_SC_ZONE_TOO_MANY_ACTIVE = 0x1bd,
1918 NVME_SC_ZONE_TOO_MANY_OPEN = 0x1be,
1919 NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1920
1921 /*
1922 * Media and Data Integrity Errors:
1923 */
1924 NVME_SC_WRITE_FAULT = 0x280,
1925 NVME_SC_READ_ERROR = 0x281,
1926 NVME_SC_GUARD_CHECK = 0x282,
1927 NVME_SC_APPTAG_CHECK = 0x283,
1928 NVME_SC_REFTAG_CHECK = 0x284,
1929 NVME_SC_COMPARE_FAILED = 0x285,
1930 NVME_SC_ACCESS_DENIED = 0x286,
1931 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1932
1933 /*
1934 * Path-related Errors:
1935 */
1936 NVME_SC_INTERNAL_PATH_ERROR = 0x300,
1937 NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1938 NVME_SC_ANA_INACCESSIBLE = 0x302,
1939 NVME_SC_ANA_TRANSITION = 0x303,
1940 NVME_SC_CTRL_PATH_ERROR = 0x360,
1941 NVME_SC_HOST_PATH_ERROR = 0x370,
1942 NVME_SC_HOST_ABORTED_CMD = 0x371,
1943
1944 NVME_SC_CRD = 0x1800,
1945 NVME_SC_MORE = 0x2000,
1946 NVME_SC_DNR = 0x4000,
1947 };
1948
1949 struct nvme_completion {
1950 /*
1951 * Used by Admin and Fabrics commands to return data:
1952 */
1953 union nvme_result {
1954 __le16 u16;
1955 __le32 u32;
1956 __le64 u64;
1957 } result;
1958 __le16 sq_head; /* how much of this queue may be reclaimed */
1959 __le16 sq_id; /* submission queue that generated this entry */
1960 __u16 command_id; /* of the command which completed */
1961 __le16 status; /* did the command fail, and if so, why? */
1962 };
1963
1964 #define NVME_VS(major, minor, tertiary) \
1965 (((major) << 16) | ((minor) << 8) | (tertiary))
1966
1967 #define NVME_MAJOR(ver) ((ver) >> 16)
1968 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1969 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1970
1971 #endif /* _LINUX_NVME_H */
1972