| /linux-6.1.9/drivers/mtd/nand/raw/ |
| D | Kconfig | 3 tristate "Raw/Parallel NAND Device Support"
8 NAND flash devices. For further information see
13 comment "Raw/parallel NAND flash controllers"
19 tristate "Denali NAND controller on Intel Moorestown"
23 Enable the driver for NAND flash on Intel Moorestown, using the
24 Denali NAND controller core.
27 tristate "Denali NAND controller as a DT device"
31 Enable the driver for NAND flash on platforms using a Denali NAND
35 tristate "Amstrad E3 NAND controller"
39 Support for NAND flash on Amstrad E3 (Delta).
[all …]
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| /linux-6.1.9/drivers/mtd/nand/raw/brcmnand/ |
| D | Kconfig | 2 tristate "Broadcom STB NAND controller"
6 Enables the Broadcom NAND controller driver. The controller was
13 tristate "Broadcom BCM63xx NAND controller glue"
16 Enables the BRCMNAND glue driver to register the NAND controller
20 tristate "Broadcom BCMA NAND controller"
29 tristate "Broadcom BCMBCA NAND controller glue"
32 Enables the BRCMNAND glue driver to register the NAND controller
39 Enables the BRCMNAND glue driver to register the NAND controller
43 tristate "Broadcom iProc NAND controller glue"
46 Enables the BRCMNAND controller glue driver to register the NAND
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| /linux-6.1.9/Documentation/devicetree/bindings/mtd/ |
| D | nand-chip.yaml | 7 title: NAND Chip and NAND Controller Generic Binding
13 This file covers the generic description of a NAND chip. It implies that the
14 bus interface should not be taken into account: both raw NAND devices and
15 SPI-NAND devices are concerned by this description.
26 1/ The ECC engine is part of the NAND controller, in this
28 2/ The ECC engine is part of the NAND part (on-die), in this
62 Regions in the NAND chip which are protected using a secure element
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| D | mtk-nand.txt | 1 MTK SoCs NAND FLASH controller (NFC) DT binding
3 This file documents the device tree bindings for MTK SoCs NAND controllers.
10 1) NFC NAND Controller Interface (NFI):
13 The first part of NFC is NAND Controller Interface (NFI) HW.
24 - #address-cells: NAND chip index, should be 1.
42 - children nodes: NAND chips.
48 - nand-on-flash-bbt: Store BBT on NAND Flash.
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
74 According to MTK NAND controller design,
76 that MTK NAND controller supports.
[all …]
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| D | brcm,brcmnand.yaml | 7 title: Broadcom STB NAND Controller
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
25 -- Additional SoC-specific NAND controller properties --
27 The NAND controller is integrated differently on the variety of SoCs on which
29 bits with which to control the 8 exposed NAND interrupts, as well as hardware
33 interesting ways, sometimes with registers that lump multiple NAND-related
37 register resources within the NAND controller node above.
56 - description: BCM63138 SoC-specific NAND controller
63 - description: iProc SoC-specific NAND controller
68 - description: BCM63168 SoC-specific NAND controller
[all …]
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| D | oxnas-nand.txt | 1 * Oxford Semiconductor OXNAS NAND Controller
3 Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.
7 - reg: Base address and length for NAND mapped memory.
10 - clocks: phandle to the NAND gate clock if needed.
11 - resets: phandle to the NAND reset control if needed.
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| D | nand-controller.yaml | 7 title: NAND Chip and NAND Controller Generic Binding
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
45 NAND controller (even if they are not used). As many additional
47 lines. 'reg' entries of the NAND chip subnodes become indexes of
73 Bus width to the NAND chip
97 want to make your NAND as reliable as possible.
102 Whether or not the NAND chip is a boot medium. Drivers might
116 Ready/Busy pins. Active state refers to the NAND ready state and
[all …]
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| D | atmel-nand.txt | 1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
30 * NAND device/chip bindings:
33 - reg: describes the CS lines assigned to the NAND device. If the NAND device
36 1st entry: the CS line this NAND chip is connected to
42 - rb-gpios: the GPIO(s) used to check the Ready/Busy status of the NAND.
49 Documentation/devicetree/bindings/mtd/{common,nand}.txt also apply to the NAND
[all …]
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| D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
41 Optional child node of NAND chip nodes:
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| D | fsmc-nand.txt | 2 NAND Interface
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
47 0xd2000000 0x0010 /* NAND Base DATA */
48 0xd2020000 0x0010 /* NAND Base ADDR */
49 0xd2010000 0x0010>; /* NAND Base CMD */
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| D | ti,gpmc-nand.yaml | 7 title: Texas Instruments GPMC NAND Flash controller.
14 GPMC NAND controller/Flash is represented as a child of the
54 Bus width to the NAND chip
61 GPIO connection to R/B signal from NAND chip
113 /* NAND generic properties */
121 label = "NAND.SPL";
125 label = "NAND.SPL.backup1";
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| D | gpio-control-nand.txt | 1 GPIO assisted NAND flash
3 The GPIO assisted NAND flash uses a memory mapped interface to
4 read/write the NAND commands and data and GPIO pins for the control
10 resource describes the data bus connected to the NAND flash and all accesses
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
24 the GPIO's and the NAND flash data bus. If present, then after changing
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| D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
16 - interrupts: shall define the NAND controller interrupt.
17 - clocks: shall reference the NAND controller clocks, the second one is
22 NAND controller related registers (only required with the
27 - dmas: shall reference DMA channel associated to the NAND controller.
35 Children nodes represent the available NAND chips.
52 the NAND chip. This value may be overwritten with nand-ecc-strength
55 - nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
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| D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
15 in a board stuffing. Typical NAND memory timings derived from this
24 only handle one NAND chip.
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| D | davinci-nand.txt | 1 Device tree bindings for Texas instruments Davinci/Keystone NAND controller
4 NAND interface contains.
29 address for the chip select space the NAND Flash
35 address for the chip select space the NAND Flash
42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
58 - ti,davinci-ecc-mode: operation mode of the NAND ecc mode. ECC mode
71 the address space. See partition.txt for more detail. The NAND Flash timing
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| D | lpc32xx-mlc.txt | 1 NXP LPC32xx SoC NAND MLC controller
6 - interrupts: The NAND interrupt specification
7 - gpios: GPIO specification for NAND write protect
10 User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
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| /linux-6.1.9/drivers/pinctrl/tegra/ |
| D | pinctrl-tegra30.c | 2197 …PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, 0x31c0, N, …
2222 …PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, 0x31f0, N, …
2223 …PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, 0x31f4, N, …
2224 …PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, 0x31f8, N, …
2225 …PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, 0x31fc, N, …
2226 …PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, 0x3200, N, …
2227 …PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, RSVD4, 0x3204, N, …
2228 …PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, RSVD4, 0x3208, N, …
2229 …PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, RSVD4, 0x320c, N, …
2230 …PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, RSVD4, 0x3210, N, …
[all …]
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| /linux-6.1.9/Documentation/arm/samsung-s3c24xx/ |
| D | nand.rst | 2 S3C24XX NAND Support
8 Small Page NAND
15 Large Page NAND
18 The driver is capable of handling NAND flash with a 2KiB page
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| /linux-6.1.9/arch/powerpc/boot/dts/fsl/ |
| D | p1010rdb-pa.dtsi | 40 label = "NAND U-Boot Image";
47 label = "NAND DTB Image";
53 label = "NAND Linux Kernel Image";
59 label = "NAND Compressed RFS Image";
65 label = "NAND JFFS2 Root File System";
71 label = "NAND User area";
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| /linux-6.1.9/arch/arm64/boot/dts/marvell/ |
| D | cn9130-db.dts | 14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When SPI controller is enabled, NAND should be disabled.
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| D | cn9132-db-B.dts | 14 /* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
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| D | cn9132-db.dts | 14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When SPI controller is enabled, NAND should be disabled.
|
| D | cn9131-db.dts | 14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When SPI controller is enabled, NAND should be disabled.
|
| D | cn9130-db-B.dts | 14 /* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
|
| D | cn9131-db-B.dts | 14 /* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
|