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Searched refs:MinClock (Results 1 – 25 of 31) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_smu11_driver_if.h24 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
Ddcn30_clk_mgr.c343 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/inc/
Dsmu10_driver_if.h51 uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */ member
Dsmu9_driver_if.h328 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
Dsmu11_driver_if.h679 uint16_t MinClock; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
Ddcn316_clk_mgr.c369 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges()
385 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges()
398 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn316_build_watermark_ranges()
404 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn316_build_watermark_ranges()
Ddcn316_smu.h41 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu13_driver_if_v13_0_5.h52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
Dsmu12_driver_if.h51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
Dsmu13_driver_if_yellow_carp.h50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
Dsmu11_driver_if_vangogh.h50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
Dsmu13_driver_if_v13_0_4.h51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
Ddcn315_smu.h42 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
Ddcn315_clk_mgr.c377 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges()
393 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges()
406 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn315_build_watermark_ranges()
412 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn315_build_watermark_ranges()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.c402 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
418 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
431 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in vg_build_watermark_ranges()
437 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in vg_build_watermark_ranges()
Ddcn301_smu.h56 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_clk_mgr.c433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
449 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
462 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn31_build_watermark_ranges()
468 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn31_build_watermark_ranges()
Ddcn31_smu.h52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
Ddcn314_clk_mgr.c452 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
468 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
481 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn314_build_watermark_ranges()
487 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn314_build_watermark_ranges()
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu_helper.h36 uint16_t MinClock; member
Dsmu_helper.c737 table->WatermarkRow[1][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
758 table->WatermarkRow[0][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dsmu_v13_0_4_ppt.c646 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
660 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
Dsmu_v13_0_5_ppt.c415 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
429 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
Dyellow_carp_ppt.c498 table->WatermarkRow[WM_DCFCLK][i].MinClock = in yellow_carp_set_watermarks_table()
512 table->WatermarkRow[WM_SOCCLK][i].MinClock = in yellow_carp_set_watermarks_table()
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/
Dsmu9_driver_if.h572 uint16_t MinClock; member

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