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Searched refs:MUX (Results 1 – 25 of 107) sorted by relevance

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/linux-6.1.9/drivers/clk/samsung/
Dclk-exynos5420.c470 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
471 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
472 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
473 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
475 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
476 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
477 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
478 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
479 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
481 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
[all …]
Dclk-exynos4.c422 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
423 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
424 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
429 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
430 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
431 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
432 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
434 MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
435 MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
440 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
[all …]
Dclk-s5pv210.c375 MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1),
376 MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1),
377 MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1),
378 MUX(MOUT_MSYS, "mout_msys", mout_group3_p, CLK_SRC0, 16, 1),
379 MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1),
380 MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1),
381 MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1),
383 MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2),
388 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1),
390 MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1),
[all …]
Dclk-exynos7.c89 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
91 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
93 MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
95 MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
97 MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
99 MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
101 MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
103 MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
106 MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
108 MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
[all …]
Dclk-exynos5260.c93 MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p,
95 MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p,
97 MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
202 MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
205 MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user",
208 MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user",
211 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER,
215 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER,
219 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER,
223 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER,
[all …]
Dclk-exynos5250.c242 MUX(CLK_MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),
258 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
263 MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
268 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
269 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
270 MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
271 MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
272 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
273 MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
275 MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
[all …]
Dclk-exynos5410.c87 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
88 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
90 MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
91 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
93 MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
94 MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
96 MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
97 MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
99 MUX(0, "sclk_epll", epll_p, SRC_TOP2, 12, 1),
101 MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
[all …]
Dclk-exynosautov9.c433 MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
435 MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
437 MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p,
439 MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p,
441 MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p,
445 MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost",
447 MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref",
451 MUX(MOUT_CLKCMU_ACC_BUS, "mout_clkcmu_acc_bus", mout_clkcmu_acc_bus_p,
455 MUX(MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus", mout_clkcmu_apm_bus_p,
459 MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu", mout_clkcmu_aud_cpu_p,
[all …]
Dclk-exynos850.c257 MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
259 MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
261 MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
265 MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
269 MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p,
273 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
275 MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
277 MUX(CLK_MOUT_CORE_MMC_EMBD, "mout_core_mmc_embd", mout_core_mmc_embd_p,
279 MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
283 MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
[all …]
Dclk-exynos3250.c247 MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p,
249 MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
252 MUX(CLK_MOUT_MPLL_USER_R, "mout_mpll_user_r", mout_mpll_user_p,
254 MUX(CLK_MOUT_GDR, "mout_gdr", mout_gdr_p, SRC_RIGHTBUS, 0, 1),
257 MUX(CLK_MOUT_EBI, "mout_ebi", mout_ebi_p, SRC_TOP0, 28, 1),
258 MUX(CLK_MOUT_ACLK_200, "mout_aclk_200", group_div_mpll_pre_p,SRC_TOP0, 24, 1),
259 MUX(CLK_MOUT_ACLK_160, "mout_aclk_160", group_div_mpll_pre_p, SRC_TOP0, 20, 1),
260 MUX(CLK_MOUT_ACLK_100, "mout_aclk_100", group_div_mpll_pre_p, SRC_TOP0, 16, 1),
261 MUX(CLK_MOUT_ACLK_266_1, "mout_aclk_266_1", mout_aclk_266_1_p, SRC_TOP0, 14, 1),
262 MUX(CLK_MOUT_ACLK_266_0, "mout_aclk_266_0", mout_aclk_266_0_p, SRC_TOP0, 13, 1),
[all …]
Dclk-exynos7885.c188 MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
190 MUX(CLK_MOUT_CORE_CCI, "mout_core_cci", mout_core_cci_p,
192 MUX(CLK_MOUT_CORE_G3D, "mout_core_g3d", mout_core_g3d_p,
196 MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
198 MUX(CLK_MOUT_PERI_SPI0, "mout_peri_spi0", mout_peri_spi0_p,
200 MUX(CLK_MOUT_PERI_SPI1, "mout_peri_spi1", mout_peri_spi1_p,
202 MUX(CLK_MOUT_PERI_UART0, "mout_peri_uart0", mout_peri_uart0_p,
204 MUX(CLK_MOUT_PERI_UART1, "mout_peri_uart1", mout_peri_uart1_p,
206 MUX(CLK_MOUT_PERI_UART2, "mout_peri_uart2", mout_peri_uart2_p,
208 MUX(CLK_MOUT_PERI_USI0, "mout_peri_usi0", mout_peri_usi0_p,
[all …]
Dclk-exynos5433.c258 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
260 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
264 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
266 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
268 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
270 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
274 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
276 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
278 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
280 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
[all …]
Dclk-s3c64xx.c126 MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1),
127 MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1),
128 MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
129 MUX(MOUT_MFC, "mout_mfc", mfc_p, CLK_SRC, 4, 1),
130 MUX(MOUT_AUDIO0, "mout_audio0", audio0_p, CLK_SRC, 7, 3),
131 MUX(MOUT_AUDIO1, "mout_audio1", audio1_p, CLK_SRC, 10, 3),
132 MUX(MOUT_UART, "mout_uart", uart_p, CLK_SRC, 13, 1),
133 MUX(MOUT_SPI0, "mout_spi0", spi_mmc_p, CLK_SRC, 14, 2),
134 MUX(MOUT_SPI1, "mout_spi1", spi_mmc_p, CLK_SRC, 16, 2),
135 MUX(MOUT_MMC0, "mout_mmc0", spi_mmc_p, CLK_SRC, 18, 2),
[all …]
Dclk-s3c2412.c88 MUX(0, "erefclk", erefclk_p, CLKSRC, 14, 2),
89 MUX(0, "urefclk", urefclk_p, CLKSRC, 12, 2),
90 MUX(0, "mux_cam", camclk_p, CLKSRC, 11, 1),
91 MUX(0, "mux_usb", usbclk_p, CLKSRC, 10, 1),
92 MUX(0, "mux_i2s", i2sclk_p, CLKSRC, 9, 1),
93 MUX(0, "mux_uart", uartclk_p, CLKSRC, 8, 1),
94 MUX(USYSCLK, "usysclk", usysclk_p, CLKSRC, 5, 1),
95 MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
96 MUX(MDIVCLK, "mdivclk", mdivclk_p, CLKSRC, 3, 1),
97 MUX(ARMCLK, "armclk", armclk_p, CLKDIVN, 4, 1),
Dclk-fsd.c191 MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1),
192 MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1),
193 MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1),
194 MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1),
195 MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1),
196 MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1),
197 MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1),
198 MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p,
200 MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1),
201 MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1),
[all …]
Dclk-s3c2443.c71 MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
72 MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
73 MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
74 MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
75 MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
76 MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
207 MUX(MUX_HSMMC0, "mux_hsmmc0", s3c2416_hsmmc0_p, CLKSRC, 16, 1),
208 MUX(MUX_HSMMC1, "mux_hsmmc1", s3c2416_hsmmc1_p, CLKSRC, 17, 1),
209 MUX(MUX_HSSPI0, "mux_hsspi0", s3c2416_hsspi0_p, CLKSRC, 18, 1),
288 MUX(0, "mux_cam", s3c2450_cam_p, CLKSRC, 20, 1),
[all …]
/linux-6.1.9/drivers/clk/mediatek/
Dclk-mt8167.c524 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
526 MUX(CLK_TOP_GFMUX_EMI1X_SEL, "gfmux_emi1x_sel", gfmux_emi1x_parents,
528 MUX(CLK_TOP_EMI_DDRPHY_SEL, "emi_ddrphy_sel", emi_ddrphy_parents,
530 MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
532 MUX(CLK_TOP_CSW_MUX_MFG_SEL, "csw_mux_mfg_sel", csw_mux_mfg_parents,
534 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
536 MUX(CLK_TOP_CAMTG_MM_SEL, "camtg_mm_sel", camtg_mm_parents,
538 MUX(CLK_TOP_PWM_MM_SEL, "pwm_mm_sel", pwm_mm_parents,
540 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
542 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
[all …]
Dclk-mt8516.c364 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
366 MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
368 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
370 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
372 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
374 MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
376 MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
378 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
381 MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
383 MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
[all …]
Dclk-mt6797.c325 MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
327 MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
329 MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
333 MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
342 MUX(CLK_TOP_MUX_ULPOSC_SPI_CK_MUX, "ulposc_spi_ck_mux",
346 MUX(CLK_TOP_MUX_MSDC50_0_HCLK, "msdc50_0_hclk_sel",
356 MUX(CLK_TOP_MUX_AUD_INTBUS, "aud_intbus_sel", aud_intbus_parents,
358 MUX(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents,
360 MUX(CLK_TOP_MUX_SCP, "scp_sel", scp_parents,
362 MUX(CLK_TOP_MUX_ATB, "atb_sel", atb_parents,
[all …]
/linux-6.1.9/drivers/clk/tegra/
Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ macro
639 …MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_…
640 …MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_…
641 …MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_…
642 …MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk…
643 …MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk…
644 …MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, t…
645 …MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_…
647 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm),
648 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
[all …]
/linux-6.1.9/drivers/clk/pistachio/
Dclk-pistachio.c124 MUX(CLK_AUDIO_REF_MUX, "audio_refclk_mux", mux_xtal_audio_refclk,
126 MUX(CLK_MIPS_PLL_MUX, "mips_pll_mux", mux_xtal_mips, 0x200, 1),
127 MUX(CLK_AUDIO_PLL_MUX, "audio_pll_mux", mux_xtal_audio, 0x200, 2),
128 MUX(CLK_AUDIO_MUX, "audio_mux", mux_audio_debug, 0x200, 4),
129 MUX(CLK_RPU_V_PLL_MUX, "rpu_v_pll_mux", mux_xtal_rpu_v, 0x200, 5),
130 MUX(CLK_RPU_L_PLL_MUX, "rpu_l_pll_mux", mux_xtal_rpu_l, 0x200, 6),
131 MUX(CLK_RPU_L_MUX, "rpu_l_mux", mux_rpu_l_mips, 0x200, 7),
132 MUX(CLK_WIFI_PLL_MUX, "wifi_pll_mux", mux_xtal_wifi, 0x200, 8),
133 MUX(CLK_WIFI_DIV4_MUX, "wifi_div4_mux", mux_xtal_wifi_div4, 0x200, 9),
134 MUX(CLK_WIFI_DIV8_MUX, "wifi_div8_mux", mux_xtal_wifi_div8, 0x200, 10),
[all …]
/linux-6.1.9/Documentation/i2c/
Di2c-sysfs.rst10 I2C topology can be complex because of the existence of I2C MUX
12 kernel abstracts the MUX channels into logical I2C bus numbers. However, there
13 is a gap of knowledge to map from the I2C bus physical number and MUX topology
32 2. General knowledge of I2C, I2C MUX and I2C topology.
85 an abstraction of a channel behind an I2C MUX. In case it is an abstraction of a
86 MUX channel, whenever we access an I2C device via a such logical bus, the kernel
87 will switch the I2C MUX for you to the proper channel as part of the
109 MUX fanouts. For the following examples, we will assume that the physical I2C
123 `-- 7-0071 (4-channel I2C MUX at 0x71)
127 | |-- 73-0070 (I2C MUX at 0x70, exists in DTS, but failed to probe)
[all …]
/linux-6.1.9/drivers/clk/rockchip/
Dclk-rk3308.c199 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
203 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
207 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
211 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
215 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
219 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
223 MUX(SCLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
227 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
231 MUX(SCLK_I2S0_8CH_TX_MUX, "clk_i2s0_8ch_tx_mux", mux_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
235 MUX(SCLK_I2S0_8CH_RX_MUX, "clk_i2s0_8ch_rx_mux", mux_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
[all …]
Dclk-rk3568.c346 MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
350 MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
354 MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
358 MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
362 MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,
366 MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, CLK_SET_RATE_PARENT,
370 MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, CLK_SET_RATE_PARENT,
374 MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, CLK_SET_RATE_PARENT,
378 MUX(SCLK_AUDPWM, "sclk_audpwm", sclk_audpwm_p, CLK_SET_RATE_PARENT,
382 MUX(0, "sclk_uart1_mux", sclk_uart1_p, CLK_SET_RATE_PARENT,
[all …]
Dclk-rk3188.c252 MUX(0, "sclk_hsadc_out", mux_sclk_hsadc_p, 0,
256 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
260 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, CLK_SET_RATE_PARENT,
264 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, CLK_SET_RATE_PARENT,
268 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, CLK_SET_RATE_PARENT,
272 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT,
330 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
335 MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
357 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
408 MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
[all …]

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