1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 *
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
7 */
8
9 #ifndef MTK_ETH_H
10 #define MTK_ETH_H
11
12 #include <linux/dma-mapping.h>
13 #include <linux/netdevice.h>
14 #include <linux/of_net.h>
15 #include <linux/u64_stats_sync.h>
16 #include <linux/refcount.h>
17 #include <linux/phylink.h>
18 #include <linux/rhashtable.h>
19 #include <linux/dim.h>
20 #include <linux/bitfield.h>
21 #include <net/page_pool.h>
22 #include <linux/bpf_trace.h>
23 #include "mtk_ppe.h"
24
25 #define MTK_QDMA_PAGE_SIZE 2048
26 #define MTK_MAX_RX_LENGTH 1536
27 #define MTK_MAX_RX_LENGTH_2K 2048
28 #define MTK_TX_DMA_BUF_LEN 0x3fff
29 #define MTK_TX_DMA_BUF_LEN_V2 0xffff
30 #define MTK_DMA_SIZE 512
31 #define MTK_MAC_COUNT 2
32 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN)
33 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
34 #define MTK_DMA_DUMMY_DESC 0xffffffff
35 #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
36 NETIF_MSG_PROBE | \
37 NETIF_MSG_LINK | \
38 NETIF_MSG_TIMER | \
39 NETIF_MSG_IFDOWN | \
40 NETIF_MSG_IFUP | \
41 NETIF_MSG_RX_ERR | \
42 NETIF_MSG_TX_ERR)
43 #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \
44 NETIF_F_RXCSUM | \
45 NETIF_F_HW_VLAN_CTAG_TX | \
46 NETIF_F_HW_VLAN_CTAG_RX | \
47 NETIF_F_SG | NETIF_F_TSO | \
48 NETIF_F_TSO6 | \
49 NETIF_F_IPV6_CSUM |\
50 NETIF_F_HW_TC)
51 #define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM)
52 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
53
54 #define MTK_PP_HEADROOM XDP_PACKET_HEADROOM
55 #define MTK_PP_PAD (MTK_PP_HEADROOM + \
56 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
57 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD)
58
59 #define MTK_QRX_OFFSET 0x10
60
61 #define MTK_MAX_RX_RING_NUM 4
62 #define MTK_HW_LRO_DMA_SIZE 8
63
64 #define MTK_MAX_LRO_RX_LENGTH (4096 * 3)
65 #define MTK_MAX_LRO_IP_CNT 2
66 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */
67 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */
68 #define MTK_HW_LRO_AGG_TIME 10 /* 200us */
69 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */
70 #define MTK_HW_LRO_MAX_AGG_CNT 64
71 #define MTK_HW_LRO_BW_THRE 3000
72 #define MTK_HW_LRO_REPLACE_DELTA 1000
73 #define MTK_HW_LRO_SDL_REMAIN_ROOM 1522
74
75 /* Frame Engine Global Reset Register */
76 #define MTK_RST_GL 0x04
77 #define RST_GL_PSE BIT(0)
78
79 /* Frame Engine Interrupt Status Register */
80 #define MTK_INT_STATUS2 0x08
81 #define MTK_GDM1_AF BIT(28)
82 #define MTK_GDM2_AF BIT(29)
83
84 /* PDMA HW LRO Alter Flow Timer Register */
85 #define MTK_PDMA_LRO_ALT_REFRESH_TIMER 0x1c
86
87 /* Frame Engine Interrupt Grouping Register */
88 #define MTK_FE_INT_GRP 0x20
89
90 /* CDMP Ingress Control Register */
91 #define MTK_CDMQ_IG_CTRL 0x1400
92 #define MTK_CDMQ_STAG_EN BIT(0)
93
94 /* CDMP Ingress Control Register */
95 #define MTK_CDMP_IG_CTRL 0x400
96 #define MTK_CDMP_STAG_EN BIT(0)
97
98 /* CDMP Exgress Control Register */
99 #define MTK_CDMP_EG_CTRL 0x404
100
101 /* GDM Exgress Control Register */
102 #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
103 #define MTK_GDMA_SPECIAL_TAG BIT(24)
104 #define MTK_GDMA_ICS_EN BIT(22)
105 #define MTK_GDMA_TCS_EN BIT(21)
106 #define MTK_GDMA_UCS_EN BIT(20)
107 #define MTK_GDMA_TO_PDMA 0x0
108 #define MTK_GDMA_DROP_ALL 0x7777
109
110 /* Unicast Filter MAC Address Register - Low */
111 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
112
113 /* Unicast Filter MAC Address Register - High */
114 #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
115
116 /* FE global misc reg*/
117 #define MTK_FE_GLO_MISC 0x124
118
119 /* PSE Free Queue Flow Control */
120 #define PSE_FQFC_CFG1 0x100
121 #define PSE_FQFC_CFG2 0x104
122 #define PSE_DROP_CFG 0x108
123 #define PSE_PPE0_DROP 0x110
124
125 /* PSE Input Queue Reservation Register*/
126 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2))
127
128 /* PSE Output Queue Threshold Register*/
129 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2))
130
131 /* GDM and CDM Threshold */
132 #define MTK_GDM2_THRES 0x1530
133 #define MTK_CDMW0_THRES 0x164c
134 #define MTK_CDMW1_THRES 0x1650
135 #define MTK_CDME0_THRES 0x1654
136 #define MTK_CDME1_THRES 0x1658
137 #define MTK_CDMM_THRES 0x165c
138
139 /* PDMA HW LRO Control Registers */
140 #define MTK_PDMA_LRO_CTRL_DW0 0x980
141 #define MTK_LRO_EN BIT(0)
142 #define MTK_L3_CKS_UPD_EN BIT(7)
143 #define MTK_L3_CKS_UPD_EN_V2 BIT(19)
144 #define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
145 #define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
146 #define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24)
147 #define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
148 #define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28)
149
150 #define MTK_PDMA_LRO_CTRL_DW1 0x984
151 #define MTK_PDMA_LRO_CTRL_DW2 0x988
152 #define MTK_PDMA_LRO_CTRL_DW3 0x98c
153 #define MTK_ADMA_MODE BIT(15)
154 #define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
155
156 #define MTK_RX_DMA_LRO_EN BIT(8)
157 #define MTK_MULTI_EN BIT(10)
158 #define MTK_PDMA_SIZE_8DWORDS (1 << 4)
159
160 /* PDMA Global Configuration Register */
161 #define MTK_PDMA_LRO_SDL 0x3000
162 #define MTK_RX_CFG_SDL_OFFSET 16
163
164 /* PDMA Reset Index Register */
165 #define MTK_PST_DRX_IDX0 BIT(16)
166 #define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
167
168 /* PDMA Delay Interrupt Register */
169 #define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0)
170 #define MTK_PDMA_DELAY_RX_EN BIT(15)
171 #define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
172 #define MTK_PDMA_DELAY_RX_PTIME_SHIFT 0
173
174 #define MTK_PDMA_DELAY_TX_MASK GENMASK(31, 16)
175 #define MTK_PDMA_DELAY_TX_EN BIT(31)
176 #define MTK_PDMA_DELAY_TX_PINT_SHIFT 24
177 #define MTK_PDMA_DELAY_TX_PTIME_SHIFT 16
178
179 #define MTK_PDMA_DELAY_PINT_MASK 0x7f
180 #define MTK_PDMA_DELAY_PTIME_MASK 0xff
181
182 /* PDMA HW LRO Alter Flow Delta Register */
183 #define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
184
185 /* PDMA HW LRO IP Setting Registers */
186 #define MTK_LRO_RX_RING0_DIP_DW0 0xb04
187 #define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
188 #define MTK_RING_MYIP_VLD BIT(9)
189
190 /* PDMA HW LRO Ring Control Registers */
191 #define MTK_LRO_RX_RING0_CTRL_DW1 0xb28
192 #define MTK_LRO_RX_RING0_CTRL_DW2 0xb2c
193 #define MTK_LRO_RX_RING0_CTRL_DW3 0xb30
194 #define MTK_LRO_CTRL_DW1_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW1 + (x * 0x40))
195 #define MTK_LRO_CTRL_DW2_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW2 + (x * 0x40))
196 #define MTK_LRO_CTRL_DW3_CFG(x) (MTK_LRO_RX_RING0_CTRL_DW3 + (x * 0x40))
197 #define MTK_RING_AGE_TIME_L ((MTK_HW_LRO_AGE_TIME & 0x3ff) << 22)
198 #define MTK_RING_AGE_TIME_H ((MTK_HW_LRO_AGE_TIME >> 10) & 0x3f)
199 #define MTK_RING_AUTO_LERAN_MODE (3 << 6)
200 #define MTK_RING_VLD BIT(8)
201 #define MTK_RING_MAX_AGG_TIME ((MTK_HW_LRO_AGG_TIME & 0xffff) << 10)
202 #define MTK_RING_MAX_AGG_CNT_L ((MTK_HW_LRO_MAX_AGG_CNT & 0x3f) << 26)
203 #define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
204
205 /* QDMA TX Queue Configuration Registers */
206 #define QDMA_RES_THRES 4
207
208 /* QDMA Global Configuration Register */
209 #define MTK_RX_2B_OFFSET BIT(31)
210 #define MTK_RX_BT_32DWORDS (3 << 11)
211 #define MTK_NDP_CO_PRO BIT(10)
212 #define MTK_TX_WB_DDONE BIT(6)
213 #define MTK_TX_BT_32DWORDS (3 << 4)
214 #define MTK_RX_DMA_BUSY BIT(3)
215 #define MTK_TX_DMA_BUSY BIT(1)
216 #define MTK_RX_DMA_EN BIT(2)
217 #define MTK_TX_DMA_EN BIT(0)
218 #define MTK_DMA_BUSY_TIMEOUT_US 1000000
219
220 /* QDMA V2 Global Configuration Register */
221 #define MTK_CHK_DDONE_EN BIT(28)
222 #define MTK_DMAD_WR_WDONE BIT(26)
223 #define MTK_WCOMP_EN BIT(24)
224 #define MTK_RESV_BUF (0x40 << 16)
225 #define MTK_MUTLI_CNT (0x4 << 12)
226
227 /* QDMA Flow Control Register */
228 #define FC_THRES_DROP_MODE BIT(20)
229 #define FC_THRES_DROP_EN (7 << 16)
230 #define FC_THRES_MIN 0x4444
231
232 /* QDMA Interrupt Status Register */
233 #define MTK_RX_DONE_DLY BIT(30)
234 #define MTK_TX_DONE_DLY BIT(28)
235 #define MTK_RX_DONE_INT3 BIT(19)
236 #define MTK_RX_DONE_INT2 BIT(18)
237 #define MTK_RX_DONE_INT1 BIT(17)
238 #define MTK_RX_DONE_INT0 BIT(16)
239 #define MTK_TX_DONE_INT3 BIT(3)
240 #define MTK_TX_DONE_INT2 BIT(2)
241 #define MTK_TX_DONE_INT1 BIT(1)
242 #define MTK_TX_DONE_INT0 BIT(0)
243 #define MTK_RX_DONE_INT MTK_RX_DONE_DLY
244 #define MTK_TX_DONE_INT MTK_TX_DONE_DLY
245
246 #define MTK_RX_DONE_INT_V2 BIT(14)
247
248 /* QDMA Interrupt grouping registers */
249 #define MTK_RLS_DONE_INT BIT(0)
250
251 #define MTK_STAT_OFFSET 0x40
252
253 /* QDMA TX NUM */
254 #define MTK_QDMA_TX_NUM 16
255 #define MTK_QDMA_TX_MASK (MTK_QDMA_TX_NUM - 1)
256 #define QID_BITS_V2(x) (((x) & 0x3f) << 16)
257 #define MTK_QDMA_GMAC2_QID 8
258
259 #define MTK_TX_DMA_BUF_SHIFT 8
260
261 /* QDMA V2 descriptor txd6 */
262 #define TX_DMA_INS_VLAN_V2 BIT(16)
263 /* QDMA V2 descriptor txd5 */
264 #define TX_DMA_CHKSUM_V2 (0x7 << 28)
265 #define TX_DMA_TSO_V2 BIT(31)
266
267 /* QDMA V2 descriptor txd4 */
268 #define TX_DMA_FPORT_SHIFT_V2 8
269 #define TX_DMA_FPORT_MASK_V2 0xf
270 #define TX_DMA_SWC_V2 BIT(30)
271
272 /* QDMA descriptor txd4 */
273 #define TX_DMA_CHKSUM (0x7 << 29)
274 #define TX_DMA_TSO BIT(28)
275 #define TX_DMA_FPORT_SHIFT 25
276 #define TX_DMA_FPORT_MASK 0x7
277 #define TX_DMA_INS_VLAN BIT(16)
278
279 /* QDMA descriptor txd3 */
280 #define TX_DMA_OWNER_CPU BIT(31)
281 #define TX_DMA_LS0 BIT(30)
282 #define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
283 #define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len)
284 #define TX_DMA_SWC BIT(14)
285
286 /* PDMA on MT7628 */
287 #define TX_DMA_DONE BIT(31)
288 #define TX_DMA_LS1 BIT(14)
289 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
290
291 /* QDMA descriptor rxd2 */
292 #define RX_DMA_DONE BIT(31)
293 #define RX_DMA_LSO BIT(30)
294 #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
295 #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
296 #define RX_DMA_VTAG BIT(15)
297
298 /* QDMA descriptor rxd3 */
299 #define RX_DMA_VID(x) ((x) & VLAN_VID_MASK)
300 #define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK))
301 #define RX_DMA_VPID(x) (((x) >> 16) & 0xffff)
302
303 /* QDMA descriptor rxd4 */
304 #define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
305 #define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14)
306 #define MTK_RXD4_SRC_PORT GENMASK(21, 19)
307 #define MTK_RXD4_ALG GENMASK(31, 22)
308
309 /* QDMA descriptor rxd4 */
310 #define RX_DMA_L4_VALID BIT(24)
311 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
312 #define RX_DMA_SPECIAL_TAG BIT(22)
313
314 /* PDMA descriptor rxd5 */
315 #define MTK_RXD5_FOE_ENTRY GENMASK(14, 0)
316 #define MTK_RXD5_PPE_CPU_REASON GENMASK(22, 18)
317 #define MTK_RXD5_SRC_PORT GENMASK(29, 26)
318
319 #define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0x7)
320 #define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0xf)
321
322 /* PDMA V2 descriptor rxd3 */
323 #define RX_DMA_VTAG_V2 BIT(0)
324 #define RX_DMA_L4_VALID_V2 BIT(2)
325
326 /* PHY Indirect Access Control registers */
327 #define MTK_PHY_IAC 0x10004
328 #define PHY_IAC_ACCESS BIT(31)
329 #define PHY_IAC_REG_MASK GENMASK(29, 25)
330 #define PHY_IAC_REG(x) FIELD_PREP(PHY_IAC_REG_MASK, (x))
331 #define PHY_IAC_ADDR_MASK GENMASK(24, 20)
332 #define PHY_IAC_ADDR(x) FIELD_PREP(PHY_IAC_ADDR_MASK, (x))
333 #define PHY_IAC_CMD_MASK GENMASK(19, 18)
334 #define PHY_IAC_CMD_C45_ADDR FIELD_PREP(PHY_IAC_CMD_MASK, 0)
335 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1)
336 #define PHY_IAC_CMD_C22_READ FIELD_PREP(PHY_IAC_CMD_MASK, 2)
337 #define PHY_IAC_CMD_C45_READ FIELD_PREP(PHY_IAC_CMD_MASK, 3)
338 #define PHY_IAC_START_MASK GENMASK(17, 16)
339 #define PHY_IAC_START_C45 FIELD_PREP(PHY_IAC_START_MASK, 0)
340 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1)
341 #define PHY_IAC_DATA_MASK GENMASK(15, 0)
342 #define PHY_IAC_DATA(x) FIELD_PREP(PHY_IAC_DATA_MASK, (x))
343 #define PHY_IAC_TIMEOUT HZ
344
345 #define MTK_MAC_MISC 0x1000c
346 #define MTK_MUX_TO_ESW BIT(0)
347
348 /* Mac control registers */
349 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
350 #define MAC_MCR_MAX_RX_MASK GENMASK(25, 24)
351 #define MAC_MCR_MAX_RX(_x) (MAC_MCR_MAX_RX_MASK & ((_x) << 24))
352 #define MAC_MCR_MAX_RX_1518 0x0
353 #define MAC_MCR_MAX_RX_1536 0x1
354 #define MAC_MCR_MAX_RX_1552 0x2
355 #define MAC_MCR_MAX_RX_2048 0x3
356 #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
357 #define MAC_MCR_FORCE_MODE BIT(15)
358 #define MAC_MCR_TX_EN BIT(14)
359 #define MAC_MCR_RX_EN BIT(13)
360 #define MAC_MCR_BACKOFF_EN BIT(9)
361 #define MAC_MCR_BACKPR_EN BIT(8)
362 #define MAC_MCR_FORCE_RX_FC BIT(5)
363 #define MAC_MCR_FORCE_TX_FC BIT(4)
364 #define MAC_MCR_SPEED_1000 BIT(3)
365 #define MAC_MCR_SPEED_100 BIT(2)
366 #define MAC_MCR_FORCE_DPX BIT(1)
367 #define MAC_MCR_FORCE_LINK BIT(0)
368 #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE)
369
370 /* Mac status registers */
371 #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100))
372 #define MAC_MSR_EEE1G BIT(7)
373 #define MAC_MSR_EEE100M BIT(6)
374 #define MAC_MSR_RX_FC BIT(5)
375 #define MAC_MSR_TX_FC BIT(4)
376 #define MAC_MSR_SPEED_1000 BIT(3)
377 #define MAC_MSR_SPEED_100 BIT(2)
378 #define MAC_MSR_SPEED_MASK (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)
379 #define MAC_MSR_DPX BIT(1)
380 #define MAC_MSR_LINK BIT(0)
381
382 /* TRGMII RXC control register */
383 #define TRGMII_RCK_CTRL 0x10300
384 #define DQSI0(x) ((x << 0) & GENMASK(6, 0))
385 #define DQSI1(x) ((x << 8) & GENMASK(14, 8))
386 #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
387 #define RXC_RST BIT(31)
388 #define RXC_DQSISEL BIT(30)
389 #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
390 #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
391
392 #define NUM_TRGMII_CTRL 5
393
394 /* TRGMII RXC control register */
395 #define TRGMII_TCK_CTRL 0x10340
396 #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
397 #define TXC_INV BIT(30)
398 #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
399 #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2))
400
401 /* TRGMII TX Drive Strength */
402 #define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
403 #define TD_DM_DRVP(x) ((x) & 0xf)
404 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
405
406 /* TRGMII Interface mode register */
407 #define INTF_MODE 0x10390
408 #define TRGMII_INTF_DIS BIT(0)
409 #define TRGMII_MODE BIT(1)
410 #define TRGMII_CENTRAL_ALIGNED BIT(2)
411 #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
412 #define INTF_MODE_RGMII_10_100 0
413
414 /* GPIO port control registers for GMAC 2*/
415 #define GPIO_OD33_CTRL8 0x4c0
416 #define GPIO_BIAS_CTRL 0xed0
417 #define GPIO_DRV_SEL10 0xf00
418
419 /* ethernet subsystem chip id register */
420 #define ETHSYS_CHIPID0_3 0x0
421 #define ETHSYS_CHIPID4_7 0x4
422 #define MT7623_ETH 7623
423 #define MT7622_ETH 7622
424 #define MT7621_ETH 7621
425
426 /* ethernet system control register */
427 #define ETHSYS_SYSCFG 0x10
428 #define SYSCFG_DRAM_TYPE_DDR2 BIT(4)
429
430 /* ethernet subsystem config register */
431 #define ETHSYS_SYSCFG0 0x14
432 #define SYSCFG0_GE_MASK 0x3
433 #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
434 #define SYSCFG0_SGMII_MASK GENMASK(9, 8)
435 #define SYSCFG0_SGMII_GMAC1 ((2 << 8) & SYSCFG0_SGMII_MASK)
436 #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
437 #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
438 #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
439
440
441 /* ethernet subsystem clock register */
442 #define ETHSYS_CLKCFG0 0x2c
443 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
444 #define ETHSYS_TRGMII_MT7621_MASK (BIT(5) | BIT(6))
445 #define ETHSYS_TRGMII_MT7621_APLL BIT(6)
446 #define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
447
448 /* ethernet reset control register */
449 #define ETHSYS_RSTCTRL 0x34
450 #define RSTCTRL_FE BIT(6)
451 #define RSTCTRL_PPE0 BIT(31)
452 #define RSTCTRL_PPE0_V2 BIT(30)
453 #define RSTCTRL_PPE1 BIT(31)
454 #define RSTCTRL_ETH BIT(23)
455
456 /* ethernet reset check idle register */
457 #define ETHSYS_FE_RST_CHK_IDLE_EN 0x28
458
459 /* ethernet dma channel agent map */
460 #define ETHSYS_DMA_AG_MAP 0x408
461 #define ETHSYS_DMA_AG_MAP_PDMA BIT(0)
462 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
463 #define ETHSYS_DMA_AG_MAP_PPE BIT(2)
464
465 /* SGMII subsystem config registers */
466 /* Register to auto-negotiation restart */
467 #define SGMSYS_PCS_CONTROL_1 0x0
468 #define SGMII_AN_RESTART BIT(9)
469 #define SGMII_ISOLATE BIT(10)
470 #define SGMII_AN_ENABLE BIT(12)
471 #define SGMII_LINK_STATYS BIT(18)
472 #define SGMII_AN_ABILITY BIT(19)
473 #define SGMII_AN_COMPLETE BIT(21)
474 #define SGMII_PCS_FAULT BIT(23)
475 #define SGMII_AN_EXPANSION_CLR BIT(30)
476
477 /* Register to programmable link timer, the unit in 2 * 8ns */
478 #define SGMSYS_PCS_LINK_TIMER 0x18
479 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0))
480
481 /* Register to control remote fault */
482 #define SGMSYS_SGMII_MODE 0x20
483 #define SGMII_IF_MODE_BIT0 BIT(0)
484 #define SGMII_SPEED_DUPLEX_AN BIT(1)
485 #define SGMII_SPEED_MASK GENMASK(3, 2)
486 #define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0)
487 #define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1)
488 #define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2)
489 #define SGMII_DUPLEX_FULL BIT(4)
490 #define SGMII_IF_MODE_BIT5 BIT(5)
491 #define SGMII_REMOTE_FAULT_DIS BIT(8)
492 #define SGMII_CODE_SYNC_SET_VAL BIT(9)
493 #define SGMII_CODE_SYNC_SET_EN BIT(10)
494 #define SGMII_SEND_AN_ERROR_EN BIT(11)
495 #define SGMII_IF_MODE_MASK GENMASK(5, 1)
496
497 /* Register to set SGMII speed, ANA RG_ Control Signals III*/
498 #define SGMSYS_ANA_RG_CS3 0x2028
499 #define RG_PHY_SPEED_MASK (BIT(2) | BIT(3))
500 #define RG_PHY_SPEED_1_25G 0x0
501 #define RG_PHY_SPEED_3_125G BIT(2)
502
503 /* Register to power up QPHY */
504 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
505 #define SGMII_PHYA_PWD BIT(4)
506
507 /* Infrasys subsystem config registers */
508 #define INFRA_MISC2 0x70c
509 #define CO_QPHY_SEL BIT(0)
510 #define GEPHY_MAC_SEL BIT(1)
511
512 /* MT7628/88 specific stuff */
513 #define MT7628_PDMA_OFFSET 0x0800
514 #define MT7628_SDM_OFFSET 0x0c00
515
516 #define MT7628_TX_BASE_PTR0 (MT7628_PDMA_OFFSET + 0x00)
517 #define MT7628_TX_MAX_CNT0 (MT7628_PDMA_OFFSET + 0x04)
518 #define MT7628_TX_CTX_IDX0 (MT7628_PDMA_OFFSET + 0x08)
519 #define MT7628_TX_DTX_IDX0 (MT7628_PDMA_OFFSET + 0x0c)
520 #define MT7628_PST_DTX_IDX0 BIT(0)
521
522 #define MT7628_SDM_MAC_ADRL (MT7628_SDM_OFFSET + 0x0c)
523 #define MT7628_SDM_MAC_ADRH (MT7628_SDM_OFFSET + 0x10)
524
525 /* Counter / stat register */
526 #define MT7628_SDM_TPCNT (MT7628_SDM_OFFSET + 0x100)
527 #define MT7628_SDM_TBCNT (MT7628_SDM_OFFSET + 0x104)
528 #define MT7628_SDM_RPCNT (MT7628_SDM_OFFSET + 0x108)
529 #define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
530 #define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
531
532 struct mtk_rx_dma {
533 unsigned int rxd1;
534 unsigned int rxd2;
535 unsigned int rxd3;
536 unsigned int rxd4;
537 } __packed __aligned(4);
538
539 struct mtk_rx_dma_v2 {
540 unsigned int rxd1;
541 unsigned int rxd2;
542 unsigned int rxd3;
543 unsigned int rxd4;
544 unsigned int rxd5;
545 unsigned int rxd6;
546 unsigned int rxd7;
547 unsigned int rxd8;
548 } __packed __aligned(4);
549
550 struct mtk_tx_dma {
551 unsigned int txd1;
552 unsigned int txd2;
553 unsigned int txd3;
554 unsigned int txd4;
555 } __packed __aligned(4);
556
557 struct mtk_tx_dma_v2 {
558 unsigned int txd1;
559 unsigned int txd2;
560 unsigned int txd3;
561 unsigned int txd4;
562 unsigned int txd5;
563 unsigned int txd6;
564 unsigned int txd7;
565 unsigned int txd8;
566 } __packed __aligned(4);
567
568 struct mtk_eth;
569 struct mtk_mac;
570
571 struct mtk_xdp_stats {
572 u64 rx_xdp_redirect;
573 u64 rx_xdp_pass;
574 u64 rx_xdp_drop;
575 u64 rx_xdp_tx;
576 u64 rx_xdp_tx_errors;
577 u64 tx_xdp_xmit;
578 u64 tx_xdp_xmit_errors;
579 };
580
581 /* struct mtk_hw_stats - the structure that holds the traffic statistics.
582 * @stats_lock: make sure that stats operations are atomic
583 * @reg_offset: the status register offset of the SoC
584 * @syncp: the refcount
585 *
586 * All of the supported SoCs have hardware counters for traffic statistics.
587 * Whenever the status IRQ triggers we can read the latest stats from these
588 * counters and store them in this struct.
589 */
590 struct mtk_hw_stats {
591 u64 tx_bytes;
592 u64 tx_packets;
593 u64 tx_skip;
594 u64 tx_collisions;
595 u64 rx_bytes;
596 u64 rx_packets;
597 u64 rx_overflow;
598 u64 rx_fcs_errors;
599 u64 rx_short_errors;
600 u64 rx_long_errors;
601 u64 rx_checksum_errors;
602 u64 rx_flow_control_packets;
603
604 struct mtk_xdp_stats xdp_stats;
605
606 spinlock_t stats_lock;
607 u32 reg_offset;
608 struct u64_stats_sync syncp;
609 };
610
611 enum mtk_tx_flags {
612 /* PDMA descriptor can point at 1-2 segments. This enum allows us to
613 * track how memory was allocated so that it can be freed properly.
614 */
615 MTK_TX_FLAGS_SINGLE0 = 0x01,
616 MTK_TX_FLAGS_PAGE0 = 0x02,
617
618 /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted
619 * SKB out instead of looking up through hardware TX descriptor.
620 */
621 MTK_TX_FLAGS_FPORT0 = 0x04,
622 MTK_TX_FLAGS_FPORT1 = 0x08,
623 };
624
625 /* This enum allows us to identify how the clock is defined on the array of the
626 * clock in the order
627 */
628 enum mtk_clks_map {
629 MTK_CLK_ETHIF,
630 MTK_CLK_SGMIITOP,
631 MTK_CLK_ESW,
632 MTK_CLK_GP0,
633 MTK_CLK_GP1,
634 MTK_CLK_GP2,
635 MTK_CLK_FE,
636 MTK_CLK_TRGPLL,
637 MTK_CLK_SGMII_TX_250M,
638 MTK_CLK_SGMII_RX_250M,
639 MTK_CLK_SGMII_CDR_REF,
640 MTK_CLK_SGMII_CDR_FB,
641 MTK_CLK_SGMII2_TX_250M,
642 MTK_CLK_SGMII2_RX_250M,
643 MTK_CLK_SGMII2_CDR_REF,
644 MTK_CLK_SGMII2_CDR_FB,
645 MTK_CLK_SGMII_CK,
646 MTK_CLK_ETH2PLL,
647 MTK_CLK_WOCPU0,
648 MTK_CLK_WOCPU1,
649 MTK_CLK_NETSYS0,
650 MTK_CLK_NETSYS1,
651 MTK_CLK_MAX
652 };
653
654 #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
655 BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \
656 BIT(MTK_CLK_TRGPLL))
657 #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
658 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
659 BIT(MTK_CLK_GP2) | \
660 BIT(MTK_CLK_SGMII_TX_250M) | \
661 BIT(MTK_CLK_SGMII_RX_250M) | \
662 BIT(MTK_CLK_SGMII_CDR_REF) | \
663 BIT(MTK_CLK_SGMII_CDR_FB) | \
664 BIT(MTK_CLK_SGMII_CK) | \
665 BIT(MTK_CLK_ETH2PLL))
666 #define MT7621_CLKS_BITMAP (0)
667 #define MT7628_CLKS_BITMAP (0)
668 #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \
669 BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \
670 BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \
671 BIT(MTK_CLK_SGMII_TX_250M) | \
672 BIT(MTK_CLK_SGMII_RX_250M) | \
673 BIT(MTK_CLK_SGMII_CDR_REF) | \
674 BIT(MTK_CLK_SGMII_CDR_FB) | \
675 BIT(MTK_CLK_SGMII2_TX_250M) | \
676 BIT(MTK_CLK_SGMII2_RX_250M) | \
677 BIT(MTK_CLK_SGMII2_CDR_REF) | \
678 BIT(MTK_CLK_SGMII2_CDR_FB) | \
679 BIT(MTK_CLK_SGMII_CK) | \
680 BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
681 #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
682 BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
683 BIT(MTK_CLK_SGMII_TX_250M) | \
684 BIT(MTK_CLK_SGMII_RX_250M) | \
685 BIT(MTK_CLK_SGMII_CDR_REF) | \
686 BIT(MTK_CLK_SGMII_CDR_FB) | \
687 BIT(MTK_CLK_SGMII2_TX_250M) | \
688 BIT(MTK_CLK_SGMII2_RX_250M) | \
689 BIT(MTK_CLK_SGMII2_CDR_REF) | \
690 BIT(MTK_CLK_SGMII2_CDR_FB))
691
692 enum mtk_dev_state {
693 MTK_HW_INIT,
694 MTK_RESETTING
695 };
696
697 enum mtk_tx_buf_type {
698 MTK_TYPE_SKB,
699 MTK_TYPE_XDP_TX,
700 MTK_TYPE_XDP_NDO,
701 };
702
703 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
704 * by the TX descriptor s
705 * @skb: The SKB pointer of the packet being sent
706 * @dma_addr0: The base addr of the first segment
707 * @dma_len0: The length of the first segment
708 * @dma_addr1: The base addr of the second segment
709 * @dma_len1: The length of the second segment
710 */
711 struct mtk_tx_buf {
712 enum mtk_tx_buf_type type;
713 void *data;
714
715 u32 flags;
716 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
717 DEFINE_DMA_UNMAP_LEN(dma_len0);
718 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
719 DEFINE_DMA_UNMAP_LEN(dma_len1);
720 };
721
722 /* struct mtk_tx_ring - This struct holds info describing a TX ring
723 * @dma: The descriptor ring
724 * @buf: The memory pointed at by the ring
725 * @phys: The physical addr of tx_buf
726 * @next_free: Pointer to the next free descriptor
727 * @last_free: Pointer to the last free descriptor
728 * @last_free_ptr: Hardware pointer value of the last free descriptor
729 * @thresh: The threshold of minimum amount of free descriptors
730 * @free_count: QDMA uses a linked list. Track how many free descriptors
731 * are present
732 */
733 struct mtk_tx_ring {
734 void *dma;
735 struct mtk_tx_buf *buf;
736 dma_addr_t phys;
737 struct mtk_tx_dma *next_free;
738 struct mtk_tx_dma *last_free;
739 u32 last_free_ptr;
740 u16 thresh;
741 atomic_t free_count;
742 int dma_size;
743 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */
744 dma_addr_t phys_pdma;
745 int cpu_idx;
746 };
747
748 /* PDMA rx ring mode */
749 enum mtk_rx_flags {
750 MTK_RX_FLAGS_NORMAL = 0,
751 MTK_RX_FLAGS_HWLRO,
752 MTK_RX_FLAGS_QDMA,
753 };
754
755 /* struct mtk_rx_ring - This struct holds info describing a RX ring
756 * @dma: The descriptor ring
757 * @data: The memory pointed at by the ring
758 * @phys: The physical addr of rx_buf
759 * @frag_size: How big can each fragment be
760 * @buf_size: The size of each packet buffer
761 * @calc_idx: The current head of ring
762 */
763 struct mtk_rx_ring {
764 void *dma;
765 u8 **data;
766 dma_addr_t phys;
767 u16 frag_size;
768 u16 buf_size;
769 u16 dma_size;
770 bool calc_idx_update;
771 u16 calc_idx;
772 u32 crx_idx_reg;
773 /* page_pool */
774 struct page_pool *page_pool;
775 struct xdp_rxq_info xdp_q;
776 };
777
778 enum mkt_eth_capabilities {
779 MTK_RGMII_BIT = 0,
780 MTK_TRGMII_BIT,
781 MTK_SGMII_BIT,
782 MTK_ESW_BIT,
783 MTK_GEPHY_BIT,
784 MTK_MUX_BIT,
785 MTK_INFRA_BIT,
786 MTK_SHARED_SGMII_BIT,
787 MTK_HWLRO_BIT,
788 MTK_SHARED_INT_BIT,
789 MTK_TRGMII_MT7621_CLK_BIT,
790 MTK_QDMA_BIT,
791 MTK_NETSYS_V2_BIT,
792 MTK_SOC_MT7628_BIT,
793 MTK_RSTCTRL_PPE1_BIT,
794
795 /* MUX BITS*/
796 MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
797 MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
798 MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
799 MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
800 MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
801
802 /* PATH BITS */
803 MTK_ETH_PATH_GMAC1_RGMII_BIT,
804 MTK_ETH_PATH_GMAC1_TRGMII_BIT,
805 MTK_ETH_PATH_GMAC1_SGMII_BIT,
806 MTK_ETH_PATH_GMAC2_RGMII_BIT,
807 MTK_ETH_PATH_GMAC2_SGMII_BIT,
808 MTK_ETH_PATH_GMAC2_GEPHY_BIT,
809 MTK_ETH_PATH_GDM1_ESW_BIT,
810 };
811
812 /* Supported hardware group on SoCs */
813 #define MTK_RGMII BIT(MTK_RGMII_BIT)
814 #define MTK_TRGMII BIT(MTK_TRGMII_BIT)
815 #define MTK_SGMII BIT(MTK_SGMII_BIT)
816 #define MTK_ESW BIT(MTK_ESW_BIT)
817 #define MTK_GEPHY BIT(MTK_GEPHY_BIT)
818 #define MTK_MUX BIT(MTK_MUX_BIT)
819 #define MTK_INFRA BIT(MTK_INFRA_BIT)
820 #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT)
821 #define MTK_HWLRO BIT(MTK_HWLRO_BIT)
822 #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
823 #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
824 #define MTK_QDMA BIT(MTK_QDMA_BIT)
825 #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
826 #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
827 #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
828
829 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
830 BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
831 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \
832 BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
833 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
834 BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
835 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
836 BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
837 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
838 BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
839
840 /* Supported path present on SoCs */
841 #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT)
842 #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
843 #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT)
844 #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT)
845 #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT)
846 #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
847 #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT)
848
849 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
850 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
851 #define MTK_GMAC1_SGMII (MTK_ETH_PATH_GMAC1_SGMII | MTK_SGMII)
852 #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
853 #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
854 #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
855 #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
856
857 /* MUXes present on SoCs */
858 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
859 #define MTK_MUX_GDM1_TO_GMAC1_ESW (MTK_ETH_MUX_GDM1_TO_GMAC1_ESW | MTK_MUX)
860
861 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
862 #define MTK_MUX_GMAC2_GMAC0_TO_GEPHY \
863 (MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_MUX | MTK_INFRA)
864
865 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
866 #define MTK_MUX_U3_GMAC2_TO_QPHY \
867 (MTK_ETH_MUX_U3_GMAC2_TO_QPHY | MTK_MUX | MTK_INFRA)
868
869 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
870 #define MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
871 (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
872 MTK_SHARED_SGMII)
873
874 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
875 #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
876 (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
877
878 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
879
880 #define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
881 MTK_GMAC2_RGMII | MTK_SHARED_INT | \
882 MTK_TRGMII_MT7621_CLK | MTK_QDMA)
883
884 #define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \
885 MTK_GMAC2_SGMII | MTK_GDM1_ESW | \
886 MTK_MUX_GDM1_TO_GMAC1_ESW | \
887 MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA)
888
889 #define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \
890 MTK_QDMA)
891
892 #define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628)
893
894 #define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
895 MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \
896 MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \
897 MTK_MUX_U3_GMAC2_TO_QPHY | \
898 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
899
900 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
901 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
902 MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
903
904 struct mtk_tx_dma_desc_info {
905 dma_addr_t addr;
906 u32 size;
907 u16 vlan_tci;
908 u16 qid;
909 u8 gso:1;
910 u8 csum:1;
911 u8 vlan:1;
912 u8 first:1;
913 u8 last:1;
914 };
915
916 struct mtk_reg_map {
917 u32 tx_irq_mask;
918 u32 tx_irq_status;
919 struct {
920 u32 rx_ptr; /* rx base pointer */
921 u32 rx_cnt_cfg; /* rx max count configuration */
922 u32 pcrx_ptr; /* rx cpu pointer */
923 u32 glo_cfg; /* global configuration */
924 u32 rst_idx; /* reset index */
925 u32 delay_irq; /* delay interrupt */
926 u32 irq_status; /* interrupt status */
927 u32 irq_mask; /* interrupt mask */
928 u32 int_grp;
929 } pdma;
930 struct {
931 u32 qtx_cfg; /* tx queue configuration */
932 u32 rx_ptr; /* rx base pointer */
933 u32 rx_cnt_cfg; /* rx max count configuration */
934 u32 qcrx_ptr; /* rx cpu pointer */
935 u32 glo_cfg; /* global configuration */
936 u32 rst_idx; /* reset index */
937 u32 delay_irq; /* delay interrupt */
938 u32 fc_th; /* flow control */
939 u32 int_grp;
940 u32 hred; /* interrupt mask */
941 u32 ctx_ptr; /* tx acquire cpu pointer */
942 u32 dtx_ptr; /* tx acquire dma pointer */
943 u32 crx_ptr; /* tx release cpu pointer */
944 u32 drx_ptr; /* tx release dma pointer */
945 u32 fq_head; /* fq head pointer */
946 u32 fq_tail; /* fq tail pointer */
947 u32 fq_count; /* fq free page count */
948 u32 fq_blen; /* fq free page buffer length */
949 } qdma;
950 u32 gdm1_cnt;
951 u32 gdma_to_ppe;
952 u32 ppe_base;
953 u32 wdma_base[2];
954 };
955
956 /* struct mtk_eth_data - This is the structure holding all differences
957 * among various plaforms
958 * @reg_map Soc register map.
959 * @ana_rgc3: The offset for register ANA_RGC3 related to
960 * sgmiisys syscon
961 * @caps Flags shown the extra capability for the SoC
962 * @hw_features Flags shown HW features
963 * @required_clks Flags shown the bitmap for required clocks on
964 * the target SoC
965 * @required_pctl A bool value to show whether the SoC requires
966 * the extra setup for those pins used by GMAC.
967 * @hash_offset Flow table hash offset.
968 * @foe_entry_size Foe table entry size.
969 * @txd_size Tx DMA descriptor size.
970 * @rxd_size Rx DMA descriptor size.
971 * @rx_irq_done_mask Rx irq done register mask.
972 * @rx_dma_l4_valid Rx DMA valid register mask.
973 * @dma_max_len Max DMA tx/rx buffer length.
974 * @dma_len_offset Tx/Rx DMA length field offset.
975 */
976 struct mtk_soc_data {
977 const struct mtk_reg_map *reg_map;
978 u32 ana_rgc3;
979 u32 caps;
980 u32 required_clks;
981 bool required_pctl;
982 u8 offload_version;
983 u8 hash_offset;
984 u16 foe_entry_size;
985 netdev_features_t hw_features;
986 struct {
987 u32 txd_size;
988 u32 rxd_size;
989 u32 rx_irq_done_mask;
990 u32 rx_dma_l4_valid;
991 u32 dma_max_len;
992 u32 dma_len_offset;
993 } txrx;
994 };
995
996 /* currently no SoC has more than 2 macs */
997 #define MTK_MAX_DEVS 2
998
999 /* struct mtk_pcs - This structure holds each sgmii regmap and associated
1000 * data
1001 * @regmap: The register map pointing at the range used to setup
1002 * SGMII modes
1003 * @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
1004 * @pcs: Phylink PCS structure
1005 */
1006 struct mtk_pcs {
1007 struct regmap *regmap;
1008 u32 ana_rgc3;
1009 struct phylink_pcs pcs;
1010 };
1011
1012 /* struct mtk_sgmii - This is the structure holding sgmii regmap and its
1013 * characteristics
1014 * @pcs Array of individual PCS structures
1015 */
1016 struct mtk_sgmii {
1017 struct mtk_pcs pcs[MTK_MAX_DEVS];
1018 };
1019
1020 /* struct mtk_eth - This is the main datasructure for holding the state
1021 * of the driver
1022 * @dev: The device pointer
1023 * @dev: The device pointer used for dma mapping/alloc
1024 * @base: The mapped register i/o base
1025 * @page_lock: Make sure that register operations are atomic
1026 * @tx_irq__lock: Make sure that IRQ register operations are atomic
1027 * @rx_irq__lock: Make sure that IRQ register operations are atomic
1028 * @dim_lock: Make sure that Net DIM operations are atomic
1029 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
1030 * dummy for NAPI to work
1031 * @netdev: The netdev instances
1032 * @mac: Each netdev is linked to a physical MAC
1033 * @irq: The IRQ that we are using
1034 * @msg_enable: Ethtool msg level
1035 * @ethsys: The register map pointing at the range used to setup
1036 * MII modes
1037 * @infra: The register map pointing at the range used to setup
1038 * SGMII and GePHY path
1039 * @pctl: The register map pointing at the range used to setup
1040 * GMAC port drive/slew values
1041 * @dma_refcnt: track how many netdevs are using the DMA engine
1042 * @tx_ring: Pointer to the memory holding info about the TX ring
1043 * @rx_ring: Pointer to the memory holding info about the RX ring
1044 * @rx_ring_qdma: Pointer to the memory holding info about the QDMA RX ring
1045 * @tx_napi: The TX NAPI struct
1046 * @rx_napi: The RX NAPI struct
1047 * @rx_events: Net DIM RX event counter
1048 * @rx_packets: Net DIM RX packet counter
1049 * @rx_bytes: Net DIM RX byte counter
1050 * @rx_dim: Net DIM RX context
1051 * @tx_events: Net DIM TX event counter
1052 * @tx_packets: Net DIM TX packet counter
1053 * @tx_bytes: Net DIM TX byte counter
1054 * @tx_dim: Net DIM TX context
1055 * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
1056 * @phy_scratch_ring: physical address of scratch_ring
1057 * @scratch_head: The scratch memory that scratch_ring points to.
1058 * @clks: clock array for all clocks required
1059 * @mii_bus: If there is a bus we need to create an instance for it
1060 * @pending_work: The workqueue used to reset the dma ring
1061 * @state: Initialization and runtime state of the device
1062 * @soc: Holding specific data among vaious SoCs
1063 */
1064
1065 struct mtk_eth {
1066 struct device *dev;
1067 struct device *dma_dev;
1068 void __iomem *base;
1069 spinlock_t page_lock;
1070 spinlock_t tx_irq_lock;
1071 spinlock_t rx_irq_lock;
1072 struct net_device dummy_dev;
1073 struct net_device *netdev[MTK_MAX_DEVS];
1074 struct mtk_mac *mac[MTK_MAX_DEVS];
1075 int irq[3];
1076 u32 msg_enable;
1077 unsigned long sysclk;
1078 struct regmap *ethsys;
1079 struct regmap *infra;
1080 struct mtk_sgmii *sgmii;
1081 struct regmap *pctl;
1082 bool hwlro;
1083 refcount_t dma_refcnt;
1084 struct mtk_tx_ring tx_ring;
1085 struct mtk_rx_ring rx_ring[MTK_MAX_RX_RING_NUM];
1086 struct mtk_rx_ring rx_ring_qdma;
1087 struct napi_struct tx_napi;
1088 struct napi_struct rx_napi;
1089 void *scratch_ring;
1090 dma_addr_t phy_scratch_ring;
1091 void *scratch_head;
1092 struct clk *clks[MTK_CLK_MAX];
1093
1094 struct mii_bus *mii_bus;
1095 struct work_struct pending_work;
1096 unsigned long state;
1097
1098 const struct mtk_soc_data *soc;
1099
1100 spinlock_t dim_lock;
1101
1102 u32 rx_events;
1103 u32 rx_packets;
1104 u32 rx_bytes;
1105 struct dim rx_dim;
1106
1107 u32 tx_events;
1108 u32 tx_packets;
1109 u32 tx_bytes;
1110 struct dim tx_dim;
1111
1112 int ip_align;
1113
1114 struct mtk_ppe *ppe[2];
1115 struct rhashtable flow_table;
1116
1117 struct bpf_prog __rcu *prog;
1118 };
1119
1120 /* struct mtk_mac - the structure that holds the info about the MACs of the
1121 * SoC
1122 * @id: The number of the MAC
1123 * @interface: Interface mode kept for detecting change in hw settings
1124 * @of_node: Our devicetree node
1125 * @hw: Backpointer to our main datastruture
1126 * @hw_stats: Packet statistics counter
1127 */
1128 struct mtk_mac {
1129 int id;
1130 phy_interface_t interface;
1131 int speed;
1132 struct device_node *of_node;
1133 struct phylink *phylink;
1134 struct phylink_config phylink_config;
1135 struct mtk_eth *hw;
1136 struct mtk_hw_stats *hw_stats;
1137 __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
1138 int hwlro_ip_cnt;
1139 unsigned int syscfg0;
1140 };
1141
1142 /* the struct describing the SoC. these are declared in the soc_xyz.c files */
1143 extern const struct of_device_id of_mtk_match[];
1144
1145 static inline struct mtk_foe_entry *
mtk_foe_get_entry(struct mtk_ppe * ppe,u16 hash)1146 mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash)
1147 {
1148 const struct mtk_soc_data *soc = ppe->eth->soc;
1149
1150 return ppe->foe_table + hash * soc->foe_entry_size;
1151 }
1152
mtk_get_ib1_ts_mask(struct mtk_eth * eth)1153 static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth)
1154 {
1155 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1156 return MTK_FOE_IB1_BIND_TIMESTAMP_V2;
1157
1158 return MTK_FOE_IB1_BIND_TIMESTAMP;
1159 }
1160
mtk_get_ib1_ppoe_mask(struct mtk_eth * eth)1161 static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth)
1162 {
1163 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1164 return MTK_FOE_IB1_BIND_PPPOE_V2;
1165
1166 return MTK_FOE_IB1_BIND_PPPOE;
1167 }
1168
mtk_get_ib1_vlan_tag_mask(struct mtk_eth * eth)1169 static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth)
1170 {
1171 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1172 return MTK_FOE_IB1_BIND_VLAN_TAG_V2;
1173
1174 return MTK_FOE_IB1_BIND_VLAN_TAG;
1175 }
1176
mtk_get_ib1_vlan_layer_mask(struct mtk_eth * eth)1177 static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth)
1178 {
1179 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1180 return MTK_FOE_IB1_BIND_VLAN_LAYER_V2;
1181
1182 return MTK_FOE_IB1_BIND_VLAN_LAYER;
1183 }
1184
mtk_prep_ib1_vlan_layer(struct mtk_eth * eth,u32 val)1185 static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
1186 {
1187 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1188 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
1189
1190 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
1191 }
1192
mtk_get_ib1_vlan_layer(struct mtk_eth * eth,u32 val)1193 static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val)
1194 {
1195 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1196 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val);
1197
1198 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val);
1199 }
1200
mtk_get_ib1_pkt_type_mask(struct mtk_eth * eth)1201 static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth)
1202 {
1203 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1204 return MTK_FOE_IB1_PACKET_TYPE_V2;
1205
1206 return MTK_FOE_IB1_PACKET_TYPE;
1207 }
1208
mtk_get_ib1_pkt_type(struct mtk_eth * eth,u32 val)1209 static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val)
1210 {
1211 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1212 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val);
1213
1214 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val);
1215 }
1216
mtk_get_ib2_multicast_mask(struct mtk_eth * eth)1217 static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth)
1218 {
1219 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
1220 return MTK_FOE_IB2_MULTICAST_V2;
1221
1222 return MTK_FOE_IB2_MULTICAST;
1223 }
1224
1225 /* read the hardware status register */
1226 void mtk_stats_update_mac(struct mtk_mac *mac);
1227
1228 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
1229 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
1230
1231 struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id);
1232 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
1233 u32 ana_rgc3);
1234
1235 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
1236 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
1237 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
1238
1239 int mtk_eth_offload_init(struct mtk_eth *eth);
1240 int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
1241 void *type_data);
1242 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
1243
1244
1245 #endif /* MTK_ETH_H */
1246