1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PERF_EVENT_H
3 #define _ASM_X86_PERF_EVENT_H
4
5 #include <linux/static_call.h>
6
7 /*
8 * Performance event hw details:
9 */
10
11 #define INTEL_PMC_MAX_GENERIC 32
12 #define INTEL_PMC_MAX_FIXED 16
13 #define INTEL_PMC_IDX_FIXED 32
14
15 #define X86_PMC_IDX_MAX 64
16
17 #define MSR_ARCH_PERFMON_PERFCTR0 0xc1
18 #define MSR_ARCH_PERFMON_PERFCTR1 0xc2
19
20 #define MSR_ARCH_PERFMON_EVENTSEL0 0x186
21 #define MSR_ARCH_PERFMON_EVENTSEL1 0x187
22
23 #define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
24 #define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
25 #define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16)
26 #define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17)
27 #define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18)
28 #define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19)
29 #define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20)
30 #define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21)
31 #define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22)
32 #define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23)
33 #define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
34
35 #define HSW_IN_TX (1ULL << 32)
36 #define HSW_IN_TX_CHECKPOINTED (1ULL << 33)
37 #define ICL_EVENTSEL_ADAPTIVE (1ULL << 34)
38 #define ICL_FIXED_0_ADAPTIVE (1ULL << 32)
39
40 #define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36)
41 #define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
42 #define AMD64_EVENTSEL_HOSTONLY (1ULL << 41)
43
44 #define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37
45 #define AMD64_EVENTSEL_INT_CORE_SEL_MASK \
46 (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
47
48 #define AMD64_EVENTSEL_EVENT \
49 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
50 #define INTEL_ARCH_EVENT_MASK \
51 (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
52
53 #define AMD64_L3_SLICE_SHIFT 48
54 #define AMD64_L3_SLICE_MASK \
55 (0xFULL << AMD64_L3_SLICE_SHIFT)
56 #define AMD64_L3_SLICEID_MASK \
57 (0x7ULL << AMD64_L3_SLICE_SHIFT)
58
59 #define AMD64_L3_THREAD_SHIFT 56
60 #define AMD64_L3_THREAD_MASK \
61 (0xFFULL << AMD64_L3_THREAD_SHIFT)
62 #define AMD64_L3_F19H_THREAD_MASK \
63 (0x3ULL << AMD64_L3_THREAD_SHIFT)
64
65 #define AMD64_L3_EN_ALL_CORES BIT_ULL(47)
66 #define AMD64_L3_EN_ALL_SLICES BIT_ULL(46)
67
68 #define AMD64_L3_COREID_SHIFT 42
69 #define AMD64_L3_COREID_MASK \
70 (0x7ULL << AMD64_L3_COREID_SHIFT)
71
72 #define X86_RAW_EVENT_MASK \
73 (ARCH_PERFMON_EVENTSEL_EVENT | \
74 ARCH_PERFMON_EVENTSEL_UMASK | \
75 ARCH_PERFMON_EVENTSEL_EDGE | \
76 ARCH_PERFMON_EVENTSEL_INV | \
77 ARCH_PERFMON_EVENTSEL_CMASK)
78 #define X86_ALL_EVENT_FLAGS \
79 (ARCH_PERFMON_EVENTSEL_EDGE | \
80 ARCH_PERFMON_EVENTSEL_INV | \
81 ARCH_PERFMON_EVENTSEL_CMASK | \
82 ARCH_PERFMON_EVENTSEL_ANY | \
83 ARCH_PERFMON_EVENTSEL_PIN_CONTROL | \
84 HSW_IN_TX | \
85 HSW_IN_TX_CHECKPOINTED)
86 #define AMD64_RAW_EVENT_MASK \
87 (X86_RAW_EVENT_MASK | \
88 AMD64_EVENTSEL_EVENT)
89 #define AMD64_RAW_EVENT_MASK_NB \
90 (AMD64_EVENTSEL_EVENT | \
91 ARCH_PERFMON_EVENTSEL_UMASK)
92
93 #define AMD64_PERFMON_V2_EVENTSEL_EVENT_NB \
94 (AMD64_EVENTSEL_EVENT | \
95 GENMASK_ULL(37, 36))
96
97 #define AMD64_PERFMON_V2_EVENTSEL_UMASK_NB \
98 (ARCH_PERFMON_EVENTSEL_UMASK | \
99 GENMASK_ULL(27, 24))
100
101 #define AMD64_PERFMON_V2_RAW_EVENT_MASK_NB \
102 (AMD64_PERFMON_V2_EVENTSEL_EVENT_NB | \
103 AMD64_PERFMON_V2_EVENTSEL_UMASK_NB)
104
105 #define AMD64_NUM_COUNTERS 4
106 #define AMD64_NUM_COUNTERS_CORE 6
107 #define AMD64_NUM_COUNTERS_NB 4
108
109 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c
110 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8)
111 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0
112 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
113 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
114
115 #define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
116 #define ARCH_PERFMON_EVENTS_COUNT 7
117
118 #define PEBS_DATACFG_MEMINFO BIT_ULL(0)
119 #define PEBS_DATACFG_GP BIT_ULL(1)
120 #define PEBS_DATACFG_XMMS BIT_ULL(2)
121 #define PEBS_DATACFG_LBRS BIT_ULL(3)
122 #define PEBS_DATACFG_LBR_SHIFT 24
123
124 /*
125 * Intel "Architectural Performance Monitoring" CPUID
126 * detection/enumeration details:
127 */
128 union cpuid10_eax {
129 struct {
130 unsigned int version_id:8;
131 unsigned int num_counters:8;
132 unsigned int bit_width:8;
133 unsigned int mask_length:8;
134 } split;
135 unsigned int full;
136 };
137
138 union cpuid10_ebx {
139 struct {
140 unsigned int no_unhalted_core_cycles:1;
141 unsigned int no_instructions_retired:1;
142 unsigned int no_unhalted_reference_cycles:1;
143 unsigned int no_llc_reference:1;
144 unsigned int no_llc_misses:1;
145 unsigned int no_branch_instruction_retired:1;
146 unsigned int no_branch_misses_retired:1;
147 } split;
148 unsigned int full;
149 };
150
151 union cpuid10_edx {
152 struct {
153 unsigned int num_counters_fixed:5;
154 unsigned int bit_width_fixed:8;
155 unsigned int reserved1:2;
156 unsigned int anythread_deprecated:1;
157 unsigned int reserved2:16;
158 } split;
159 unsigned int full;
160 };
161
162 /*
163 * Intel Architectural LBR CPUID detection/enumeration details:
164 */
165 union cpuid28_eax {
166 struct {
167 /* Supported LBR depth values */
168 unsigned int lbr_depth_mask:8;
169 unsigned int reserved:22;
170 /* Deep C-state Reset */
171 unsigned int lbr_deep_c_reset:1;
172 /* IP values contain LIP */
173 unsigned int lbr_lip:1;
174 } split;
175 unsigned int full;
176 };
177
178 union cpuid28_ebx {
179 struct {
180 /* CPL Filtering Supported */
181 unsigned int lbr_cpl:1;
182 /* Branch Filtering Supported */
183 unsigned int lbr_filter:1;
184 /* Call-stack Mode Supported */
185 unsigned int lbr_call_stack:1;
186 } split;
187 unsigned int full;
188 };
189
190 union cpuid28_ecx {
191 struct {
192 /* Mispredict Bit Supported */
193 unsigned int lbr_mispred:1;
194 /* Timed LBRs Supported */
195 unsigned int lbr_timed_lbr:1;
196 /* Branch Type Field Supported */
197 unsigned int lbr_br_type:1;
198 } split;
199 unsigned int full;
200 };
201
202 /*
203 * AMD "Extended Performance Monitoring and Debug" CPUID
204 * detection/enumeration details:
205 */
206 union cpuid_0x80000022_ebx {
207 struct {
208 /* Number of Core Performance Counters */
209 unsigned int num_core_pmc:4;
210 /* Number of available LBR Stack Entries */
211 unsigned int lbr_v2_stack_sz:6;
212 /* Number of Data Fabric Counters */
213 unsigned int num_df_pmc:6;
214 } split;
215 unsigned int full;
216 };
217
218 struct x86_pmu_capability {
219 int version;
220 int num_counters_gp;
221 int num_counters_fixed;
222 int bit_width_gp;
223 int bit_width_fixed;
224 unsigned int events_mask;
225 int events_mask_len;
226 unsigned int pebs_ept :1;
227 };
228
229 /*
230 * Fixed-purpose performance events:
231 */
232
233 /* RDPMC offset for Fixed PMCs */
234 #define INTEL_PMC_FIXED_RDPMC_BASE (1 << 30)
235 #define INTEL_PMC_FIXED_RDPMC_METRICS (1 << 29)
236
237 /*
238 * All the fixed-mode PMCs are configured via this single MSR:
239 */
240 #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
241
242 /*
243 * There is no event-code assigned to the fixed-mode PMCs.
244 *
245 * For a fixed-mode PMC, which has an equivalent event on a general-purpose
246 * PMC, the event-code of the equivalent event is used for the fixed-mode PMC,
247 * e.g., Instr_Retired.Any and CPU_CLK_Unhalted.Core.
248 *
249 * For a fixed-mode PMC, which doesn't have an equivalent event, a
250 * pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS.
251 * The pseudo event-code for a fixed-mode PMC must be 0x00.
252 * The pseudo umask-code is 0xX. The X equals the index of the fixed
253 * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.
254 *
255 * The counts are available in separate MSRs:
256 */
257
258 /* Instr_Retired.Any: */
259 #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
260 #define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0)
261
262 /* CPU_CLK_Unhalted.Core: */
263 #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
264 #define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1)
265
266 /* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */
267 #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
268 #define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
269 #define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
270
271 /* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */
272 #define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c
273 #define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)
274 #define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
275
use_fixed_pseudo_encoding(u64 code)276 static inline bool use_fixed_pseudo_encoding(u64 code)
277 {
278 return !(code & 0xff);
279 }
280
281 /*
282 * We model BTS tracing as another fixed-mode PMC.
283 *
284 * We choose the value 47 for the fixed index of BTS, since lower
285 * values are used by actual fixed events and higher values are used
286 * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
287 */
288 #define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15)
289
290 /*
291 * The PERF_METRICS MSR is modeled as several magic fixed-mode PMCs, one for
292 * each TopDown metric event.
293 *
294 * Internally the TopDown metric events are mapped to the FxCtr 3 (SLOTS).
295 */
296 #define INTEL_PMC_IDX_METRIC_BASE (INTEL_PMC_IDX_FIXED + 16)
297 #define INTEL_PMC_IDX_TD_RETIRING (INTEL_PMC_IDX_METRIC_BASE + 0)
298 #define INTEL_PMC_IDX_TD_BAD_SPEC (INTEL_PMC_IDX_METRIC_BASE + 1)
299 #define INTEL_PMC_IDX_TD_FE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 2)
300 #define INTEL_PMC_IDX_TD_BE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 3)
301 #define INTEL_PMC_IDX_TD_HEAVY_OPS (INTEL_PMC_IDX_METRIC_BASE + 4)
302 #define INTEL_PMC_IDX_TD_BR_MISPREDICT (INTEL_PMC_IDX_METRIC_BASE + 5)
303 #define INTEL_PMC_IDX_TD_FETCH_LAT (INTEL_PMC_IDX_METRIC_BASE + 6)
304 #define INTEL_PMC_IDX_TD_MEM_BOUND (INTEL_PMC_IDX_METRIC_BASE + 7)
305 #define INTEL_PMC_IDX_METRIC_END INTEL_PMC_IDX_TD_MEM_BOUND
306 #define INTEL_PMC_MSK_TOPDOWN ((0xffull << INTEL_PMC_IDX_METRIC_BASE) | \
307 INTEL_PMC_MSK_FIXED_SLOTS)
308
309 /*
310 * There is no event-code assigned to the TopDown events.
311 *
312 * For the slots event, use the pseudo code of the fixed counter 3.
313 *
314 * For the metric events, the pseudo event-code is 0x00.
315 * The pseudo umask-code starts from the middle of the pseudo event
316 * space, 0x80.
317 */
318 #define INTEL_TD_SLOTS 0x0400 /* TOPDOWN.SLOTS */
319 /* Level 1 metrics */
320 #define INTEL_TD_METRIC_RETIRING 0x8000 /* Retiring metric */
321 #define INTEL_TD_METRIC_BAD_SPEC 0x8100 /* Bad speculation metric */
322 #define INTEL_TD_METRIC_FE_BOUND 0x8200 /* FE bound metric */
323 #define INTEL_TD_METRIC_BE_BOUND 0x8300 /* BE bound metric */
324 /* Level 2 metrics */
325 #define INTEL_TD_METRIC_HEAVY_OPS 0x8400 /* Heavy Operations metric */
326 #define INTEL_TD_METRIC_BR_MISPREDICT 0x8500 /* Branch Mispredict metric */
327 #define INTEL_TD_METRIC_FETCH_LAT 0x8600 /* Fetch Latency metric */
328 #define INTEL_TD_METRIC_MEM_BOUND 0x8700 /* Memory bound metric */
329
330 #define INTEL_TD_METRIC_MAX INTEL_TD_METRIC_MEM_BOUND
331 #define INTEL_TD_METRIC_NUM 8
332
is_metric_idx(int idx)333 static inline bool is_metric_idx(int idx)
334 {
335 return (unsigned)(idx - INTEL_PMC_IDX_METRIC_BASE) < INTEL_TD_METRIC_NUM;
336 }
337
is_topdown_idx(int idx)338 static inline bool is_topdown_idx(int idx)
339 {
340 return is_metric_idx(idx) || idx == INTEL_PMC_IDX_FIXED_SLOTS;
341 }
342
343 #define INTEL_PMC_OTHER_TOPDOWN_BITS(bit) \
344 (~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN)
345
346 #define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
347 #define GLOBAL_STATUS_BUFFER_OVF_BIT 62
348 #define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT)
349 #define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
350 #define GLOBAL_STATUS_ASIF BIT_ULL(60)
351 #define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
352 #define GLOBAL_STATUS_LBRS_FROZEN_BIT 58
353 #define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT)
354 #define GLOBAL_STATUS_TRACE_TOPAPMI_BIT 55
355 #define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT)
356 #define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48
357
358 #define GLOBAL_CTRL_EN_PERF_METRICS 48
359 /*
360 * We model guest LBR event tracing as another fixed-mode PMC like BTS.
361 *
362 * We choose bit 58 because it's used to indicate LBR stack frozen state
363 * for architectural perfmon v4, also we unconditionally mask that bit in
364 * the handle_pmi_common(), so it'll never be set in the overflow handling.
365 *
366 * With this fake counter assigned, the guest LBR event user (such as KVM),
367 * can program the LBR registers on its own, and we don't actually do anything
368 * with then in the host context.
369 */
370 #define INTEL_PMC_IDX_FIXED_VLBR (GLOBAL_STATUS_LBRS_FROZEN_BIT)
371
372 /*
373 * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b,
374 * since it would claim bit 58 which is effectively Fixed26.
375 */
376 #define INTEL_FIXED_VLBR_EVENT 0x1b00
377
378 /*
379 * Adaptive PEBS v4
380 */
381
382 struct pebs_basic {
383 u64 format_size;
384 u64 ip;
385 u64 applicable_counters;
386 u64 tsc;
387 };
388
389 struct pebs_meminfo {
390 u64 address;
391 u64 aux;
392 u64 latency;
393 u64 tsx_tuning;
394 };
395
396 struct pebs_gprs {
397 u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di;
398 u64 r8, r9, r10, r11, r12, r13, r14, r15;
399 };
400
401 struct pebs_xmm {
402 u64 xmm[16*2]; /* two entries for each register */
403 };
404
405 /*
406 * AMD Extended Performance Monitoring and Debug cpuid feature detection
407 */
408 #define EXT_PERFMON_DEBUG_FEATURES 0x80000022
409
410 /*
411 * IBS cpuid feature detection
412 */
413
414 #define IBS_CPUID_FEATURES 0x8000001b
415
416 /*
417 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
418 * bit 0 is used to indicate the existence of IBS.
419 */
420 #define IBS_CAPS_AVAIL (1U<<0)
421 #define IBS_CAPS_FETCHSAM (1U<<1)
422 #define IBS_CAPS_OPSAM (1U<<2)
423 #define IBS_CAPS_RDWROPCNT (1U<<3)
424 #define IBS_CAPS_OPCNT (1U<<4)
425 #define IBS_CAPS_BRNTRGT (1U<<5)
426 #define IBS_CAPS_OPCNTEXT (1U<<6)
427 #define IBS_CAPS_RIPINVALIDCHK (1U<<7)
428 #define IBS_CAPS_OPBRNFUSE (1U<<8)
429 #define IBS_CAPS_FETCHCTLEXTD (1U<<9)
430 #define IBS_CAPS_OPDATA4 (1U<<10)
431 #define IBS_CAPS_ZEN4 (1U<<11)
432
433 #define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \
434 | IBS_CAPS_FETCHSAM \
435 | IBS_CAPS_OPSAM)
436
437 /*
438 * IBS APIC setup
439 */
440 #define IBSCTL 0x1cc
441 #define IBSCTL_LVT_OFFSET_VALID (1ULL<<8)
442 #define IBSCTL_LVT_OFFSET_MASK 0x0F
443
444 /* IBS fetch bits/masks */
445 #define IBS_FETCH_L3MISSONLY (1ULL<<59)
446 #define IBS_FETCH_RAND_EN (1ULL<<57)
447 #define IBS_FETCH_VAL (1ULL<<49)
448 #define IBS_FETCH_ENABLE (1ULL<<48)
449 #define IBS_FETCH_CNT 0xFFFF0000ULL
450 #define IBS_FETCH_MAX_CNT 0x0000FFFFULL
451
452 /*
453 * IBS op bits/masks
454 * The lower 7 bits of the current count are random bits
455 * preloaded by hardware and ignored in software
456 */
457 #define IBS_OP_CUR_CNT (0xFFF80ULL<<32)
458 #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32)
459 #define IBS_OP_CNT_CTL (1ULL<<19)
460 #define IBS_OP_VAL (1ULL<<18)
461 #define IBS_OP_ENABLE (1ULL<<17)
462 #define IBS_OP_L3MISSONLY (1ULL<<16)
463 #define IBS_OP_MAX_CNT 0x0000FFFFULL
464 #define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */
465 #define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL<<20) /* separate upper 7 bits */
466 #define IBS_RIP_INVALID (1ULL<<38)
467
468 #ifdef CONFIG_X86_LOCAL_APIC
469 extern u32 get_ibs_caps(void);
470 #else
get_ibs_caps(void)471 static inline u32 get_ibs_caps(void) { return 0; }
472 #endif
473
474 #ifdef CONFIG_PERF_EVENTS
475 extern void perf_events_lapic_init(void);
476
477 /*
478 * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
479 * unused and ABI specified to be 0, so nobody should care what we do with
480 * them.
481 *
482 * EXACT - the IP points to the exact instruction that triggered the
483 * event (HW bugs exempt).
484 * VM - original X86_VM_MASK; see set_linear_ip().
485 */
486 #define PERF_EFLAGS_EXACT (1UL << 3)
487 #define PERF_EFLAGS_VM (1UL << 5)
488
489 struct pt_regs;
490 struct x86_perf_regs {
491 struct pt_regs regs;
492 u64 *xmm_regs;
493 };
494
495 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
496 extern unsigned long perf_misc_flags(struct pt_regs *regs);
497 #define perf_misc_flags(regs) perf_misc_flags(regs)
498
499 #include <asm/stacktrace.h>
500
501 /*
502 * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
503 * and the comment with PERF_EFLAGS_EXACT.
504 */
505 #define perf_arch_fetch_caller_regs(regs, __ip) { \
506 (regs)->ip = (__ip); \
507 (regs)->sp = (unsigned long)__builtin_frame_address(0); \
508 (regs)->cs = __KERNEL_CS; \
509 regs->flags = 0; \
510 }
511
512 struct perf_guest_switch_msr {
513 unsigned msr;
514 u64 host, guest;
515 };
516
517 struct x86_pmu_lbr {
518 unsigned int nr;
519 unsigned int from;
520 unsigned int to;
521 unsigned int info;
522 };
523
524 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
525 extern u64 perf_get_hw_event_config(int hw_event);
526 extern void perf_check_microcode(void);
527 extern void perf_clear_dirty_counters(void);
528 extern int x86_perf_rdpmc_index(struct perf_event *event);
529 #else
perf_get_x86_pmu_capability(struct x86_pmu_capability * cap)530 static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
531 {
532 memset(cap, 0, sizeof(*cap));
533 }
534
perf_get_hw_event_config(int hw_event)535 static inline u64 perf_get_hw_event_config(int hw_event)
536 {
537 return 0;
538 }
539
perf_events_lapic_init(void)540 static inline void perf_events_lapic_init(void) { }
perf_check_microcode(void)541 static inline void perf_check_microcode(void) { }
542 #endif
543
544 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
545 extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data);
546 extern int x86_perf_get_lbr(struct x86_pmu_lbr *lbr);
547 #else
548 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data);
x86_perf_get_lbr(struct x86_pmu_lbr * lbr)549 static inline int x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
550 {
551 return -1;
552 }
553 #endif
554
555 #ifdef CONFIG_CPU_SUP_INTEL
556 extern void intel_pt_handle_vmx(int on);
557 #else
intel_pt_handle_vmx(int on)558 static inline void intel_pt_handle_vmx(int on)
559 {
560
561 }
562 #endif
563
564 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
565 extern void amd_pmu_enable_virt(void);
566 extern void amd_pmu_disable_virt(void);
567
568 #if defined(CONFIG_PERF_EVENTS_AMD_BRS)
569
570 #define PERF_NEEDS_LOPWR_CB 1
571
572 /*
573 * architectural low power callback impacts
574 * drivers/acpi/processor_idle.c
575 * drivers/acpi/acpi_pad.c
576 */
577 extern void perf_amd_brs_lopwr_cb(bool lopwr_in);
578
579 DECLARE_STATIC_CALL(perf_lopwr_cb, perf_amd_brs_lopwr_cb);
580
perf_lopwr_cb(bool lopwr_in)581 static inline void perf_lopwr_cb(bool lopwr_in)
582 {
583 static_call_mod(perf_lopwr_cb)(lopwr_in);
584 }
585
586 #endif /* PERF_NEEDS_LOPWR_CB */
587
588 #else
amd_pmu_enable_virt(void)589 static inline void amd_pmu_enable_virt(void) { }
amd_pmu_disable_virt(void)590 static inline void amd_pmu_disable_virt(void) { }
591 #endif
592
593 #define arch_perf_out_copy_user copy_from_user_nmi
594
595 #endif /* _ASM_X86_PERF_EVENT_H */
596