Searched refs:MPLL (Results 1 – 12 of 12) sorted by relevance
| /linux-6.1.9/drivers/clk/mstar/ |
| D | Kconfig | 3 bool "MStar MPLL driver"
8 Support for the MPLL PLL and dividers block present on
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| /linux-6.1.9/Documentation/devicetree/bindings/clock/ |
| D | mstar,msc313-mpll.yaml | 7 title: MStar/Sigmastar MSC313 MPLL
13 The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that
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| D | mvebu-core-clock.txt | 38 3 = mpll (MPLL Clock)
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| /linux-6.1.9/include/dt-bindings/clock/ |
| D | s3c2410.h | 22 #define MPLL 2 macro
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| D | s3c2412.h | 22 #define MPLL 2 macro
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| D | s3c2443.h | 26 #define MPLL 7 macro
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| /linux-6.1.9/drivers/clk/samsung/ |
| D | clk-s3c2410.c | 109 ALIAS(MPLL, NULL, "mpll"),
155 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
221 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
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| D | clk-s3c2412.c | 101 PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
155 ALIAS(MPLL, NULL, "mpll"),
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| D | clk-s3c2443.c | 148 ALIAS(MPLL, NULL, "mpll"),
182 PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
234 PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
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| /linux-6.1.9/Documentation/devicetree/bindings/net/ |
| D | mdio-mux-meson-g12a.txt | 14 * "clkin1" : SoC 50MHz MPLL
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| /linux-6.1.9/arch/arm/boot/dts/ |
| D | exynos5422-odroid-core.dtsi | 41 /* derived from 532MHz MPLL */
133 /* derived from 532MHz MPLL */
181 /* derived from 532MHz MPLL */
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| /linux-6.1.9/drivers/clk/ingenic/ |
| D | jz4780-cgu.c | 301 .pll = DEF_PLL(MPLL),
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