Searched refs:MLX5_MATCH_MISC_PARAMETERS_2 (Results 1 – 12 of 12) sorted by relevance
113 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2; in parse_tunnel()
1592 MLX5_MATCH_MISC_PARAMETERS_2); in mlx5_tc_ct_alloc_pre_ct()
188 MLX5_MATCH_OUTER_HEADERS | MLX5_MATCH_MISC_PARAMETERS_2); in mlx5_esw_bridge_ingress_vlan_proto_fg_create()250 MLX5_MATCH_OUTER_HEADERS | MLX5_MATCH_MISC_PARAMETERS_2); in mlx5_esw_bridge_ingress_vlan_proto_filter_fg_create()308 MLX5_MATCH_OUTER_HEADERS | MLX5_MATCH_MISC_PARAMETERS_2); in mlx5_esw_bridge_ingress_mac_fg_create()429 MLX5_SET(create_flow_group_in, in, match_criteria_enable, MLX5_MATCH_MISC_PARAMETERS_2); in mlx5_esw_bridge_egress_miss_fg_create()676 rule_spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS | MLX5_MATCH_MISC_PARAMETERS_2; in mlx5_esw_bridge_ingress_flow_with_esw_create()775 rule_spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS | MLX5_MATCH_MISC_PARAMETERS_2; in mlx5_esw_bridge_ingress_filter_flow_create()896 rule_spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; in mlx5_esw_bridge_egress_miss_flow_create()
157 MLX5_MATCH_MISC_PARAMETERS_2; in mlx5_esw_indir_table_rule_get()301 MLX5_MATCH_MISC_PARAMETERS | MLX5_MATCH_MISC_PARAMETERS_2); in mlx5_create_indir_recirc_group()
66 MLX5_MATCH_MISC_PARAMETERS_2); in mlx5e_post_meter_fg_create()
84 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; in mlx5e_int_port_create_rx_rule()
101 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2 | MLX5_MATCH_OUTER_HEADERS; in mlx5_ct_fs_smfs_matcher_create()
183 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_MISC_PARAMETERS_2); in macsec_fs_tx_create_crypto_table_groups()367 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; in macsec_fs_tx_create()438 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2; in macsec_fs_tx_setup_fte()851 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; in macsec_fs_rx_create_check_decap_rule()
497 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2; in tx_add_rule()
122 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2; in mlx5_eswitch_clear_rule_source_port()159 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2; in mlx5_eswitch_set_rule_source_port()1090 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; in mlx5_eswitch_add_send_to_vport_meta_rule()1172 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; in peer_miss_rules_setup()1422 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; in esw_add_restore_rule()1457 MLX5_MATCH_MISC_PARAMETERS_2); in esw_set_flow_group_source_port()1692 MLX5_MATCH_MISC_PARAMETERS_2); in esw_create_meta_send_to_vport_group()2119 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; in mlx5_eswitch_create_vport_rx_rule()2268 MLX5_MATCH_MISC_PARAMETERS_2); in esw_create_restore_table()
209 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2; in mlx5e_tc_match_to_reg_match()
1115 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3, enumerator