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Searched refs:MISC_CLK_CTRL__ZCLK_SEL_MASK (Results 1 – 12 of 12) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dfiji_baco.c99 …{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__…
Dci_baco.c116 …{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__…
Dpolaris_baco.c102 …{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__…
Dtonga_baco.c107 …{ CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__…
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dcik.c1832 MISC_CLK_CTRL__ZCLK_SEL_MASK); in cik_program_aspm()
Dvi.c1228 MISC_CLK_CTRL__ZCLK_SEL_MASK | MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK); in vi_program_aspm()
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_0_0_sh_mask.h271 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 macro
Dsmu_7_1_1_sh_mask.h269 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 macro
Dsmu_7_0_1_sh_mask.h269 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 macro
Dsmu_7_1_0_sh_mask.h267 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 macro
Dsmu_7_1_2_sh_mask.h269 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 macro
Dsmu_7_1_3_sh_mask.h297 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 macro