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Searched refs:MHZ (Results 1 – 25 of 77) sorted by relevance

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/linux-6.1.9/drivers/clk/samsung/
Dclk-s3c2410.c123 PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
124 PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
125 PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
126 PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
127 PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
129 PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
130 PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
131 PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
132 PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
133 PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
[all …]
Dclk-exynos3250.c670 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
671 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
672 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
673 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
674 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
675 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
676 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
677 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
678 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
679 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
[all …]
Dclk-exynos4.c1071 PLL_4508_RATE(24 * MHZ, 1200000000, 150, 3, 1, 28),
1072 PLL_4508_RATE(24 * MHZ, 1000000000, 250, 6, 1, 28),
1073 PLL_4508_RATE(24 * MHZ, 800000000, 200, 6, 1, 28),
1074 PLL_4508_RATE(24 * MHZ, 666857142, 389, 14, 1, 13),
1075 PLL_4508_RATE(24 * MHZ, 600000000, 100, 4, 1, 13),
1076 PLL_4508_RATE(24 * MHZ, 533000000, 533, 24, 1, 5),
1077 PLL_4508_RATE(24 * MHZ, 500000000, 250, 6, 2, 28),
1078 PLL_4508_RATE(24 * MHZ, 400000000, 200, 6, 2, 28),
1079 PLL_4508_RATE(24 * MHZ, 200000000, 200, 6, 3, 28),
1084 PLL_4600_RATE(24 * MHZ, 192000000, 48, 3, 1, 0, 0),
[all …]
Dclk-exynos5420.c1400 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1401 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1402 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1403 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1404 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1405 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1406 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1407 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1408 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1409 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
[all …]
Dclk-exynos5250.c691 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0),
693 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0),
700 PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0),
701 PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762),
702 PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0),
703 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923),
704 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762),
705 PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923),
706 PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762),
707 PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719),
[all …]
Dclk-exynos5260.c23 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
24 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
25 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
26 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
27 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
28 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
29 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
30 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
31 PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
32 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
[all …]
Dclk-exynos5410.c227 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
228 PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
229 PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
230 PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
231 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
232 PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
233 PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
234 PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
235 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
236 PLL_36XX_RATE(24 * MHZ, 66000000U, 176, 2, 5, 0),
[all …]
Dclk-exynos5433.c715 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
716 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
717 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
718 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
719 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
720 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
721 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
722 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
723 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
724 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
[all …]
/linux-6.1.9/Documentation/userspace-api/media/dvb/
Dfe-bandwidth-t.rst30 - .. _BANDWIDTH-1-712-MHZ:
38 - .. _BANDWIDTH-5-MHZ:
46 - .. _BANDWIDTH-6-MHZ:
54 - .. _BANDWIDTH-7-MHZ:
62 - .. _BANDWIDTH-8-MHZ:
70 - .. _BANDWIDTH-10-MHZ:
/linux-6.1.9/drivers/clk/
Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
/linux-6.1.9/arch/mips/ralink/
Dmt7620.c64 #define MHZ(x) ((x) * 1000 * 1000) macro
73 return MHZ(40); in mt7620_get_xtal_rate()
75 return MHZ(20); in mt7620_get_xtal_rate()
87 return MHZ(40); in mt7620_get_periph_rate()
104 return MHZ(600); in mt7620_get_cpu_pll_rate()
130 return MHZ(480); in mt7620_get_pll_rate()
208 if (xtal_rate == MHZ(40)) in ralink_clk_init()
209 cpu_rate = MHZ(580); in ralink_clk_init()
211 cpu_rate = MHZ(575); in ralink_clk_init()
213 periph_rate = MHZ(40); in ralink_clk_init()
[all …]
/linux-6.1.9/drivers/net/can/softing/
Dsofting_cs.c26 #define MHZ (1000*1000) macro
33 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
45 .freq = 16 * MHZ, .max_brp = 32, .max_sjw = 4,
57 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
69 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
81 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
93 .freq = 20 * MHZ, .max_brp = 32, .max_sjw = 4,
105 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
117 .freq = 16 * MHZ, .max_brp = 64, .max_sjw = 4,
129 .freq = 24 * MHZ, .max_brp = 64, .max_sjw = 4,
/linux-6.1.9/arch/arm/mach-s3c/
Dsetup-usb-phy-s3c64xx.c36 case 12 * MHZ: in s3c_usb_otgphy_init()
39 case 24 * MHZ: in s3c_usb_otgphy_init()
43 case 48 * MHZ: in s3c_usb_otgphy_init()
Dcpu.h80 #ifndef MHZ
81 #define MHZ (1000*1000) macro
84 #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000)
/linux-6.1.9/drivers/clk/mediatek/
Dclk-mt8365.c760 #define MT8365_PLL_FMAX (3800UL * MHZ)
761 #define MT8365_PLL_FMIN (1500UL * MHZ)
802 { .div = 1, .freq = 1500 * MHZ },
803 { .div = 2, .freq = 750 * MHZ },
804 { .div = 3, .freq = 375 * MHZ },
811 { .div = 1, .freq = 1600 * MHZ },
812 { .div = 2, .freq = 800 * MHZ },
813 { .div = 3, .freq = 400 * MHZ },
814 { .div = 4, .freq = 200 * MHZ },
820 { .div = 1, .freq = 1600 * MHZ },
[all …]
Dclk-mt2701.c31 108 * MHZ),
33 400 * MHZ),
37 340 * MHZ),
39 340 * MHZ),
41 340 * MHZ),
43 27 * MHZ),
45 416 * MHZ),
47 143 * MHZ),
49 27 * MHZ),
936 #define MT8590_PLL_FMAX (2000 * MHZ)
Dclk-mt8183.c1062 #define MT8183_PLL_FMAX (3800UL * MHZ)
1063 #define MT8183_PLL_FMIN (1500UL * MHZ)
1105 { .div = 1, .freq = 1500 * MHZ },
1106 { .div = 2, .freq = 750 * MHZ },
1107 { .div = 3, .freq = 375 * MHZ },
1114 { .div = 1, .freq = 1600 * MHZ },
1115 { .div = 2, .freq = 800 * MHZ },
1116 { .div = 3, .freq = 400 * MHZ },
1117 { .div = 4, .freq = 200 * MHZ },
/linux-6.1.9/drivers/gpu/drm/exynos/
Dexynos_drm_dsi.c534 #ifndef MHZ
535 #define MHZ (1000*1000) macro
549 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); in exynos_dsi_pll_find_pms()
550 p_max = fin / (6 * MHZ); in exynos_dsi_pll_find_pms()
565 if (tmp < 500 * MHZ || in exynos_dsi_pll_find_pms()
566 tmp > driver_data->max_freq * MHZ) in exynos_dsi_pll_find_pms()
618 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, in exynos_dsi_set_pll()
619 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, in exynos_dsi_set_pll()
620 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, in exynos_dsi_set_pll()
621 770 * MHZ, 870 * MHZ, 950 * MHZ, in exynos_dsi_set_pll()
[all …]
/linux-6.1.9/drivers/phy/samsung/
Dphy-exynos4x12-usb2.c140 case 10 * MHZ: in exynos4x12_rate_to_clk()
143 case 12 * MHZ: in exynos4x12_rate_to_clk()
149 case 20 * MHZ: in exynos4x12_rate_to_clk()
152 case 24 * MHZ: in exynos4x12_rate_to_clk()
155 case 50 * MHZ: in exynos4x12_rate_to_clk()
Dphy-s5pv210-usb2.c73 case 12 * MHZ: in s5pv210_rate_to_clk()
76 case 24 * MHZ: in s5pv210_rate_to_clk()
79 case 48 * MHZ: in s5pv210_rate_to_clk()
Dphy-exynos5250-usb2.c149 case 10 * MHZ: in exynos5250_rate_to_clk()
152 case 12 * MHZ: in exynos5250_rate_to_clk()
158 case 20 * MHZ: in exynos5250_rate_to_clk()
161 case 24 * MHZ: in exynos5250_rate_to_clk()
164 case 50 * MHZ: in exynos5250_rate_to_clk()
/linux-6.1.9/arch/powerpc/boot/
Dredboot-83xx.c20 #define MHZ(x) ((x + 500000) / 1000000) macro
33 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
Dredboot-8xx.c19 #define MHZ(x) ((x + 500000) / 1000000) macro
32 bd.bi_busfreq, MHZ(bd.bi_busfreq)); in platform_fixups()
/linux-6.1.9/drivers/soc/samsung/
Dexynos-asv.c23 #define MHZ 1000000U macro
49 opp = dev_pm_opp_find_freq_exact(cpu, opp_freq * MHZ, true); in exynos_asv_update_cpu_opps()
64 ret = dev_pm_opp_adjust_voltage(cpu, opp_freq * MHZ, in exynos_asv_update_cpu_opps()
/linux-6.1.9/drivers/clk/hisilicon/
Dclk-hi3660-stub.c25 #define MHZ (1000 * 1000) macro
66 stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ; in hi3660_stub_clk_recalc_rate()
86 stub_clk->msg[1] = rate / MHZ; in hi3660_stub_clk_set_rate()

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