1 /*
2  * Generic EDAC defs
3  *
4  * Author: Dave Jiang <djiang@mvista.com>
5  *
6  * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
7  * the terms of the GNU General Public License version 2. This program
8  * is licensed "as is" without any warranty of any kind, whether express
9  * or implied.
10  *
11  */
12 #ifndef _LINUX_EDAC_H_
13 #define _LINUX_EDAC_H_
14 
15 #include <linux/atomic.h>
16 #include <linux/device.h>
17 #include <linux/completion.h>
18 #include <linux/workqueue.h>
19 #include <linux/debugfs.h>
20 #include <linux/numa.h>
21 
22 #define EDAC_DEVICE_NAME_LEN	31
23 
24 struct device;
25 
26 #define EDAC_OPSTATE_INVAL	-1
27 #define EDAC_OPSTATE_POLL	0
28 #define EDAC_OPSTATE_NMI	1
29 #define EDAC_OPSTATE_INT	2
30 
31 extern int edac_op_state;
32 
33 struct bus_type *edac_get_sysfs_subsys(void);
34 
opstate_init(void)35 static inline void opstate_init(void)
36 {
37 	switch (edac_op_state) {
38 	case EDAC_OPSTATE_POLL:
39 	case EDAC_OPSTATE_NMI:
40 		break;
41 	default:
42 		edac_op_state = EDAC_OPSTATE_POLL;
43 	}
44 	return;
45 }
46 
47 /* Max length of a DIMM label*/
48 #define EDAC_MC_LABEL_LEN	31
49 
50 /* Maximum size of the location string */
51 #define LOCATION_SIZE 256
52 
53 /* Defines the maximum number of labels that can be reported */
54 #define EDAC_MAX_LABELS		8
55 
56 /* String used to join two or more labels */
57 #define OTHER_LABEL " or "
58 
59 /**
60  * enum dev_type - describe the type of memory DRAM chips used at the stick
61  * @DEV_UNKNOWN:	Can't be determined, or MC doesn't support detect it
62  * @DEV_X1:		1 bit for data
63  * @DEV_X2:		2 bits for data
64  * @DEV_X4:		4 bits for data
65  * @DEV_X8:		8 bits for data
66  * @DEV_X16:		16 bits for data
67  * @DEV_X32:		32 bits for data
68  * @DEV_X64:		64 bits for data
69  *
70  * Typical values are x4 and x8.
71  */
72 enum dev_type {
73 	DEV_UNKNOWN = 0,
74 	DEV_X1,
75 	DEV_X2,
76 	DEV_X4,
77 	DEV_X8,
78 	DEV_X16,
79 	DEV_X32,		/* Do these parts exist? */
80 	DEV_X64			/* Do these parts exist? */
81 };
82 
83 #define DEV_FLAG_UNKNOWN	BIT(DEV_UNKNOWN)
84 #define DEV_FLAG_X1		BIT(DEV_X1)
85 #define DEV_FLAG_X2		BIT(DEV_X2)
86 #define DEV_FLAG_X4		BIT(DEV_X4)
87 #define DEV_FLAG_X8		BIT(DEV_X8)
88 #define DEV_FLAG_X16		BIT(DEV_X16)
89 #define DEV_FLAG_X32		BIT(DEV_X32)
90 #define DEV_FLAG_X64		BIT(DEV_X64)
91 
92 /**
93  * enum hw_event_mc_err_type - type of the detected error
94  *
95  * @HW_EVENT_ERR_CORRECTED:	Corrected Error - Indicates that an ECC
96  *				corrected error was detected
97  * @HW_EVENT_ERR_UNCORRECTED:	Uncorrected Error - Indicates an error that
98  *				can't be corrected by ECC, but it is not
99  *				fatal (maybe it is on an unused memory area,
100  *				or the memory controller could recover from
101  *				it for example, by re-trying the operation).
102  * @HW_EVENT_ERR_DEFERRED:	Deferred Error - Indicates an uncorrectable
103  *				error whose handling is not urgent. This could
104  *				be due to hardware data poisoning where the
105  *				system can continue operation until the poisoned
106  *				data is consumed. Preemptive measures may also
107  *				be taken, e.g. offlining pages, etc.
108  * @HW_EVENT_ERR_FATAL:		Fatal Error - Uncorrected error that could not
109  *				be recovered.
110  * @HW_EVENT_ERR_INFO:		Informational - The CPER spec defines a forth
111  *				type of error: informational logs.
112  */
113 enum hw_event_mc_err_type {
114 	HW_EVENT_ERR_CORRECTED,
115 	HW_EVENT_ERR_UNCORRECTED,
116 	HW_EVENT_ERR_DEFERRED,
117 	HW_EVENT_ERR_FATAL,
118 	HW_EVENT_ERR_INFO,
119 };
120 
mc_event_error_type(const unsigned int err_type)121 static inline char *mc_event_error_type(const unsigned int err_type)
122 {
123 	switch (err_type) {
124 	case HW_EVENT_ERR_CORRECTED:
125 		return "Corrected";
126 	case HW_EVENT_ERR_UNCORRECTED:
127 		return "Uncorrected";
128 	case HW_EVENT_ERR_DEFERRED:
129 		return "Deferred";
130 	case HW_EVENT_ERR_FATAL:
131 		return "Fatal";
132 	default:
133 	case HW_EVENT_ERR_INFO:
134 		return "Info";
135 	}
136 }
137 
138 /**
139  * enum mem_type - memory types. For a more detailed reference, please see
140  *			http://en.wikipedia.org/wiki/DRAM
141  *
142  * @MEM_EMPTY:		Empty csrow
143  * @MEM_RESERVED:	Reserved csrow type
144  * @MEM_UNKNOWN:	Unknown csrow type
145  * @MEM_FPM:		FPM - Fast Page Mode, used on systems up to 1995.
146  * @MEM_EDO:		EDO - Extended data out, used on systems up to 1998.
147  * @MEM_BEDO:		BEDO - Burst Extended data out, an EDO variant.
148  * @MEM_SDR:		SDR - Single data rate SDRAM
149  *			http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
150  *			They use 3 pins for chip select: Pins 0 and 2 are
151  *			for rank 0; pins 1 and 3 are for rank 1, if the memory
152  *			is dual-rank.
153  * @MEM_RDR:		Registered SDR SDRAM
154  * @MEM_DDR:		Double data rate SDRAM
155  *			http://en.wikipedia.org/wiki/DDR_SDRAM
156  * @MEM_RDDR:		Registered Double data rate SDRAM
157  *			This is a variant of the DDR memories.
158  *			A registered memory has a buffer inside it, hiding
159  *			part of the memory details to the memory controller.
160  * @MEM_RMBS:		Rambus DRAM, used on a few Pentium III/IV controllers.
161  * @MEM_DDR2:		DDR2 RAM, as described at JEDEC JESD79-2F.
162  *			Those memories are labeled as "PC2-" instead of "PC" to
163  *			differentiate from DDR.
164  * @MEM_FB_DDR2:	Fully-Buffered DDR2, as described at JEDEC Std No. 205
165  *			and JESD206.
166  *			Those memories are accessed per DIMM slot, and not by
167  *			a chip select signal.
168  * @MEM_RDDR2:		Registered DDR2 RAM
169  *			This is a variant of the DDR2 memories.
170  * @MEM_XDR:		Rambus XDR
171  *			It is an evolution of the original RAMBUS memories,
172  *			created to compete with DDR2. Weren't used on any
173  *			x86 arch, but cell_edac PPC memory controller uses it.
174  * @MEM_DDR3:		DDR3 RAM
175  * @MEM_RDDR3:		Registered DDR3 RAM
176  *			This is a variant of the DDR3 memories.
177  * @MEM_LRDDR3:		Load-Reduced DDR3 memory.
178  * @MEM_LPDDR3:		Low-Power DDR3 memory.
179  * @MEM_DDR4:		Unbuffered DDR4 RAM
180  * @MEM_RDDR4:		Registered DDR4 RAM
181  *			This is a variant of the DDR4 memories.
182  * @MEM_LRDDR4:		Load-Reduced DDR4 memory.
183  * @MEM_LPDDR4:		Low-Power DDR4 memory.
184  * @MEM_DDR5:		Unbuffered DDR5 RAM
185  * @MEM_RDDR5:		Registered DDR5 RAM
186  * @MEM_LRDDR5:		Load-Reduced DDR5 memory.
187  * @MEM_NVDIMM:		Non-volatile RAM
188  * @MEM_WIO2:		Wide I/O 2.
189  * @MEM_HBM2:		High bandwidth Memory Gen 2.
190  */
191 enum mem_type {
192 	MEM_EMPTY = 0,
193 	MEM_RESERVED,
194 	MEM_UNKNOWN,
195 	MEM_FPM,
196 	MEM_EDO,
197 	MEM_BEDO,
198 	MEM_SDR,
199 	MEM_RDR,
200 	MEM_DDR,
201 	MEM_RDDR,
202 	MEM_RMBS,
203 	MEM_DDR2,
204 	MEM_FB_DDR2,
205 	MEM_RDDR2,
206 	MEM_XDR,
207 	MEM_DDR3,
208 	MEM_RDDR3,
209 	MEM_LRDDR3,
210 	MEM_LPDDR3,
211 	MEM_DDR4,
212 	MEM_RDDR4,
213 	MEM_LRDDR4,
214 	MEM_LPDDR4,
215 	MEM_DDR5,
216 	MEM_RDDR5,
217 	MEM_LRDDR5,
218 	MEM_NVDIMM,
219 	MEM_WIO2,
220 	MEM_HBM2,
221 };
222 
223 #define MEM_FLAG_EMPTY		BIT(MEM_EMPTY)
224 #define MEM_FLAG_RESERVED	BIT(MEM_RESERVED)
225 #define MEM_FLAG_UNKNOWN	BIT(MEM_UNKNOWN)
226 #define MEM_FLAG_FPM		BIT(MEM_FPM)
227 #define MEM_FLAG_EDO		BIT(MEM_EDO)
228 #define MEM_FLAG_BEDO		BIT(MEM_BEDO)
229 #define MEM_FLAG_SDR		BIT(MEM_SDR)
230 #define MEM_FLAG_RDR		BIT(MEM_RDR)
231 #define MEM_FLAG_DDR		BIT(MEM_DDR)
232 #define MEM_FLAG_RDDR		BIT(MEM_RDDR)
233 #define MEM_FLAG_RMBS		BIT(MEM_RMBS)
234 #define MEM_FLAG_DDR2		BIT(MEM_DDR2)
235 #define MEM_FLAG_FB_DDR2	BIT(MEM_FB_DDR2)
236 #define MEM_FLAG_RDDR2		BIT(MEM_RDDR2)
237 #define MEM_FLAG_XDR		BIT(MEM_XDR)
238 #define MEM_FLAG_DDR3		BIT(MEM_DDR3)
239 #define MEM_FLAG_RDDR3		BIT(MEM_RDDR3)
240 #define MEM_FLAG_LPDDR3		BIT(MEM_LPDDR3)
241 #define MEM_FLAG_DDR4		BIT(MEM_DDR4)
242 #define MEM_FLAG_RDDR4		BIT(MEM_RDDR4)
243 #define MEM_FLAG_LRDDR4		BIT(MEM_LRDDR4)
244 #define MEM_FLAG_LPDDR4		BIT(MEM_LPDDR4)
245 #define MEM_FLAG_DDR5		BIT(MEM_DDR5)
246 #define MEM_FLAG_RDDR5		BIT(MEM_RDDR5)
247 #define MEM_FLAG_LRDDR5		BIT(MEM_LRDDR5)
248 #define MEM_FLAG_NVDIMM		BIT(MEM_NVDIMM)
249 #define MEM_FLAG_WIO2		BIT(MEM_WIO2)
250 #define MEM_FLAG_HBM2		BIT(MEM_HBM2)
251 
252 /**
253  * enum edac_type - Error Detection and Correction capabilities and mode
254  * @EDAC_UNKNOWN:	Unknown if ECC is available
255  * @EDAC_NONE:		Doesn't support ECC
256  * @EDAC_RESERVED:	Reserved ECC type
257  * @EDAC_PARITY:	Detects parity errors
258  * @EDAC_EC:		Error Checking - no correction
259  * @EDAC_SECDED:	Single bit error correction, Double detection
260  * @EDAC_S2ECD2ED:	Chipkill x2 devices - do these exist?
261  * @EDAC_S4ECD4ED:	Chipkill x4 devices
262  * @EDAC_S8ECD8ED:	Chipkill x8 devices
263  * @EDAC_S16ECD16ED:	Chipkill x16 devices
264  */
265 enum edac_type {
266 	EDAC_UNKNOWN =	0,
267 	EDAC_NONE,
268 	EDAC_RESERVED,
269 	EDAC_PARITY,
270 	EDAC_EC,
271 	EDAC_SECDED,
272 	EDAC_S2ECD2ED,
273 	EDAC_S4ECD4ED,
274 	EDAC_S8ECD8ED,
275 	EDAC_S16ECD16ED,
276 };
277 
278 #define EDAC_FLAG_UNKNOWN	BIT(EDAC_UNKNOWN)
279 #define EDAC_FLAG_NONE		BIT(EDAC_NONE)
280 #define EDAC_FLAG_PARITY	BIT(EDAC_PARITY)
281 #define EDAC_FLAG_EC		BIT(EDAC_EC)
282 #define EDAC_FLAG_SECDED	BIT(EDAC_SECDED)
283 #define EDAC_FLAG_S2ECD2ED	BIT(EDAC_S2ECD2ED)
284 #define EDAC_FLAG_S4ECD4ED	BIT(EDAC_S4ECD4ED)
285 #define EDAC_FLAG_S8ECD8ED	BIT(EDAC_S8ECD8ED)
286 #define EDAC_FLAG_S16ECD16ED	BIT(EDAC_S16ECD16ED)
287 
288 /**
289  * enum scrub_type - scrubbing capabilities
290  * @SCRUB_UNKNOWN:		Unknown if scrubber is available
291  * @SCRUB_NONE:			No scrubber
292  * @SCRUB_SW_PROG:		SW progressive (sequential) scrubbing
293  * @SCRUB_SW_SRC:		Software scrub only errors
294  * @SCRUB_SW_PROG_SRC:		Progressive software scrub from an error
295  * @SCRUB_SW_TUNABLE:		Software scrub frequency is tunable
296  * @SCRUB_HW_PROG:		HW progressive (sequential) scrubbing
297  * @SCRUB_HW_SRC:		Hardware scrub only errors
298  * @SCRUB_HW_PROG_SRC:		Progressive hardware scrub from an error
299  * @SCRUB_HW_TUNABLE:		Hardware scrub frequency is tunable
300  */
301 enum scrub_type {
302 	SCRUB_UNKNOWN =	0,
303 	SCRUB_NONE,
304 	SCRUB_SW_PROG,
305 	SCRUB_SW_SRC,
306 	SCRUB_SW_PROG_SRC,
307 	SCRUB_SW_TUNABLE,
308 	SCRUB_HW_PROG,
309 	SCRUB_HW_SRC,
310 	SCRUB_HW_PROG_SRC,
311 	SCRUB_HW_TUNABLE
312 };
313 
314 #define SCRUB_FLAG_SW_PROG	BIT(SCRUB_SW_PROG)
315 #define SCRUB_FLAG_SW_SRC	BIT(SCRUB_SW_SRC)
316 #define SCRUB_FLAG_SW_PROG_SRC	BIT(SCRUB_SW_PROG_SRC)
317 #define SCRUB_FLAG_SW_TUN	BIT(SCRUB_SW_SCRUB_TUNABLE)
318 #define SCRUB_FLAG_HW_PROG	BIT(SCRUB_HW_PROG)
319 #define SCRUB_FLAG_HW_SRC	BIT(SCRUB_HW_SRC)
320 #define SCRUB_FLAG_HW_PROG_SRC	BIT(SCRUB_HW_PROG_SRC)
321 #define SCRUB_FLAG_HW_TUN	BIT(SCRUB_HW_TUNABLE)
322 
323 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
324 
325 /* EDAC internal operation states */
326 #define	OP_ALLOC		0x100
327 #define OP_RUNNING_POLL		0x201
328 #define OP_RUNNING_INTERRUPT	0x202
329 #define OP_RUNNING_POLL_INTR	0x203
330 #define OP_OFFLINE		0x300
331 
332 /**
333  * enum edac_mc_layer_type - memory controller hierarchy layer
334  *
335  * @EDAC_MC_LAYER_BRANCH:	memory layer is named "branch"
336  * @EDAC_MC_LAYER_CHANNEL:	memory layer is named "channel"
337  * @EDAC_MC_LAYER_SLOT:		memory layer is named "slot"
338  * @EDAC_MC_LAYER_CHIP_SELECT:	memory layer is named "chip select"
339  * @EDAC_MC_LAYER_ALL_MEM:	memory layout is unknown. All memory is mapped
340  *				as a single memory area. This is used when
341  *				retrieving errors from a firmware driven driver.
342  *
343  * This enum is used by the drivers to tell edac_mc_sysfs what name should
344  * be used when describing a memory stick location.
345  */
346 enum edac_mc_layer_type {
347 	EDAC_MC_LAYER_BRANCH,
348 	EDAC_MC_LAYER_CHANNEL,
349 	EDAC_MC_LAYER_SLOT,
350 	EDAC_MC_LAYER_CHIP_SELECT,
351 	EDAC_MC_LAYER_ALL_MEM,
352 };
353 
354 /**
355  * struct edac_mc_layer - describes the memory controller hierarchy
356  * @type:		layer type
357  * @size:		number of components per layer. For example,
358  *			if the channel layer has two channels, size = 2
359  * @is_virt_csrow:	This layer is part of the "csrow" when old API
360  *			compatibility mode is enabled. Otherwise, it is
361  *			a channel
362  */
363 struct edac_mc_layer {
364 	enum edac_mc_layer_type	type;
365 	unsigned		size;
366 	bool			is_virt_csrow;
367 };
368 
369 /*
370  * Maximum number of layers used by the memory controller to uniquely
371  * identify a single memory stick.
372  * NOTE: Changing this constant requires not only to change the constant
373  * below, but also to change the existing code at the core, as there are
374  * some code there that are optimized for 3 layers.
375  */
376 #define EDAC_MAX_LAYERS		3
377 
378 struct dimm_info {
379 	struct device dev;
380 
381 	char label[EDAC_MC_LABEL_LEN + 1];	/* DIMM label on motherboard */
382 
383 	/* Memory location data */
384 	unsigned int location[EDAC_MAX_LAYERS];
385 
386 	struct mem_ctl_info *mci;	/* the parent */
387 	unsigned int idx;		/* index within the parent dimm array */
388 
389 	u32 grain;		/* granularity of reported error in bytes */
390 	enum dev_type dtype;	/* memory device type */
391 	enum mem_type mtype;	/* memory dimm type */
392 	enum edac_type edac_mode;	/* EDAC mode for this dimm */
393 
394 	u32 nr_pages;			/* number of pages on this dimm */
395 
396 	unsigned int csrow, cschannel;	/* Points to the old API data */
397 
398 	u16 smbios_handle;              /* Handle for SMBIOS type 17 */
399 
400 	u32 ce_count;
401 	u32 ue_count;
402 };
403 
404 /**
405  * struct rank_info - contains the information for one DIMM rank
406  *
407  * @chan_idx:	channel number where the rank is (typically, 0 or 1)
408  * @ce_count:	number of correctable errors for this rank
409  * @csrow:	A pointer to the chip select row structure (the parent
410  *		structure). The location of the rank is given by
411  *		the (csrow->csrow_idx, chan_idx) vector.
412  * @dimm:	A pointer to the DIMM structure, where the DIMM label
413  *		information is stored.
414  *
415  * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
416  *	  This is a bad assumption, but it makes this patch easier. Later
417  *	  patches in this series will fix this issue.
418  */
419 struct rank_info {
420 	int chan_idx;
421 	struct csrow_info *csrow;
422 	struct dimm_info *dimm;
423 
424 	u32 ce_count;		/* Correctable Errors for this csrow */
425 };
426 
427 struct csrow_info {
428 	struct device dev;
429 
430 	/* Used only by edac_mc_find_csrow_by_page() */
431 	unsigned long first_page;	/* first page number in csrow */
432 	unsigned long last_page;	/* last page number in csrow */
433 	unsigned long page_mask;	/* used for interleaving -
434 					 * 0UL for non intlv */
435 
436 	int csrow_idx;			/* the chip-select row */
437 
438 	u32 ue_count;		/* Uncorrectable Errors for this csrow */
439 	u32 ce_count;		/* Correctable Errors for this csrow */
440 
441 	struct mem_ctl_info *mci;	/* the parent */
442 
443 	/* channel information for this csrow */
444 	u32 nr_channels;
445 	struct rank_info **channels;
446 };
447 
448 /*
449  * struct errcount_attribute - used to store the several error counts
450  */
451 struct errcount_attribute_data {
452 	int n_layers;
453 	int pos[EDAC_MAX_LAYERS];
454 	int layer0, layer1, layer2;
455 };
456 
457 /**
458  * struct edac_raw_error_desc - Raw error report structure
459  * @grain:			minimum granularity for an error report, in bytes
460  * @error_count:		number of errors of the same type
461  * @type:			severity of the error (CE/UE/Fatal)
462  * @top_layer:			top layer of the error (layer[0])
463  * @mid_layer:			middle layer of the error (layer[1])
464  * @low_layer:			low layer of the error (layer[2])
465  * @page_frame_number:		page where the error happened
466  * @offset_in_page:		page offset
467  * @syndrome:			syndrome of the error (or 0 if unknown or if
468  * 				the syndrome is not applicable)
469  * @msg:			error message
470  * @location:			location of the error
471  * @label:			label of the affected DIMM(s)
472  * @other_detail:		other driver-specific detail about the error
473  */
474 struct edac_raw_error_desc {
475 	char location[LOCATION_SIZE];
476 	char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
477 	long grain;
478 
479 	u16 error_count;
480 	enum hw_event_mc_err_type type;
481 	int top_layer;
482 	int mid_layer;
483 	int low_layer;
484 	unsigned long page_frame_number;
485 	unsigned long offset_in_page;
486 	unsigned long syndrome;
487 	const char *msg;
488 	const char *other_detail;
489 };
490 
491 /* MEMORY controller information structure
492  */
493 struct mem_ctl_info {
494 	struct device			dev;
495 	struct bus_type			*bus;
496 
497 	struct list_head link;	/* for global list of mem_ctl_info structs */
498 
499 	struct module *owner;	/* Module owner of this control struct */
500 
501 	unsigned long mtype_cap;	/* memory types supported by mc */
502 	unsigned long edac_ctl_cap;	/* Mem controller EDAC capabilities */
503 	unsigned long edac_cap;	/* configuration capabilities - this is
504 				 * closely related to edac_ctl_cap.  The
505 				 * difference is that the controller may be
506 				 * capable of s4ecd4ed which would be listed
507 				 * in edac_ctl_cap, but if channels aren't
508 				 * capable of s4ecd4ed then the edac_cap would
509 				 * not have that capability.
510 				 */
511 	unsigned long scrub_cap;	/* chipset scrub capabilities */
512 	enum scrub_type scrub_mode;	/* current scrub mode */
513 
514 	/* Translates sdram memory scrub rate given in bytes/sec to the
515 	   internal representation and configures whatever else needs
516 	   to be configured.
517 	 */
518 	int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
519 
520 	/* Get the current sdram memory scrub rate from the internal
521 	   representation and converts it to the closest matching
522 	   bandwidth in bytes/sec.
523 	 */
524 	int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
525 
526 
527 	/* pointer to edac checking routine */
528 	void (*edac_check) (struct mem_ctl_info * mci);
529 
530 	/*
531 	 * Remaps memory pages: controller pages to physical pages.
532 	 * For most MC's, this will be NULL.
533 	 */
534 	/* FIXME - why not send the phys page to begin with? */
535 	unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
536 					   unsigned long page);
537 	int mc_idx;
538 	struct csrow_info **csrows;
539 	unsigned int nr_csrows, num_cschannel;
540 
541 	/*
542 	 * Memory Controller hierarchy
543 	 *
544 	 * There are basically two types of memory controller: the ones that
545 	 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
546 	 * All old memory controllers enumerate memories per rank, but most
547 	 * of the recent drivers enumerate memories per DIMM, instead.
548 	 * When the memory controller is per rank, csbased is true.
549 	 */
550 	unsigned int n_layers;
551 	struct edac_mc_layer *layers;
552 	bool csbased;
553 
554 	/*
555 	 * DIMM info. Will eventually remove the entire csrows_info some day
556 	 */
557 	unsigned int tot_dimms;
558 	struct dimm_info **dimms;
559 
560 	/*
561 	 * FIXME - what about controllers on other busses? - IDs must be
562 	 * unique.  dev pointer should be sufficiently unique, but
563 	 * BUS:SLOT.FUNC numbers may not be unique.
564 	 */
565 	struct device *pdev;
566 	const char *mod_name;
567 	const char *ctl_name;
568 	const char *dev_name;
569 	void *pvt_info;
570 	unsigned long start_time;	/* mci load start time (in jiffies) */
571 
572 	/*
573 	 * drivers shouldn't access those fields directly, as the core
574 	 * already handles that.
575 	 */
576 	u32 ce_noinfo_count, ue_noinfo_count;
577 	u32 ue_mc, ce_mc;
578 
579 	struct completion complete;
580 
581 	/* Additional top controller level attributes, but specified
582 	 * by the low level driver.
583 	 *
584 	 * Set by the low level driver to provide attributes at the
585 	 * controller level.
586 	 * An array of structures, NULL terminated
587 	 *
588 	 * If attributes are desired, then set to array of attributes
589 	 * If no attributes are desired, leave NULL
590 	 */
591 	const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
592 
593 	/* work struct for this MC */
594 	struct delayed_work work;
595 
596 	/*
597 	 * Used to report an error - by being at the global struct
598 	 * makes the memory allocated by the EDAC core
599 	 */
600 	struct edac_raw_error_desc error_desc;
601 
602 	/* the internal state of this controller instance */
603 	int op_state;
604 
605 	struct dentry *debugfs;
606 	u8 fake_inject_layer[EDAC_MAX_LAYERS];
607 	bool fake_inject_ue;
608 	u16 fake_inject_count;
609 };
610 
611 #define mci_for_each_dimm(mci, dimm)				\
612 	for ((dimm) = (mci)->dimms[0];				\
613 	     (dimm);						\
614 	     (dimm) = (dimm)->idx + 1 < (mci)->tot_dimms	\
615 		     ? (mci)->dimms[(dimm)->idx + 1]		\
616 		     : NULL)
617 
618 /**
619  * edac_get_dimm - Get DIMM info from a memory controller given by
620  *                 [layer0,layer1,layer2] position
621  *
622  * @mci:	MC descriptor struct mem_ctl_info
623  * @layer0:	layer0 position
624  * @layer1:	layer1 position. Unused if n_layers < 2
625  * @layer2:	layer2 position. Unused if n_layers < 3
626  *
627  * For 1 layer, this function returns "dimms[layer0]";
628  *
629  * For 2 layers, this function is similar to allocating a two-dimensional
630  * array and returning "dimms[layer0][layer1]";
631  *
632  * For 3 layers, this function is similar to allocating a tri-dimensional
633  * array and returning "dimms[layer0][layer1][layer2]";
634  */
edac_get_dimm(struct mem_ctl_info * mci,int layer0,int layer1,int layer2)635 static inline struct dimm_info *edac_get_dimm(struct mem_ctl_info *mci,
636 	int layer0, int layer1, int layer2)
637 {
638 	int index;
639 
640 	if (layer0 < 0
641 	    || (mci->n_layers > 1 && layer1 < 0)
642 	    || (mci->n_layers > 2 && layer2 < 0))
643 		return NULL;
644 
645 	index = layer0;
646 
647 	if (mci->n_layers > 1)
648 		index = index * mci->layers[1].size + layer1;
649 
650 	if (mci->n_layers > 2)
651 		index = index * mci->layers[2].size + layer2;
652 
653 	if (index < 0 || index >= mci->tot_dimms)
654 		return NULL;
655 
656 	if (WARN_ON_ONCE(mci->dimms[index]->idx != index))
657 		return NULL;
658 
659 	return mci->dimms[index];
660 }
661 #endif /* _LINUX_EDAC_H_ */
662