1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Driver for Microchip Pulse Density Microphone Controller (PDMC) interfaces
4 //
5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries
6 //
7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
8
9 #include <dt-bindings/sound/microchip,pdmc.h>
10
11 #include <linux/clk.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/regmap.h>
15
16 #include <sound/core.h>
17 #include <sound/dmaengine_pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/tlv.h>
20
21 /*
22 * ---- PDMC Register map ----
23 */
24 #define MCHP_PDMC_CR 0x00 /* Control Register */
25 #define MCHP_PDMC_MR 0x04 /* Mode Register */
26 #define MCHP_PDMC_CFGR 0x08 /* Configuration Register */
27 #define MCHP_PDMC_RHR 0x0C /* Receive Holding Register */
28 #define MCHP_PDMC_IER 0x14 /* Interrupt Enable Register */
29 #define MCHP_PDMC_IDR 0x18 /* Interrupt Disable Register */
30 #define MCHP_PDMC_IMR 0x1C /* Interrupt Mask Register */
31 #define MCHP_PDMC_ISR 0x20 /* Interrupt Status Register */
32 #define MCHP_PDMC_VER 0x50 /* Version Register */
33
34 /*
35 * ---- Control Register (Write-only) ----
36 */
37 #define MCHP_PDMC_CR_SWRST BIT(0) /* Software Reset */
38
39 /*
40 * ---- Mode Register (Read/Write) ----
41 */
42 #define MCHP_PDMC_MR_PDMCEN_MASK GENMASK(3, 0)
43 #define MCHP_PDMC_MR_PDMCEN(ch) (BIT(ch) & MCHP_PDMC_MR_PDMCEN_MASK)
44
45 #define MCHP_PDMC_MR_OSR_MASK GENMASK(17, 16)
46 #define MCHP_PDMC_MR_OSR64 (1 << 16)
47 #define MCHP_PDMC_MR_OSR128 (2 << 16)
48 #define MCHP_PDMC_MR_OSR256 (3 << 16)
49
50 #define MCHP_PDMC_MR_SINCORDER_MASK GENMASK(23, 20)
51 #define MCHP_PDMC_MR_SINCORDER(order) (((order) << 20) & \
52 MCHP_PDMC_MR_SINCORDER_MASK)
53
54 #define MCHP_PDMC_MR_SINC_OSR_MASK GENMASK(27, 24)
55 #define MCHP_PDMC_MR_SINC_OSR_DIS (0 << 24)
56 #define MCHP_PDMC_MR_SINC_OSR_8 (1 << 24)
57 #define MCHP_PDMC_MR_SINC_OSR_16 (2 << 24)
58 #define MCHP_PDMC_MR_SINC_OSR_32 (3 << 24)
59 #define MCHP_PDMC_MR_SINC_OSR_64 (4 << 24)
60 #define MCHP_PDMC_MR_SINC_OSR_128 (5 << 24)
61 #define MCHP_PDMC_MR_SINC_OSR_256 (6 << 24)
62
63 #define MCHP_PDMC_MR_CHUNK_MASK GENMASK(31, 28)
64 #define MCHP_PDMC_MR_CHUNK(chunk) (((chunk) << 28) & \
65 MCHP_PDMC_MR_CHUNK_MASK)
66
67 /*
68 * ---- Configuration Register (Read/Write) ----
69 */
70 #define MCHP_PDMC_CFGR_BSSEL_MASK (BIT(0) | BIT(2) | BIT(4) | BIT(6))
71 #define MCHP_PDMC_CFGR_BSSEL(ch) BIT((ch) * 2)
72
73 #define MCHP_PDMC_CFGR_PDMSEL_MASK (BIT(16) | BIT(18) | BIT(20) | BIT(22))
74 #define MCHP_PDMC_CFGR_PDMSEL(ch) BIT((ch) * 2 + 16)
75
76 /*
77 * ---- Interrupt Enable/Disable/Mask/Status Registers ----
78 */
79 #define MCHP_PDMC_IR_RXRDY BIT(0)
80 #define MCHP_PDMC_IR_RXEMPTY BIT(1)
81 #define MCHP_PDMC_IR_RXFULL BIT(2)
82 #define MCHP_PDMC_IR_RXCHUNK BIT(3)
83 #define MCHP_PDMC_IR_RXUDR BIT(4)
84 #define MCHP_PDMC_IR_RXOVR BIT(5)
85
86 /*
87 * ---- Version Register (Read-only) ----
88 */
89 #define MCHP_PDMC_VER_VERSION GENMASK(11, 0)
90
91 #define MCHP_PDMC_MAX_CHANNELS 4
92 #define MCHP_PDMC_DS_NO 2
93 #define MCHP_PDMC_EDGE_NO 2
94
95 struct mic_map {
96 int ds_pos;
97 int clk_edge;
98 };
99
100 struct mchp_pdmc_chmap {
101 struct snd_pcm_chmap_elem *chmap;
102 struct mchp_pdmc *dd;
103 struct snd_pcm *pcm;
104 struct snd_kcontrol *kctl;
105 };
106
107 struct mchp_pdmc {
108 struct mic_map channel_mic_map[MCHP_PDMC_MAX_CHANNELS];
109 struct device *dev;
110 struct snd_dmaengine_dai_dma_data addr;
111 struct regmap *regmap;
112 struct clk *pclk;
113 struct clk *gclk;
114 u32 pdmcen;
115 int mic_no;
116 int sinc_order;
117 bool audio_filter_en;
118 u8 gclk_enabled:1;
119 };
120
121 static const char *const mchp_pdmc_sinc_filter_order_text[] = {
122 "1", "2", "3", "4", "5"
123 };
124
125 static const unsigned int mchp_pdmc_sinc_filter_order_values[] = {
126 1, 2, 3, 4, 5,
127 };
128
129 static const struct soc_enum mchp_pdmc_sinc_filter_order_enum = {
130 .items = ARRAY_SIZE(mchp_pdmc_sinc_filter_order_text),
131 .texts = mchp_pdmc_sinc_filter_order_text,
132 .values = mchp_pdmc_sinc_filter_order_values,
133 };
134
mchp_pdmc_sinc_order_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)135 static int mchp_pdmc_sinc_order_get(struct snd_kcontrol *kcontrol,
136 struct snd_ctl_elem_value *uvalue)
137 {
138 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
139 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
140 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
141 unsigned int item;
142
143 item = snd_soc_enum_val_to_item(e, dd->sinc_order);
144 uvalue->value.enumerated.item[0] = item;
145
146 return 0;
147 }
148
mchp_pdmc_sinc_order_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)149 static int mchp_pdmc_sinc_order_put(struct snd_kcontrol *kcontrol,
150 struct snd_ctl_elem_value *uvalue)
151 {
152 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
153 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
154 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
155 unsigned int *item = uvalue->value.enumerated.item;
156 unsigned int val;
157
158 if (item[0] >= e->items)
159 return -EINVAL;
160
161 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
162 if (val == dd->sinc_order)
163 return 0;
164
165 dd->sinc_order = val;
166
167 return 1;
168 }
169
mchp_pdmc_af_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)170 static int mchp_pdmc_af_get(struct snd_kcontrol *kcontrol,
171 struct snd_ctl_elem_value *uvalue)
172 {
173 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
174 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
175
176 uvalue->value.integer.value[0] = !!dd->audio_filter_en;
177
178 return 0;
179 }
180
mchp_pdmc_af_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * uvalue)181 static int mchp_pdmc_af_put(struct snd_kcontrol *kcontrol,
182 struct snd_ctl_elem_value *uvalue)
183 {
184 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
185 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
186 bool af = uvalue->value.integer.value[0] ? true : false;
187
188 if (dd->audio_filter_en == af)
189 return 0;
190
191 dd->audio_filter_en = af;
192
193 return 1;
194 }
195
mchp_pdmc_chmap_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)196 static int mchp_pdmc_chmap_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
197 {
198 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
199
200 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
201 uinfo->count = info->dd->mic_no;
202 uinfo->value.integer.min = 0;
203 uinfo->value.integer.max = SNDRV_CHMAP_RR; /* maxmimum 4 channels */
204 return 0;
205 }
206
207 static inline struct snd_pcm_substream *
mchp_pdmc_chmap_substream(struct mchp_pdmc_chmap * info,unsigned int idx)208 mchp_pdmc_chmap_substream(struct mchp_pdmc_chmap *info, unsigned int idx)
209 {
210 struct snd_pcm_substream *s;
211
212 for (s = info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; s; s = s->next)
213 if (s->number == idx)
214 return s;
215 return NULL;
216 }
217
mchp_pdmc_chmap_get(struct snd_pcm_substream * substream,struct mchp_pdmc_chmap * ch_info)218 static struct snd_pcm_chmap_elem *mchp_pdmc_chmap_get(struct snd_pcm_substream *substream,
219 struct mchp_pdmc_chmap *ch_info)
220 {
221 struct snd_pcm_chmap_elem *map;
222
223 for (map = ch_info->chmap; map->channels; map++) {
224 if (map->channels == substream->runtime->channels)
225 return map;
226 }
227 return NULL;
228 }
229
mchp_pdmc_chmap_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)230 static int mchp_pdmc_chmap_ctl_get(struct snd_kcontrol *kcontrol,
231 struct snd_ctl_elem_value *ucontrol)
232 {
233 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
234 struct mchp_pdmc *dd = info->dd;
235 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
236 struct snd_pcm_substream *substream;
237 const struct snd_pcm_chmap_elem *map;
238 int i;
239 u32 cfgr_val = 0;
240
241 if (!info->chmap)
242 return -EINVAL;
243 substream = mchp_pdmc_chmap_substream(info, idx);
244 if (!substream)
245 return -ENODEV;
246 memset(ucontrol->value.integer.value, 0, sizeof(long) * info->dd->mic_no);
247 if (!substream->runtime)
248 return 0; /* no channels set */
249
250 map = mchp_pdmc_chmap_get(substream, info);
251 if (!map)
252 return -EINVAL;
253
254 for (i = 0; i < map->channels; i++) {
255 int map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO :
256 map->map[i] - SNDRV_CHMAP_FL;
257
258 /* make sure the reported channel map is the real one, so write the map */
259 if (dd->channel_mic_map[map_idx].ds_pos)
260 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
261 if (dd->channel_mic_map[map_idx].clk_edge)
262 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
263
264 ucontrol->value.integer.value[i] = map->map[i];
265 }
266
267 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
268
269 return 0;
270 }
271
mchp_pdmc_chmap_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)272 static int mchp_pdmc_chmap_ctl_put(struct snd_kcontrol *kcontrol,
273 struct snd_ctl_elem_value *ucontrol)
274 {
275 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
276 struct mchp_pdmc *dd = info->dd;
277 unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
278 struct snd_pcm_substream *substream;
279 struct snd_pcm_chmap_elem *map;
280 u32 cfgr_val = 0;
281 int i;
282
283 if (!info->chmap)
284 return -EINVAL;
285 substream = mchp_pdmc_chmap_substream(info, idx);
286 if (!substream)
287 return -ENODEV;
288
289 map = mchp_pdmc_chmap_get(substream, info);
290 if (!map)
291 return -EINVAL;
292
293 for (i = 0; i < map->channels; i++) {
294 int map_idx;
295
296 map->map[i] = ucontrol->value.integer.value[i];
297 map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO :
298 map->map[i] - SNDRV_CHMAP_FL;
299
300 /* configure IP for the desired channel map */
301 if (dd->channel_mic_map[map_idx].ds_pos)
302 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
303 if (dd->channel_mic_map[map_idx].clk_edge)
304 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
305 }
306
307 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
308
309 return 0;
310 }
311
mchp_pdmc_chmap_ctl_private_free(struct snd_kcontrol * kcontrol)312 static void mchp_pdmc_chmap_ctl_private_free(struct snd_kcontrol *kcontrol)
313 {
314 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
315
316 info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = NULL;
317 kfree(info);
318 }
319
mchp_pdmc_chmap_ctl_tlv(struct snd_kcontrol * kcontrol,int op_flag,unsigned int size,unsigned int __user * tlv)320 static int mchp_pdmc_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
321 unsigned int size, unsigned int __user *tlv)
322 {
323 struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
324 const struct snd_pcm_chmap_elem *map;
325 unsigned int __user *dst;
326 int c, count = 0;
327
328 if (!info->chmap)
329 return -EINVAL;
330 if (size < 8)
331 return -ENOMEM;
332 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
333 return -EFAULT;
334 size -= 8;
335 dst = tlv + 2;
336 for (map = info->chmap; map->channels; map++) {
337 int chs_bytes = map->channels * 4;
338
339 if (size < 8)
340 return -ENOMEM;
341 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
342 put_user(chs_bytes, dst + 1))
343 return -EFAULT;
344 dst += 2;
345 size -= 8;
346 count += 8;
347 if (size < chs_bytes)
348 return -ENOMEM;
349 size -= chs_bytes;
350 count += chs_bytes;
351 for (c = 0; c < map->channels; c++) {
352 if (put_user(map->map[c], dst))
353 return -EFAULT;
354 dst++;
355 }
356 }
357 if (put_user(count, tlv + 1))
358 return -EFAULT;
359 return 0;
360 }
361
362 static const struct snd_kcontrol_new mchp_pdmc_snd_controls[] = {
363 SOC_SINGLE_BOOL_EXT("Audio Filter", 0, &mchp_pdmc_af_get, &mchp_pdmc_af_put),
364 {
365 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
366 .name = "SINC Filter Order",
367 .info = snd_soc_info_enum_double,
368 .get = mchp_pdmc_sinc_order_get,
369 .put = mchp_pdmc_sinc_order_put,
370 .private_value = (unsigned long)&mchp_pdmc_sinc_filter_order_enum,
371 },
372 };
373
mchp_pdmc_close(struct snd_soc_component * component,struct snd_pcm_substream * substream)374 static int mchp_pdmc_close(struct snd_soc_component *component,
375 struct snd_pcm_substream *substream)
376 {
377 return snd_soc_add_component_controls(component, mchp_pdmc_snd_controls,
378 ARRAY_SIZE(mchp_pdmc_snd_controls));
379 }
380
mchp_pdmc_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)381 static int mchp_pdmc_open(struct snd_soc_component *component,
382 struct snd_pcm_substream *substream)
383 {
384 int i;
385
386 /* remove controls that can't be changed at runtime */
387 for (i = 0; i < ARRAY_SIZE(mchp_pdmc_snd_controls); i++) {
388 const struct snd_kcontrol_new *control = &mchp_pdmc_snd_controls[i];
389 struct snd_ctl_elem_id id;
390 struct snd_kcontrol *kctl;
391 int err;
392
393 if (component->name_prefix)
394 snprintf(id.name, sizeof(id.name), "%s %s", component->name_prefix,
395 control->name);
396 else
397 strscpy(id.name, control->name, sizeof(id.name));
398
399 id.numid = 0;
400 id.iface = control->iface;
401 id.device = control->device;
402 id.subdevice = control->subdevice;
403 id.index = control->index;
404 kctl = snd_ctl_find_id(component->card->snd_card, &id);
405 if (!kctl) {
406 dev_err(component->dev, "Failed to find %s\n", control->name);
407 continue;
408 }
409 err = snd_ctl_remove(component->card->snd_card, kctl);
410 if (err < 0) {
411 dev_err(component->dev, "%d: Failed to remove %s\n", err,
412 control->name);
413 continue;
414 }
415 }
416
417 return 0;
418 }
419
420 static const struct snd_soc_component_driver mchp_pdmc_dai_component = {
421 .name = "mchp-pdmc",
422 .controls = mchp_pdmc_snd_controls,
423 .num_controls = ARRAY_SIZE(mchp_pdmc_snd_controls),
424 .open = &mchp_pdmc_open,
425 .close = &mchp_pdmc_close,
426 .legacy_dai_naming = 1,
427 };
428
429 static const unsigned int mchp_pdmc_1mic[] = {1};
430 static const unsigned int mchp_pdmc_2mic[] = {1, 2};
431 static const unsigned int mchp_pdmc_3mic[] = {1, 2, 3};
432 static const unsigned int mchp_pdmc_4mic[] = {1, 2, 3, 4};
433
434 static const struct snd_pcm_hw_constraint_list mchp_pdmc_chan_constr[] = {
435 {
436 .list = mchp_pdmc_1mic,
437 .count = ARRAY_SIZE(mchp_pdmc_1mic),
438 },
439 {
440 .list = mchp_pdmc_2mic,
441 .count = ARRAY_SIZE(mchp_pdmc_2mic),
442 },
443 {
444 .list = mchp_pdmc_3mic,
445 .count = ARRAY_SIZE(mchp_pdmc_3mic),
446 },
447 {
448 .list = mchp_pdmc_4mic,
449 .count = ARRAY_SIZE(mchp_pdmc_4mic),
450 },
451 };
452
mchp_pdmc_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)453 static int mchp_pdmc_startup(struct snd_pcm_substream *substream,
454 struct snd_soc_dai *dai)
455 {
456 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
457 int ret;
458
459 ret = clk_prepare_enable(dd->pclk);
460 if (ret) {
461 dev_err(dd->dev, "failed to enable the peripheral clock: %d\n", ret);
462 return ret;
463 }
464
465 regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST);
466
467 snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
468 &mchp_pdmc_chan_constr[dd->mic_no - 1]);
469
470 return 0;
471 }
472
mchp_pdmc_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)473 static void mchp_pdmc_shutdown(struct snd_pcm_substream *substream,
474 struct snd_soc_dai *dai)
475 {
476 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
477
478 clk_disable_unprepare(dd->pclk);
479 }
480
mchp_pdmc_dai_probe(struct snd_soc_dai * dai)481 static int mchp_pdmc_dai_probe(struct snd_soc_dai *dai)
482 {
483 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
484
485 snd_soc_dai_init_dma_data(dai, NULL, &dd->addr);
486
487 return 0;
488 }
489
mchp_pdmc_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)490 static int mchp_pdmc_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
491 {
492 unsigned int fmt_master = fmt & SND_SOC_DAIFMT_MASTER_MASK;
493 unsigned int fmt_format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
494
495 /* IP needs to be bitclock master */
496 if (fmt_master != SND_SOC_DAIFMT_BP_FP &&
497 fmt_master != SND_SOC_DAIFMT_BP_FC)
498 return -EINVAL;
499
500 /* IP supports only PDM interface */
501 if (fmt_format != SND_SOC_DAIFMT_PDM)
502 return -EINVAL;
503
504 return 0;
505 }
506
mchp_pdmc_mr_set_osr(int audio_filter_en,unsigned int osr)507 static u32 mchp_pdmc_mr_set_osr(int audio_filter_en, unsigned int osr)
508 {
509 if (audio_filter_en) {
510 switch (osr) {
511 case 64:
512 return MCHP_PDMC_MR_OSR64;
513 case 128:
514 return MCHP_PDMC_MR_OSR128;
515 case 256:
516 return MCHP_PDMC_MR_OSR256;
517 }
518 } else {
519 switch (osr) {
520 case 8:
521 return MCHP_PDMC_MR_SINC_OSR_8;
522 case 16:
523 return MCHP_PDMC_MR_SINC_OSR_16;
524 case 32:
525 return MCHP_PDMC_MR_SINC_OSR_32;
526 case 64:
527 return MCHP_PDMC_MR_SINC_OSR_64;
528 case 128:
529 return MCHP_PDMC_MR_SINC_OSR_128;
530 case 256:
531 return MCHP_PDMC_MR_SINC_OSR_256;
532 }
533 }
534 return 0;
535 }
536
mchp_pdmc_period_to_maxburst(int period_size)537 static inline int mchp_pdmc_period_to_maxburst(int period_size)
538 {
539 if (!(period_size % 8))
540 return 8;
541 if (!(period_size % 4))
542 return 4;
543 if (!(period_size % 2))
544 return 2;
545 return 1;
546 }
547
548 static struct snd_pcm_chmap_elem mchp_pdmc_std_chmaps[] = {
549 { .channels = 1,
550 .map = { SNDRV_CHMAP_MONO } },
551 { .channels = 2,
552 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
553 { .channels = 3,
554 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
555 SNDRV_CHMAP_RL } },
556 { .channels = 4,
557 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
558 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
559 { }
560 };
561
mchp_pdmc_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)562 static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream,
563 struct snd_pcm_hw_params *params,
564 struct snd_soc_dai *dai)
565 {
566 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
567 struct snd_soc_component *comp = dai->component;
568 unsigned long gclk_rate = 0;
569 unsigned long best_diff_rate = ~0UL;
570 unsigned int channels = params_channels(params);
571 unsigned int osr = 0, osr_start;
572 unsigned int fs = params_rate(params);
573 u32 mr_val = 0;
574 u32 cfgr_val = 0;
575 int i;
576 int ret;
577
578 dev_dbg(comp->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
579 __func__, params_rate(params), params_format(params),
580 params_width(params), params_channels(params));
581
582 if (channels > dd->mic_no) {
583 dev_err(comp->dev, "more channels %u than microphones %d\n",
584 channels, dd->mic_no);
585 return -EINVAL;
586 }
587
588 dd->pdmcen = 0;
589 for (i = 0; i < channels; i++) {
590 dd->pdmcen |= MCHP_PDMC_MR_PDMCEN(i);
591 if (dd->channel_mic_map[i].ds_pos)
592 cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
593 if (dd->channel_mic_map[i].clk_edge)
594 cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
595 }
596
597 if (dd->gclk_enabled) {
598 clk_disable_unprepare(dd->gclk);
599 dd->gclk_enabled = 0;
600 }
601
602 for (osr_start = dd->audio_filter_en ? 64 : 8;
603 osr_start <= 256 && best_diff_rate; osr_start *= 2) {
604 long round_rate;
605 unsigned long diff_rate;
606
607 round_rate = clk_round_rate(dd->gclk,
608 (unsigned long)fs * 16 * osr_start);
609 if (round_rate < 0)
610 continue;
611 diff_rate = abs((fs * 16 * osr_start) - round_rate);
612 if (diff_rate < best_diff_rate) {
613 best_diff_rate = diff_rate;
614 osr = osr_start;
615 gclk_rate = fs * 16 * osr;
616 }
617 }
618 if (!gclk_rate) {
619 dev_err(comp->dev, "invalid sampling rate: %u\n", fs);
620 return -EINVAL;
621 }
622
623 /* set the rate */
624 ret = clk_set_rate(dd->gclk, gclk_rate);
625 if (ret) {
626 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n",
627 gclk_rate, ret);
628 return ret;
629 }
630
631 mr_val |= mchp_pdmc_mr_set_osr(dd->audio_filter_en, osr);
632
633 mr_val |= MCHP_PDMC_MR_SINCORDER(dd->sinc_order);
634
635 dd->addr.maxburst = mchp_pdmc_period_to_maxburst(snd_pcm_lib_period_bytes(substream));
636 mr_val |= MCHP_PDMC_MR_CHUNK(dd->addr.maxburst);
637 dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst);
638
639 clk_prepare_enable(dd->gclk);
640 dd->gclk_enabled = 1;
641
642 snd_soc_component_update_bits(comp, MCHP_PDMC_MR,
643 MCHP_PDMC_MR_OSR_MASK |
644 MCHP_PDMC_MR_SINCORDER_MASK |
645 MCHP_PDMC_MR_SINC_OSR_MASK |
646 MCHP_PDMC_MR_CHUNK_MASK, mr_val);
647
648 snd_soc_component_write(comp, MCHP_PDMC_CFGR, cfgr_val);
649
650 return 0;
651 }
652
mchp_pdmc_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)653 static int mchp_pdmc_hw_free(struct snd_pcm_substream *substream,
654 struct snd_soc_dai *dai)
655 {
656 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
657
658 if (dd->gclk_enabled) {
659 clk_disable_unprepare(dd->gclk);
660 dd->gclk_enabled = 0;
661 }
662
663 return 0;
664 }
665
mchp_pdmc_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)666 static int mchp_pdmc_trigger(struct snd_pcm_substream *substream,
667 int cmd, struct snd_soc_dai *dai)
668 {
669 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
670 struct snd_soc_component *cpu = dai->component;
671 #ifdef DEBUG
672 u32 val;
673 #endif
674
675 switch (cmd) {
676 case SNDRV_PCM_TRIGGER_START:
677 case SNDRV_PCM_TRIGGER_RESUME:
678 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
679 /* Enable overrun and underrun error interrupts */
680 regmap_write(dd->regmap, MCHP_PDMC_IER,
681 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR);
682 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR,
683 MCHP_PDMC_MR_PDMCEN_MASK,
684 dd->pdmcen);
685 break;
686 case SNDRV_PCM_TRIGGER_STOP:
687 case SNDRV_PCM_TRIGGER_SUSPEND:
688 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
689 /* Disable overrun and underrun error interrupts */
690 regmap_write(dd->regmap, MCHP_PDMC_IDR,
691 MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR);
692 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR,
693 MCHP_PDMC_MR_PDMCEN_MASK, 0);
694 break;
695 default:
696 return -EINVAL;
697 }
698
699 #ifdef DEBUG
700 regmap_read(dd->regmap, MCHP_PDMC_MR, &val);
701 dev_dbg(dd->dev, "MR (0x%02x): 0x%08x\n", MCHP_PDMC_MR, val);
702 regmap_read(dd->regmap, MCHP_PDMC_CFGR, &val);
703 dev_dbg(dd->dev, "CFGR (0x%02x): 0x%08x\n", MCHP_PDMC_CFGR, val);
704 regmap_read(dd->regmap, MCHP_PDMC_IMR, &val);
705 dev_dbg(dd->dev, "IMR (0x%02x): 0x%08x\n", MCHP_PDMC_IMR, val);
706 #endif
707
708 return 0;
709 }
710
711 static const struct snd_soc_dai_ops mchp_pdmc_dai_ops = {
712 .set_fmt = mchp_pdmc_set_fmt,
713 .startup = mchp_pdmc_startup,
714 .shutdown = mchp_pdmc_shutdown,
715 .hw_params = mchp_pdmc_hw_params,
716 .hw_free = mchp_pdmc_hw_free,
717 .trigger = mchp_pdmc_trigger,
718 };
719
mchp_pdmc_add_chmap_ctls(struct snd_pcm * pcm,struct mchp_pdmc * dd)720 static int mchp_pdmc_add_chmap_ctls(struct snd_pcm *pcm, struct mchp_pdmc *dd)
721 {
722 struct mchp_pdmc_chmap *info;
723 struct snd_kcontrol_new knew = {
724 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
725 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
726 SNDRV_CTL_ELEM_ACCESS_TLV_READ |
727 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK,
728 .info = mchp_pdmc_chmap_ctl_info,
729 .get = mchp_pdmc_chmap_ctl_get,
730 .put = mchp_pdmc_chmap_ctl_put,
731 .tlv.c = mchp_pdmc_chmap_ctl_tlv,
732 };
733 int err;
734
735 if (WARN_ON(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl))
736 return -EBUSY;
737 info = kzalloc(sizeof(*info), GFP_KERNEL);
738 if (!info)
739 return -ENOMEM;
740 info->pcm = pcm;
741 info->dd = dd;
742 info->chmap = mchp_pdmc_std_chmaps;
743 knew.name = "Capture Channel Map";
744 knew.device = pcm->device;
745 knew.count = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream_count;
746 info->kctl = snd_ctl_new1(&knew, info);
747 if (!info->kctl) {
748 kfree(info);
749 return -ENOMEM;
750 }
751 info->kctl->private_free = mchp_pdmc_chmap_ctl_private_free;
752 err = snd_ctl_add(pcm->card, info->kctl);
753 if (err < 0)
754 return err;
755 pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = info->kctl;
756 return 0;
757 }
758
mchp_pdmc_pcm_new(struct snd_soc_pcm_runtime * rtd,struct snd_soc_dai * dai)759 static int mchp_pdmc_pcm_new(struct snd_soc_pcm_runtime *rtd,
760 struct snd_soc_dai *dai)
761 {
762 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
763 int ret;
764
765 ret = mchp_pdmc_add_chmap_ctls(rtd->pcm, dd);
766 if (ret < 0) {
767 dev_err(dd->dev, "failed to add channel map controls: %d\n", ret);
768 return ret;
769 }
770
771 return 0;
772 }
773
774 static struct snd_soc_dai_driver mchp_pdmc_dai = {
775 .probe = mchp_pdmc_dai_probe,
776 .capture = {
777 .stream_name = "Capture",
778 .channels_min = 1,
779 .channels_max = 4,
780 .rate_min = 8000,
781 .rate_max = 192000,
782 .rates = SNDRV_PCM_RATE_KNOT,
783 .formats = SNDRV_PCM_FMTBIT_S24_LE,
784 },
785 .ops = &mchp_pdmc_dai_ops,
786 .pcm_new = &mchp_pdmc_pcm_new,
787 };
788
789 /* PDMC interrupt handler */
mchp_pdmc_interrupt(int irq,void * dev_id)790 static irqreturn_t mchp_pdmc_interrupt(int irq, void *dev_id)
791 {
792 struct mchp_pdmc *dd = (struct mchp_pdmc *)dev_id;
793 u32 isr, msr, pending;
794 irqreturn_t ret = IRQ_NONE;
795
796 regmap_read(dd->regmap, MCHP_PDMC_ISR, &isr);
797 regmap_read(dd->regmap, MCHP_PDMC_IMR, &msr);
798
799 pending = isr & msr;
800 dev_dbg(dd->dev, "ISR (0x%02x): 0x%08x, IMR (0x%02x): 0x%08x, pending: 0x%08x\n",
801 MCHP_PDMC_ISR, isr, MCHP_PDMC_IMR, msr, pending);
802 if (!pending)
803 return IRQ_NONE;
804
805 if (pending & MCHP_PDMC_IR_RXUDR) {
806 dev_warn(dd->dev, "underrun detected\n");
807 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXUDR);
808 ret = IRQ_HANDLED;
809 }
810 if (pending & MCHP_PDMC_IR_RXOVR) {
811 dev_warn(dd->dev, "overrun detected\n");
812 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXOVR);
813 ret = IRQ_HANDLED;
814 }
815
816 return ret;
817 }
818
819 /* regmap configuration */
mchp_pdmc_readable_reg(struct device * dev,unsigned int reg)820 static bool mchp_pdmc_readable_reg(struct device *dev, unsigned int reg)
821 {
822 switch (reg) {
823 case MCHP_PDMC_MR:
824 case MCHP_PDMC_CFGR:
825 case MCHP_PDMC_IMR:
826 case MCHP_PDMC_ISR:
827 case MCHP_PDMC_VER:
828 return true;
829 default:
830 return false;
831 }
832 }
833
mchp_pdmc_writeable_reg(struct device * dev,unsigned int reg)834 static bool mchp_pdmc_writeable_reg(struct device *dev, unsigned int reg)
835 {
836 switch (reg) {
837 case MCHP_PDMC_CR:
838 case MCHP_PDMC_MR:
839 case MCHP_PDMC_CFGR:
840 case MCHP_PDMC_IER:
841 case MCHP_PDMC_IDR:
842 return true;
843 default:
844 return false;
845 }
846 }
847
mchp_pdmc_precious_reg(struct device * dev,unsigned int reg)848 static bool mchp_pdmc_precious_reg(struct device *dev, unsigned int reg)
849 {
850 switch (reg) {
851 case MCHP_PDMC_RHR:
852 case MCHP_PDMC_ISR:
853 return true;
854 default:
855 return false;
856 }
857 }
858
859 static const struct regmap_config mchp_pdmc_regmap_config = {
860 .reg_bits = 32,
861 .reg_stride = 4,
862 .val_bits = 32,
863 .max_register = MCHP_PDMC_VER,
864 .readable_reg = mchp_pdmc_readable_reg,
865 .writeable_reg = mchp_pdmc_writeable_reg,
866 .precious_reg = mchp_pdmc_precious_reg,
867 };
868
mchp_pdmc_dt_init(struct mchp_pdmc * dd)869 static int mchp_pdmc_dt_init(struct mchp_pdmc *dd)
870 {
871 struct device_node *np = dd->dev->of_node;
872 bool mic_ch[MCHP_PDMC_DS_NO][MCHP_PDMC_EDGE_NO] = {0};
873 int i;
874 int ret;
875
876 if (!np) {
877 dev_err(dd->dev, "device node not found\n");
878 return -EINVAL;
879 }
880
881 dd->mic_no = of_property_count_u32_elems(np, "microchip,mic-pos");
882 if (dd->mic_no < 0) {
883 dev_err(dd->dev, "failed to get microchip,mic-pos: %d",
884 dd->mic_no);
885 return dd->mic_no;
886 }
887 if (!dd->mic_no || dd->mic_no % 2 ||
888 dd->mic_no / 2 > MCHP_PDMC_MAX_CHANNELS) {
889 dev_err(dd->dev, "invalid array length for microchip,mic-pos: %d",
890 dd->mic_no);
891 return -EINVAL;
892 }
893
894 dd->mic_no /= 2;
895
896 dev_info(dd->dev, "%d PDM microphones declared\n", dd->mic_no);
897
898 /*
899 * by default, we consider the order of microphones in
900 * microchip,mic-pos to be the same with the channel mapping;
901 * 1st microphone channel 0, 2nd microphone channel 1, etc.
902 */
903 for (i = 0; i < dd->mic_no; i++) {
904 int ds;
905 int edge;
906
907 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2,
908 &ds);
909 if (ret) {
910 dev_err(dd->dev,
911 "failed to get value no %d value from microchip,mic-pos: %d",
912 i * 2, ret);
913 return ret;
914 }
915 if (ds >= MCHP_PDMC_DS_NO) {
916 dev_err(dd->dev,
917 "invalid DS index in microchip,mic-pos array: %d",
918 ds);
919 return -EINVAL;
920 }
921
922 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2 + 1,
923 &edge);
924 if (ret) {
925 dev_err(dd->dev,
926 "failed to get value no %d value from microchip,mic-pos: %d",
927 i * 2 + 1, ret);
928 return ret;
929 }
930
931 if (edge != MCHP_PDMC_CLK_POSITIVE &&
932 edge != MCHP_PDMC_CLK_NEGATIVE) {
933 dev_err(dd->dev,
934 "invalid edge in microchip,mic-pos array: %d", edge);
935 return -EINVAL;
936 }
937 if (mic_ch[ds][edge]) {
938 dev_err(dd->dev,
939 "duplicated mic (DS %d, edge %d) in microchip,mic-pos array",
940 ds, edge);
941 return -EINVAL;
942 }
943 mic_ch[ds][edge] = true;
944 dd->channel_mic_map[i].ds_pos = ds;
945 dd->channel_mic_map[i].clk_edge = edge;
946 }
947
948 return 0;
949 }
950
951 /* used to clean the channel index found on RHR's MSB */
mchp_pdmc_process(struct snd_pcm_substream * substream,int channel,unsigned long hwoff,void * buf,unsigned long bytes)952 static int mchp_pdmc_process(struct snd_pcm_substream *substream,
953 int channel, unsigned long hwoff,
954 void *buf, unsigned long bytes)
955 {
956 struct snd_pcm_runtime *runtime = substream->runtime;
957 u8 *dma_ptr = runtime->dma_area + hwoff +
958 channel * (runtime->dma_bytes / runtime->channels);
959 u8 *dma_ptr_end = dma_ptr + bytes;
960 unsigned int sample_size = samples_to_bytes(runtime, 1);
961
962 for (; dma_ptr < dma_ptr_end; dma_ptr += sample_size)
963 *dma_ptr = 0;
964
965 return 0;
966 }
967
968 static struct snd_dmaengine_pcm_config mchp_pdmc_config = {
969 .process = mchp_pdmc_process,
970 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
971 };
972
mchp_pdmc_probe(struct platform_device * pdev)973 static int mchp_pdmc_probe(struct platform_device *pdev)
974 {
975 struct device *dev = &pdev->dev;
976 struct mchp_pdmc *dd;
977 struct resource *res;
978 void __iomem *io_base;
979 u32 version;
980 int irq;
981 int ret;
982
983 dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL);
984 if (!dd)
985 return -ENOMEM;
986
987 dd->dev = &pdev->dev;
988 ret = mchp_pdmc_dt_init(dd);
989 if (ret < 0)
990 return ret;
991
992 irq = platform_get_irq(pdev, 0);
993 if (irq < 0)
994 return irq;
995
996 dd->pclk = devm_clk_get(dev, "pclk");
997 if (IS_ERR(dd->pclk)) {
998 ret = PTR_ERR(dd->pclk);
999 dev_err(dev, "failed to get peripheral clock: %d\n", ret);
1000 return ret;
1001 }
1002
1003 dd->gclk = devm_clk_get(dev, "gclk");
1004 if (IS_ERR(dd->gclk)) {
1005 ret = PTR_ERR(dd->gclk);
1006 dev_err(dev, "failed to get GCK: %d\n", ret);
1007 return ret;
1008 }
1009
1010 io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1011 if (IS_ERR(io_base)) {
1012 ret = PTR_ERR(io_base);
1013 dev_err(dev, "failed to remap register memory: %d\n", ret);
1014 return ret;
1015 }
1016
1017 dd->regmap = devm_regmap_init_mmio(dev, io_base,
1018 &mchp_pdmc_regmap_config);
1019 if (IS_ERR(dd->regmap)) {
1020 ret = PTR_ERR(dd->regmap);
1021 dev_err(dev, "failed to init register map: %d\n", ret);
1022 return ret;
1023 }
1024
1025 ret = devm_request_irq(dev, irq, mchp_pdmc_interrupt, 0,
1026 dev_name(&pdev->dev), (void *)dd);
1027 if (ret < 0) {
1028 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
1029 irq, ret);
1030 return ret;
1031 }
1032
1033 /* by default audio filter is enabled and the SINC Filter order
1034 * will be set to the recommended value, 3
1035 */
1036 dd->audio_filter_en = true;
1037 dd->sinc_order = 3;
1038
1039 dd->addr.addr = (dma_addr_t)res->start + MCHP_PDMC_RHR;
1040 platform_set_drvdata(pdev, dd);
1041
1042 /* register platform */
1043 ret = devm_snd_dmaengine_pcm_register(dev, &mchp_pdmc_config, 0);
1044 if (ret) {
1045 dev_err(dev, "could not register platform: %d\n", ret);
1046 return ret;
1047 }
1048
1049 ret = devm_snd_soc_register_component(dev, &mchp_pdmc_dai_component,
1050 &mchp_pdmc_dai, 1);
1051 if (ret) {
1052 dev_err(dev, "could not register CPU DAI: %d\n", ret);
1053 return ret;
1054 }
1055
1056 /* print IP version */
1057 regmap_read(dd->regmap, MCHP_PDMC_VER, &version);
1058 dev_info(dd->dev, "hw version: %#lx\n",
1059 version & MCHP_PDMC_VER_VERSION);
1060
1061 return 0;
1062 }
1063
1064 static const struct of_device_id mchp_pdmc_of_match[] = {
1065 {
1066 .compatible = "microchip,sama7g5-pdmc",
1067 }, {
1068 /* sentinel */
1069 }
1070 };
1071 MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match);
1072
1073 static struct platform_driver mchp_pdmc_driver = {
1074 .driver = {
1075 .name = "mchp-pdmc",
1076 .of_match_table = of_match_ptr(mchp_pdmc_of_match),
1077 .pm = &snd_soc_pm_ops,
1078 },
1079 .probe = mchp_pdmc_probe,
1080 };
1081 module_platform_driver(mchp_pdmc_driver);
1082
1083 MODULE_DESCRIPTION("Microchip PDMC driver under ALSA SoC architecture");
1084 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
1085 MODULE_LICENSE("GPL v2");
1086